Changeset 66342 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Mar 29, 2017 4:22:31 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

114278

Message:

IEM: Converted grp 9 to tables and fixed cmpxchg16b/8b prefix handling.

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-decoding-1.c32 (modified) (7 diffs)
• bs3-cpu-instr-2-template.c (modified) (7 diffs)
• bs3-cpu-instr-2-template.mac (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32

@@ -406 +406 @@
 CPUDECODE1UDTST const g_aUdTest2Byte_0f[] =
 {
-#if 1
+#if 0
     {  UD_T_EXACT, 2, { 0x0f, 0x04 }, UD_F_ANY_PFX },
     {  UD_T_EXACT, 2, { 0x0f, 0x0a }, UD_F_ANY_PFX },
@@ -536 +536 @@
     {  UD_T_MODRM_MR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_RR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-    //{  UD_T_MODRM_MR1, 2, { 0x0f, 0xc7 }, xxxx }, - cmpxchg8b/16b is weird, needs special testcase.
+    //{  UD_T_MODRM_MR1, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX | UD_F_NOT_RZ_PFX | UD_F_NOT_LK_PFX }, - cmpxchg8b ignores everything. @
     {  UD_T_MODRM_RR1, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_MR2, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
@@ -546 +546 @@
     {  UD_T_MODRM_MR5, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_RR5, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-    //{  UD_T_MODRM_MR0, 2, { 0x0f, 0xc7 }, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX |  },
-    {  UD_T_MODRM_RR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-#if 1
+    {  UD_T_MODRM_MR6, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX }, /* f2? */
+    {  UD_T_MODRM_RR6, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX }, /* (rdrand Rv) */
+    {  UD_T_MODRM_MR7, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX }, /* vmptrst Mq (f2?); */
+    {  UD_T_MODRM_RR7, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX }, /* rdrand Rv; rdpid Rd/q (f2,66??); */
+#if 0
     {  UD_T_MODRM, 2, { 0x0f, 0xd0 }, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX },
     {  UD_T_MODRM, 2, { 0x0f, 0xd1 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX },
@@ -1290 +1292 @@
 
 
+#if 0
+/**
+ * Checks how prefixes affects cmpxchg8b and cmpxchg16b
+ *
+ * The thing here is that the intel opcode tables indicates that the 66 and f3
+ * prefixes encodings are reserved and causes \#UD, where AMD doesn't.  Seems
+ * though that the f2, f3 and 66 prefixes are ignored on skylake intel.  Need to
+ * make sure this is the case, also in 64-bit mode and for the 16b version.
+ */
+static void DecodeCmpXchg8bVs16b(void)
+{
+    uint8_t BS3_FAR *pbPages;
+
+    /* Check that the instructions are supported. */
+    if (   !(g_uBs3CpuDetected & BS3CPU_F_CPUID)
+        || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_CX8))
+    {
+        Bs3TestSkipped("not supported");
+        return;
+    }
+
+    /* Setup a guarded page. */
+    pbPages = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32);
+    if (pbPages)
+    {
+
+        Bs3MemGuardedTestPageFree(pbPages);
+    }
+    else
+        Bs3TestFailed("Failed to allocate two pages!\n");
+}
+#endif
+
+
 /**
  * Checks various prefix encodings with the MOVBE and CRC32 instructions to try
@@ -1661 +1697 @@
     Bs3TestPrintf("g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
 
-#if 1
+#if 0
     Bs3TestSub("CMPPS, CMPPD, CMPSS, CMPSD");
     DecodeCmppsCmppdCmpssCmpsd();
@@ -1668 +1704 @@
     DecodeMovbeVsCrc32();
 #endif
+
+    //Bs3TestSub("CMPXCHG8B/16B");
+    //DecodeCmpXchg8bVs16b();
 
 #if 1
@@ -1673 +1712 @@
     DecodeUdEdgeTest(g_aUdTest2Byte_0f, RT_ELEMENTS(g_aUdTest2Byte_0f));
 #endif
-#if 1
+#if 0
     Bs3TestSub("3 byte undefined opcodes 0f 38");
     DecodeUdEdgeTest(g_aUdTest3Byte_0f_38, RT_ELEMENTS(g_aUdTest3Byte_0f_38));

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c

@@ -54 +54 @@
 extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2);
 extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2);
 # endif
 #endif
@@ -550 +556 @@
     PRTUINT128U     pau128       = RT_ALIGN_PT(&au128[0], sizeof(RTUINT128U), PRTUINT128U);
     bool const      fSupportCX16 = RT_BOOL(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16);
-    unsigned        iLocked;
     unsigned        iFlags;
     unsigned        offBuf;
     unsigned        iMatch;
+    unsigned        iWorker;
+    static struct
+    {
+        bool        fLocked;
+        uint8_t     offUd2;
+        FNBS3FAR   *pfnWorker;
+    } const s_aWorkers[] =
+    {
+        {   false,  4,  BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2) },
+        {   false,  5,  BS3_CMN_NM(bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2) },
+        {   false,  5,  BS3_CMN_NM(bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2) },
+        {   false,  5,  BS3_CMN_NM(bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2) },
+        {   true, 1+4,  BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2) },
+        {   true, 1+5,  BS3_CMN_NM(bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2) },
+        {   true, 1+5,  BS3_CMN_NM(bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2) },
+        {   true, 1+5,  BS3_CMN_NM(bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2) },
+    };
 
     /* Ensure the structures are allocated before we sample the stack pointer. */
@@ -572 +594 @@
      */
     g_usBs3TestStep = 0;
-    Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2));
-    for (iLocked = 0; iLocked < 2; iLocked++)
-    {
+    for (iWorker = 0; iWorker < RT_ELEMENTS(s_aWorkers); iWorker++)
+    {
+        Bs3RegCtxSetRipCsFromCurPtr(&Ctx, s_aWorkers[iWorker].pfnWorker);
+
         /*
          * One loop with all status flags set, and one with them clear.
@@ -604 +627 @@
                     Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
                     g_usBs3TestStep++;
-                    //Bs3TestPrintf("Test: iFlags=%d offBuf=%d iMatch=%u\n", iFlags, offBuf, iMatch);
+                    //Bs3TestPrintf("Test: iFlags=%d offBuf=%d iMatch=%u iWorker=%u\n", iFlags, offBuf, iMatch, iWorker);
                     bExpectXcpt = X86_XCPT_UD;
                     if (fSupportCX16)
@@ -622 +645 @@
                             else
                                 ExpectCtx.rflags.u32 = Ctx.rflags.u32 & ~X86_EFL_ZF;
-                            ExpectCtx.rip.u = Ctx.rip.u + 4 + (iLocked & 1);
+                            ExpectCtx.rip.u = Ctx.rip.u + s_aWorkers[iWorker].offUd2;
                         }
                         ExpectCtx.rflags.u32 |= X86_EFL_RF;
@@ -632 +655 @@
                         if (TrapFrame.bXcpt != bExpectXcpt)
                             Bs3TestFailedF("Expected bXcpt=#%x, got %#x (%#x)", bExpectXcpt, TrapFrame.bXcpt, TrapFrame.uErrCd);
-                        Bs3TestFailedF("^^^ iLocked=%d iFlags=%d offBuf=%d iMatch=%u\n", iLocked, iFlags, offBuf, iMatch);
+                        Bs3TestFailedF("^^^ iWorker=%d iFlags=%d offBuf=%d iMatch=%u\n", iWorker, iFlags, offBuf, iMatch);
                         ASMHalt();
                     }
@@ -642 +665 @@
             Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS;
         }
-        Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2));
     }
 
     return 0;
-
 }
 # endif /* ARCH_BITS == 64 */

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac

@@ -101 +101 @@
 AssertCompile(.again - BS3_LAST_LABEL == 5)
 BS3_PROC_END_CMN   bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        o16 cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        db 0f0h, 066h
+        cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 6)
+BS3_PROC_END_CMN   bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        repz cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        db 0f0h, 0f3h
+        cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 6)
+BS3_PROC_END_CMN   bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        repnz cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        db 0f0h, 0f2h
+        cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 6)
+BS3_PROC_END_CMN   bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
+
+;; @todo figure out this fudge. sigh.
+times (348) db 0cch ; fudge to avoid 'rderr' during boot.
+
  %endif ; TMPL_BITS == 64