VirtualBox

Changeset 66920 in vbox


Ignore:
Timestamp:
May 16, 2017 7:21:21 PM (8 years ago)
Author:
vboxsync
Message:

IEM: Implemented movss Uss,Hss,Vss (VEX.F3.0F 11 mod=3) and movss Md,Vss (VEX.F3.0F 11 mod!=3).

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/disopcode.h

    r66906 r66920  
    10831083#define OP_PARM_UqHi            (OP_PARM_U+OP_PARM_dq)
    10841084#define OP_PARM_Uss             (OP_PARM_U+OP_PARM_ss)
     1085#define OP_PARM_Uss_WO          OP_PARM_Uss             /**< Annotates write only operand. */
    10851086#define OP_PARM_Usd             (OP_PARM_U+OP_PARM_sd)
    10861087#define OP_PARM_Vdq_WO          OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are accessed. */

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r66909 r66920  
    1149311493    } while (0)
    1149411494
     11495#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
     11496    do { PX86XSAVEAREA   pXStateTmp     = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
     11497         uintptr_t const iYRegSrcTmp    = (a_iYRegSrc); \
     11498         (a_u32Dst) = pXStateTmp->x87.aXMM[iYRegSrcTmp].au32[0]; \
     11499    } while (0)
    1149511500#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
    1149611501    do { PX86XSAVEAREA   pXStateTmp     = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \
    1149711502         uintptr_t const iYRegSrcTmp    = (a_iYRegSrc); \
    11498          (a_u64Dst).au64[0] = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[0]; \
     11503         (a_u64Dst) = pXStateTmp->x87.aXMM[iYRegSrcTmp].au64[0]; \
    1149911504    } while (0)
    1150011505#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

    r66909 r66920  
    233233    'UqHi':         ( 'IDX_UseModRM',       'rm',     '%Uq',  'UqHi',    ),
    234234    'Uss':          ( 'IDX_UseModRM',       'rm',     '%Uss', 'Uss',     ),
     235    'Uss_WO':       ( 'IDX_UseModRM',       'rm',     '%Uss', 'Uss',     ),
    235236    'Usd':          ( 'IDX_UseModRM',       'rm',     '%Usd', 'Usd',     ),
    236237    'Nq':           ( 'IDX_UseModRM',       'rm',     '%Qq',  'Nq',      ),

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h

    r66919 r66920  
    306306         * @opgroup     og_avx_simdfp_datamove
    307307         * @opxcpttype  5
    308          * @opfunction  iemOp_vmovss_Vss_Hss_Wss
     308         * @opfunction  iemOp_vmovsd_Vsd_Hsd_Wsd
    309309         * @optest      op1=1 op2=2 -> op1=2
    310310         * @optest      op1=0 op2=-22 -> op1=-22
    … …  
    415415 * @optest      op1=1 op2=2 -> op1=2
    416416 * @optest      op1=0 op2=-22 -> op1=-22
    417  * @oponly
    418417 */
    419418FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
    … …  
    483482}
    484483
    485 /**
    486  * @ opcode      0x11
    487  * @ oppfx       0xf3
    488  * @ opcpuid     sse
    489  * @ opgroup     og_sse_simdfp_datamove
    490  * @ opxcpttype  5
    491  * @ optest      op1=1 op2=2 -> op1=2
    492  * @ optest      op1=0 op2=-22 -> op1=-22
    493  */
    494 FNIEMOP_STUB(iemOp_vmovss_Wss_Hx_Vss);
    495 //FNIEMOP_DEF(iemOp_vmovss_Wss_Hx_Vss)
    496 //{
    497 //    IEMOP_MNEMONIC2(MR, VMOVSS, vmovss, Wss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
    498 //    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
    499 //    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
    500 //    {
    501 //        /*
    502 //         * Register, register.
    503 //         */
    504 //        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
    505 //        IEM_MC_BEGIN(0, 1);
    506 //        IEM_MC_LOCAL(uint32_t,                  uSrc);
    507 //
    508 //        IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
    509 //        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
    510 //        IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
    511 //        IEM_MC_STORE_XREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
    512 //
    513 //        IEM_MC_ADVANCE_RIP();
    514 //        IEM_MC_END();
    515 //    }
    516 //    else
    517 //    {
    518 //        /*
    519 //         * Memory, register.
    520 //         */
    521 //        IEM_MC_BEGIN(0, 2);
    522 //        IEM_MC_LOCAL(uint32_t,                  uSrc);
    523 //        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
    524 //
    525 //        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
    526 //        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
    527 //        IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
    528 //        IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
    529 //
    530 //        IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
    531 //        IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
    532 //
    533 //        IEM_MC_ADVANCE_RIP();
    534 //        IEM_MC_END();
    535 //    }
    536 //    return VINF_SUCCESS;
    537 //}
     484
     485FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
     486{
     487    Assert(pVCpu->iem.s.uVexLength <= 1);
     488    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     489    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     490    {
     491        /**
     492         * @opcode      0x11
     493         * @oppfx       0xf3
     494         * @opcodesub   11 mr/reg
     495         * @opcpuid     avx
     496         * @opgroup     og_avx_simdfp_datamerge
     497         * @opxcpttype  5
     498         * @optest      op1=1 op2=0  op3=2    -> op1=2
     499         * @optest      op1=0 op2=0  op3=-22  -> op1=0xffffffea
     500         * @optest      op1=3 op2=-1 op3=0x77 -> op1=-4294967177
     501         */
     502        IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HdqCss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     503        IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
     504        IEM_MC_BEGIN(0, 0);
     505
     506        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
     507        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
     508        IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
     509                                           ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
     510                                           pVCpu->iem.s.uVex3rdReg /*Hss*/);
     511        IEM_MC_ADVANCE_RIP();
     512        IEM_MC_END();
     513    }
     514    else
     515    {
     516        /**
     517         * @opdone
     518         * @opcode      0x11
     519         * @oppfx       0xf3
     520         * @opcodesub   11 mr/reg
     521         * @opcpuid     avx
     522         * @opgroup     og_avx_simdfp_datamove
     523         * @opxcpttype  5
     524         * @opfunction  iemOp_vmovss_Vss_Hss_Wss
     525         * @optest      op1=1 op2=2 -> op1=2
     526         * @optest      op1=0 op2=-22 -> op1=-22
     527         */
     528        IEMOP_MNEMONIC2(VEX_MR, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     529        IEM_MC_BEGIN(0, 2);
     530        IEM_MC_LOCAL(uint32_t,                  uSrc);
     531        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     532
     533        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
     534        IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
     535        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
     536        IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
     537
     538        IEM_MC_FETCH_YREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
     539        IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
     540
     541        IEM_MC_ADVANCE_RIP();
     542        IEM_MC_END();
     543    }
     544
     545    return VINF_SUCCESS;
     546}
    538547
    539548
    … …  
    30693078
    30703079    /* 0x10 */  iemOp_vmovups_Vps_Wps,      iemOp_vmovupd_Vpd_Wpd,      iemOp_vmovss_Vss_Hss_Wss,   iemOp_vmovsd_Vsd_Hsd_Wsd,
    3071     /* 0x11 */  iemOp_vmovups_Wps_Vps,      iemOp_vmovupd_Wpd_Vpd,      iemOp_vmovss_Wss_Hx_Vss,    iemOp_vmovsd_Wsd_Hx_Vsd,
     3080    /* 0x11 */  iemOp_vmovups_Wps_Vps,      iemOp_vmovupd_Wpd_Vpd,      iemOp_vmovss_Wss_Hss_Vss,   iemOp_vmovsd_Wsd_Hx_Vsd,
    30723081    /* 0x12 */  iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx,    iemOp_vmovddup_Vx_Wx,
    30733082    /* 0x13 */  iemOp_vmovlps_Mq_Vq,        iemOp_vmovlpd_Mq_Vq,        iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66919 r66920  
    12771277{
    12781278    pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
    1279     return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg, cbOp, cbMissalign, enmLocation);
     1279    return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg & 7, cbOp, cbMissalign, enmLocation);
     1280}
     1281
     1282
     1283/** Also encodes idxField of the register operand using idxFieldBase.   */
     1284static unsigned BS3_NEAR_CODE
     1285Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off,
     1286                                                uint8_t iReg, uint8_t cbMissalign)
     1287{
     1288    pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
     1289    return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg & 7, pThis->aOperands[pThis->iRmOp].cbOp, cbMissalign,
     1290                                    pThis->aOperands[pThis->iRmOp].enmLocation);
    12801291}
    12811292
    … …  
    24152426
    24162427
    2417 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething(PBS3CG1STATE pThis, unsigned iEncoding)
     2428static unsigned BS3_NEAR_CODE
     2429Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_OR_Vice_Versa(PBS3CG1STATE pThis, unsigned iEncoding)
    24182430{
    24192431    unsigned off;
    … …  
    24242436            off = Bs3Cg1InsertOpcodes(pThis, off);
    24252437            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2426             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2427             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    2428             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2438            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2439            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 0;
     2440            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24292441            break;
    24302442        case 1:
    … …  
    24322444            off = Bs3Cg1InsertOpcodes(pThis, off);
    24332445            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 3, 1);
    2434             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 3;
    2435             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 7;
    2436             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2446            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 3;
     2447            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 7;
     2448            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24372449            break;
    24382450        case 2:
    … …  
    24432455                off = Bs3Cg1InsertOpcodes(pThis, off);
    24442456                pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 3, 2);
    2445                 pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 11;
    2446                 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 15;
    2447                 pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 2;
     2457                pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 11;
     2458                pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 15;
     2459                pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 2;
    24482460                break;
    24492461            }
    … …  
    24542466            off = Bs3Cg1InsertOpcodes(pThis, off);
    24552467            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2456             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2457             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    2458             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2468            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2469            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 0;
     2470            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24592471            break;
    24602472        case 4:
    … …  
    24622474            off = Bs3Cg1InsertOpcodes(pThis, off);
    24632475            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2464             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2465             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    2466             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2476            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2477            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 0;
     2478            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24672479            break;
    24682480        case 5:
    … …  
    24702482            off = Bs3Cg1InsertOpcodes(pThis, off);
    24712483            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2472             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2473             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 3;
    2474             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2484            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2485            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + 3;
     2486            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24752487            break;
    24762488        case 6:
    … …  
    24782490            off = Bs3Cg1InsertOpcodes(pThis, off);
    24792491            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2480             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2481             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7);
    2482             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2492            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2493            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7);
     2494            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24832495            break;
    24842496        case 7:
    … …  
    24862498            off = Bs3Cg1InsertOpcodes(pThis, off);
    24872499            pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1);
    2488             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
    2489             pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7);
    2490             pThis->aOperands[2].idxField = pThis->aOperands[2].idxFieldBase + 1;
     2500            pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2;
     2501            pThis->aOperands[1            ].idxField = pThis->aOperands[1            ].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7);
     2502            pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1;
    24912503            break;
    24922504        default:
    … …  
    24982510
    24992511
    2500 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig(PBS3CG1STATE pThis, unsigned iEncoding)
     2512/**
     2513 * Wip - VEX.W ignored.
     2514 * Lig - VEX.L ignored.
     2515 */
     2516static unsigned BS3_NEAR_CODE
     2517Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
    25012518{
    25022519    unsigned off;
    … …  
    25062523            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    25072524            off = Bs3Cg1InsertOpcodes(pThis, off);
    2508             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 0, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2509             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 0;
     2525            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
    25102526            break;
    25112527        case 1:
    25122528            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/);
    25132529            off = Bs3Cg1InsertOpcodes(pThis, off);
    2514             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 7, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2515             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 7;
     2530            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7, 0);
    25162531            break;
    25172532        case 2:
    … …  
    25212536                off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 0 /*~R*/);
    25222537                off = Bs3Cg1InsertOpcodes(pThis, off);
    2523                 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 7, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2524                 pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 15;
     2538                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
    25252539                break;
    25262540            }
    … …  
    25312545            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
    25322546            off = Bs3Cg1InsertOpcodes(pThis, off);
    2533             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 0, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2534             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 0;
     2547            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
    25352548            pThis->fInvalidEncoding = true;
    25362549            break;
    … …  
    25382551            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    25392552            off = Bs3Cg1InsertOpcodes(pThis, off);
    2540             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 1, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2541             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 1;
     2553            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
    25422554            break;
    25432555        case 5:
    25442556            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    25452557            off = Bs3Cg1InsertOpcodes(pThis, off);
    2546             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 1, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2547             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 1;
     2558            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
    25482559            break;
    25492560        case 6:
    25502561            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    25512562            off = Bs3Cg1InsertOpcodes(pThis, off);
    2552             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 5, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2553             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 5;
     2563            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
    25542564            break;
    25552565        case 7:
    … …  
    25592569                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    25602570                off = Bs3Cg1InsertOpcodes(pThis, off);
    2561                 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 5, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2562                 pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 13;
     2571                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
    25632572                break;
    25642573            }
    … …  
    25712580                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    25722581                off = Bs3Cg1InsertOpcodes(pThis, off);
    2573                 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 1, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2574                 pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 1;
     2582                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
    25752583                break;
    25762584            }
    … …  
    25832591                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    25842592                off = Bs3Cg1InsertOpcodes(pThis, off);
    2585                 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2586                 pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 2;
     2593                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
    25872594                break;
    25882595            }
    … …  
    25932600            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    25942601            off = Bs3Cg1InsertOpcodes(pThis, off);
    2595             off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 5, pThis->aOperands[1].cbOp, 0, BS3CG1OPLOC_MEM);
    2596             pThis->aOperands[0].idxField = pThis->aOperands[0].idxFieldBase + 5;
     2602            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
    25972603            pThis->fInvalidEncoding = true;
    25982604            break;
    … …  
    30263032#ifdef BS3CG1_WITH_VEX
    30273033        case BS3CG1ENC_VEX_MODRM_VssZx_WO_Md:
    3028             return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig(pThis, iEncoding);
     3034            return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa(pThis, iEncoding);
    30293035
    30303036        case BS3CG1ENC_VEX_MODRM_Md_WO:
    … …  
    32763282
    32773283        case BS3CG1ENC_VEX_MODRM_VssZx_WO_Md:
    3278             pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig;
     3284            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
    32793285            pThis->iRmOp             = 1;
    32803286            pThis->iRegOp            = 0;
    … …  
    32883294
    32893295        case BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss:
    3290             pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething;
     3296            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_OR_Vice_Versa;
    32913297            pThis->iRegOp            = 0;
    32923298            pThis->iRmOp             = 2;
    … …  
    33033309
    33043310        case BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq:
    3305             pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig;
     3311            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
    33063312            pThis->iRmOp             = 1;
    33073313            pThis->iRegOp            = 0;
    … …  
    33153321
    33163322        case BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd:
    3317             pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething;
     3323            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_OR_Vice_Versa;
    33183324            pThis->iRegOp            = 0;
    33193325            pThis->iRmOp             = 2;
    … …  
    33273333            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
    33283334            pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
     3335            break;
     3336
     3337        case BS3CG1ENC_VEX_MODRM_Md_WO_Vss:
     3338            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
     3339            pThis->iRmOp             = 0;
     3340            pThis->iRegOp            = 1;
     3341            pThis->aOperands[0].cbOp = 4;
     3342            pThis->aOperands[1].cbOp = 4;
     3343            pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_MEM_WO;
     3344            pThis->aOperands[1].enmLocation  = BS3CG1OPLOC_CTX;
     3345            pThis->aOperands[0].idxFieldBase = BS3CG1DST_INVALID;
     3346            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_DW0;
     3347            break;
     3348
     3349        case BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss:
     3350            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_OR_Vice_Versa;
     3351            pThis->iRegOp            = 2;
     3352            pThis->iRmOp             = 0;
     3353            pThis->aOperands[0].cbOp = 16;
     3354            pThis->aOperands[1].cbOp = 16;
     3355            pThis->aOperands[2].cbOp = 4;
     3356            pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
     3357            pThis->aOperands[1].enmLocation  = BS3CG1OPLOC_CTX;
     3358            pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
     3359            pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
     3360            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
     3361            pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
    33293362            break;
    33303363

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

    r66919 r66920  
    6868    BS3CG1OP_UqHi,
    6969    BS3CG1OP_Uss,
     70    BS3CG1OP_Uss_WO,
    7071    BS3CG1OP_Usd,
     72    BS3CG1OP_Usd_WO,
    7173    BS3CG1OP_Vss,
    7274    BS3CG1OP_Vss_WO,
    … …  
    153155    BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
    154156    BS3CG1ENC_VEX_MODRM_Md_WO,
     157    BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
     158    BS3CG1ENC_VEX_MODRM_Md_WO_Vsd,
     159    BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss,
     160    BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd,
    155161    BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
    156162    BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
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