Changeset 66935 in vbox
- Timestamp:
- May 17, 2017 12:09:30 PM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 115465
- Location:
- trunk
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/disopcode.h
r66932 r66935 782 782 OP_VMOVHLPS, 783 783 OP_VMOVLPS, 784 OP_VMOVLPD, 784 785 /** @} */ 785 786 OP_END_OF_OPCODES … … 1075 1076 #define OP_PARM_HdqCsd OP_PARM_Hx /**< Hdq register complements (high) a sd specifier (low). */ 1076 1077 #define OP_PARM_HdqCq OP_PARM_Hx /**< Hdq register complements (high) a q specifier (low). */ 1078 #define OP_PARM_HqHi OP_PARM_Hx /**< Registered referced by VEX.vvvv, bits [127:64]. */ 1077 1079 #define OP_PARM_M_RO OP_PARM_M /**< Annotates read only memory of variable operand size (xrstor). */ 1078 1080 #define OP_PARM_M_RW OP_PARM_M /**< Annotates read-write memory of variable operand size (xsave). */ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r66932 r66935 276 276 'HdqCsd': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HdqCsd', ), 277 277 'HdqCq': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HdqCq', ), 278 'HqHi': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HqHi', ), 278 279 279 280 # Immediate values. … … 673 674 sName += sWord[0].upper() + sWord[1:]; 674 675 return sName; 676 677 678 def isVexMap(self): 679 """ Returns True if a VEX map. """ 680 return self.sEncoding.startswith('vex'); 675 681 676 682 … … 1448 1454 return self._flagsToIntegerMask(self.asFlClear); 1449 1455 1456 def onlyInVexMaps(self): 1457 """ Returns True if only in VEX maps, otherwise False. (No maps -> False) """ 1458 if not self.aoMaps: 1459 return False; 1460 for oMap in self.aoMaps: 1461 if not oMap.isVexMap(): 1462 return False; 1463 return True; 1464 1465 1450 1466 1451 1467 ## All the instructions. … … 1738 1754 oInstr.sFunction = 'iemOp_' + oInstr.sStats; 1739 1755 1740 # Derive encoding from operands.1741 if oInstr.sEncoding is None:1742 if not oInstr.aoOperands:1743 if oInstr.fUnused and oInstr.sSubOpcode:1744 oInstr.sEncoding = 'ModR/M';1745 else:1746 oInstr.sEncoding = 'fixed';1747 elif oInstr.aoOperands[0].usesModRM():1748 if len(oInstr.aoOperands) >= 2 and oInstr.aoOperands[1].sWhere == 'vvvv':1749 oInstr.sEncoding = 'ModR/M+VEX';1750 else:1751 oInstr.sEncoding = 'ModR/M';1752 1753 1756 # 1754 1757 # Apply default map and then add the instruction to all it's groups. … … 1758 1761 for oMap in oInstr.aoMaps: 1759 1762 oMap.aoInstructions.append(oInstr); 1763 1764 # 1765 # Derive encoding from operands and maps. 1766 # 1767 if oInstr.sEncoding is None: 1768 if not oInstr.aoOperands: 1769 if oInstr.fUnused and oInstr.sSubOpcode: 1770 oInstr.sEncoding = 'VEX.ModR/M' if oInstr.onlyInVexMaps() else 'ModR/M'; 1771 else: 1772 oInstr.sEncoding = 'fixed'; 1773 elif oInstr.aoOperands[0].usesModRM(): 1774 if (len(oInstr.aoOperands) >= 2 and oInstr.aoOperands[1].sWhere == 'vvvv') \ 1775 or oInstr.onlyInVexMaps(): 1776 oInstr.sEncoding = 'VEX.ModR/M'; 1777 else: 1778 oInstr.sEncoding = 'ModR/M'; 1760 1779 1761 1780 # … … 3166 3185 3167 3186 self.doneInstructions(); 3168 self.debug('%3s stubs out of %3s instructions in %s' % (self.cTotalStubs, self.cTotalInstr, os.path.basename(self.sSrcFile),)); 3187 self.debug('%3s stubs out of %3s instructions in %s' 3188 % (self.cTotalStubs, self.cTotalInstr, os.path.basename(self.sSrcFile),)); 3169 3189 return self.printErrors(); 3170 3190 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r66932 r66935 684 684 685 685 /** 686 * @ opcode 0x12 687 * @ opcodesub !11 mr/reg 688 * @ oppfx 0x66 689 * @ opcpuid sse2 690 * @ opgroup og_sse2_pcksclr_datamove 691 * @ opxcpttype 5 692 * @ optest op1=1 op2=2 -> op1=2 693 * @ optest op1=0 op2=-42 -> op1=-42 686 * @opcode 0x12 687 * @opcodesub !11 mr/reg 688 * @oppfx 0x66 689 * @opcpuid avx 690 * @opgroup og_avx_pcksclr_datamerge 691 * @opxcpttype 5LZ 692 * @optest op2=0 op3=2 -> op1=2 693 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033 694 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9 695 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9 694 696 */ 695 FNIEMOP_STUB(iemOp_vmovlpd_Vq_Hq_Mq); 697 FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq) 698 { 699 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 700 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)) 701 { 702 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 703 704 IEM_MC_BEGIN(0, 2); 705 IEM_MC_LOCAL(uint64_t, uSrc); 706 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 707 708 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 709 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0(); 710 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 711 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 712 713 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 714 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 715 uSrc, 716 pVCpu->iem.s.uVex3rdReg /*Hq*/); 717 718 IEM_MC_ADVANCE_RIP(); 719 IEM_MC_END(); 720 return VINF_SUCCESS; 721 } 722 723 /** 724 * @opdone 725 * @opmnemonic udvex660f12m3 726 * @opcode 0x12 727 * @opcodesub 11 mr/reg 728 * @oppfx 0x66 729 * @opunused immediate 730 * @opcpuid avx 731 * @optest -> 732 */ 733 return IEMOP_RAISE_INVALID_OPCODE(); 734 } 735 736 696 737 //FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq) 697 738 //{ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r66932 r66935 533 533 #define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; } while (0) 534 534 #define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; } while (0) 535 #define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0)536 #define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0)537 #define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0)538 #define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0)535 #define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; } while (0) 536 #define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; } while (0) 537 #define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; } while (0) 538 #define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; } while (0) 539 539 540 540 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py
r66810 r66935 302 302 self.asOpcodes = oMap.asLeadOpcodes + [ '0x%02x' % (oInstr.getOpcodeByte(),) ]; 303 303 self.sEncoding = iai.g_kdEncodings[oInstr.sEncoding][0]; 304 304 305 for oOp in oInstr.aoOperands: 305 306 self.sEncoding += '_' + oOp.sType; 306 307 if oInstr.fUnused: 308 print('DEBUG: Unused Bs3Cg1Instruction: %s\n' % (oInstr.sEncoding,)); 307 309 if oInstr.sInvalidStyle == 'immediate' and oInstr.sSubOpcode: 308 310 self.sEncoding += '_MOD_EQ_3' if oInstr.sSubOpcode == '11 mr/reg' else '_MOD_NE_3'; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66932 r66935 2062 2062 off = Bs3Cg1InsertReqPrefix(pThis, 0); 2063 2063 off = Bs3Cg1InsertOpcodes(pThis, off); 2064 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding );2064 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7); 2065 2065 } 2066 2066 else … … 3143 3143 } 3144 3144 3145 3146 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding) 3147 { 3148 unsigned off; 3149 if (iEncoding < 8) 3150 { 3151 if (iEncoding & 1) 3152 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/); 3153 else 3154 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3155 off = Bs3Cg1InsertOpcodes(pThis, off); 3156 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1); 3157 } 3158 else if (iEncoding < 16) 3159 { 3160 if (iEncoding & 1) 3161 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/); 3162 else 3163 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3164 off = Bs3Cg1InsertOpcodes(pThis, off); 3165 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding & 7, 1); 3166 } 3167 else if (iEncoding < 24) 3168 { 3169 if (iEncoding & 1) 3170 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/); 3171 else 3172 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3173 off = Bs3Cg1InsertOpcodes(pThis, off); 3174 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7); 3175 } 3176 else if (iEncoding < 32) 3177 { 3178 if (iEncoding & 1) 3179 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 3) != 0 /*L*/, 1 /*~R*/); 3180 else 3181 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 3182 1 /*~B*/, (iEncoding & 4) != 0 /*W*/); 3183 off = Bs3Cg1InsertOpcodes(pThis, off); 3184 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7); 3185 } 3186 else 3187 return 0; 3188 pThis->cbCurInstr = off; 3189 3190 return iEncoding + 1; 3191 } 3192 3193 3194 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding) 3195 { 3196 unsigned off; 3197 if (iEncoding < 8) 3198 { 3199 unsigned iMod = iEncoding % 3; 3200 if (iEncoding & 1) 3201 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/); 3202 else 3203 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, (iEncoding & 2) != 0 /*L*/, 1 /*~R*/, 3204 1 /*~X*/, 1 /*~B*/, (iEncoding & 4) != 0 /*W*/); 3205 off = Bs3Cg1InsertOpcodes(pThis, off); 3206 pThis->abCurInstr[off++] = X86_MODRM_MAKE(iMod, 0, 1); 3207 if (iMod >= 1) 3208 pThis->abCurInstr[off++] = 0x7f; 3209 if (iMod == 2) 3210 { 3211 pThis->abCurInstr[off++] = 0x5f; 3212 if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode)) 3213 { 3214 pThis->abCurInstr[off++] = 0x3f; 3215 pThis->abCurInstr[off++] = 0x1f; 3216 } 3217 } 3218 } 3219 else 3220 return 0; 3221 pThis->cbCurInstr = off; 3222 return iEncoding + 1; 3223 } 3224 3145 3225 #endif /* BS3CG1_WITH_VEX */ 3146 3226 … … 3227 3307 return Bs3Cg1EncodeNext_FIXED_rAX_Iz(pThis, iEncoding); 3228 3308 3229 case BS3CG1ENC_MODRM_MOD_EQ_3:3230 return Bs3Cg1EncodeNext_MODRM_MOD_EQ_3(pThis, iEncoding);3231 case BS3CG1ENC_MODRM_MOD_NE_3:3232 return Bs3Cg1EncodeNext_MODRM_MOD_NE_3(pThis, iEncoding);3233 3234 3309 /* 3235 3310 * VEX stuff … … 3468 3543 break; 3469 3544 3545 /* Unused or invalid instructions mostly. */ 3470 3546 case BS3CG1ENC_MODRM_MOD_EQ_3: 3547 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_EQ_3; 3548 break; 3471 3549 case BS3CG1ENC_MODRM_MOD_NE_3: 3472 /* Unused or invalid instructions mostly. */3550 pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_NE_3; 3473 3551 break; 3474 3552 … … 3570 3648 break; 3571 3649 3650 case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq: 3651 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa; 3652 pThis->iRegOp = 0; 3653 pThis->iRmOp = 2; 3654 pThis->aOperands[0].cbOp = 16; 3655 pThis->aOperands[1].cbOp = 8; 3656 pThis->aOperands[2].cbOp = 8; 3657 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 3658 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; 3659 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_MEM; 3660 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0; 3661 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI; 3662 pThis->aOperands[2].idxFieldBase = BS3CG1DST_INVALID; 3663 break; 3664 3572 3665 case BS3CG1ENC_VEX_MODRM_Md_WO_Vss: 3573 3666 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa; … … 3637 3730 break; 3638 3731 3732 3733 /* Unused or invalid instructions mostly. */ 3734 case BS3CG1ENC_VEX_MODRM_MOD_EQ_3: 3735 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3; 3736 break; 3737 case BS3CG1ENC_VEX_MODRM_MOD_NE_3: 3738 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3; 3739 break; 3639 3740 3640 3741 #endif /* BS3CG1_WITH_VEX */ … … 4179 4280 /* FPU and FXSAVE format. */ 4180 4281 else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT 4181 && offField - sizeof(BS3REGCTX) < = RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]))4282 && offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15])) 4182 4283 { 4183 4284 if (!pThis->fWorkExtCtx) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r66932 r66935 64 64 BS3CG1OP_HdqCsd, 65 65 BS3CG1OP_HdqCq, 66 BS3CG1OP_HqHi, 66 67 BS3CG1OP_Nq, 67 68 BS3CG1OP_Pq_WO, … … 155 156 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi, 156 157 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq, 158 BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq, 157 159 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md, 158 160 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq, … … 169 171 BS3CG1ENC_FIXED_rAX_Iz, 170 172 173 171 174 BS3CG1ENC_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */ 172 175 BS3CG1ENC_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */ 176 BS3CG1ENC_VEX_MODRM_MOD_EQ_3, /**< Unused or invalid instruction. */ 177 BS3CG1ENC_VEX_MODRM_MOD_NE_3, /**< Unused or invalid instruction. */ 173 178 174 179 BS3CG1ENC_END
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