Changeset 67072 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- May 25, 2017 8:26:51 AM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 115735
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-generated-1-data.py (modified) (4 diffs)
-
bs3-cpu-generated-1-template.c (modified) (22 diffs)
-
bs3-cpu-generated-1.h (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py
r67040 r67072 305 305 for oOp in oInstr.aoOperands: 306 306 self.sEncoding += '_' + oOp.sType; 307 if oInstr.sSubOpcode == 'rex.w=1': self.sEncoding += '_WNZ';308 elif oInstr.sSubOpcode == 'rex.w=0': self.sEncoding += '_WZ';307 if oInstr.sSubOpcode and iai.g_kdSubOpcodes[oInstr.sSubOpcode][1]: 308 self.sEncoding += '_' + iai.g_kdSubOpcodes[oInstr.sSubOpcode][1]; 309 309 310 310 if oInstr.fUnused: … … 334 334 if 'vex_l_zero' in oInstr.dHints: 335 335 self.asFlags.append('BS3CG1INSTR_F_VEX_L_ZERO'); 336 if 'vex_l_ignored' in oInstr.dHints: 337 self.asFlags.append('BS3CG1INSTR_F_VEX_L_IGNORED'); 336 338 337 339 self.fAdvanceMnemonic = True; ##< Set by the caller. … … 367 369 return ', '.join(['(uint8_t)BS3CG1OP_%s' % (oOp.sType,) for oOp in self.oInstr.aoOperands]); 368 370 371 def getOpcodeMap(self): 372 """ Returns the opcode map number for the BS3CG1INSTR structure. """ 373 sEncoding = self.oInstr.aoMaps[0].sEncoding; 374 if sEncoding == 'legacy': return 0; 375 if sEncoding == 'vex1': return 1; 376 if sEncoding == 'vex2': return 2; 377 if sEncoding == 'vex3': return 3; 378 if sEncoding == 'xop8': return 8; 379 if sEncoding == 'xop9': return 9; 380 if sEncoding == 'xop10': return 10; 381 assert False, sEncoding; 382 return 3; 383 369 384 def getInstructionEntry(self): 370 385 """ Returns an array of BS3CG1INSTR member initializers. """ 386 assert len(self.oInstr.sMnemonic) < 16; 371 387 sOperands = ', '.join([oOp.sType for oOp in self.oInstr.aoOperands]); 372 388 if sOperands: … … 379 395 ' /* offTests = */ %s,' % (self.oTests.offTests,), 380 396 ' /* enmEncoding = */ (unsigned)%s,' % (self.sEncoding,), 397 ' /* uOpcodeMap = */ (unsigned)%s,' % (self.getOpcodeMap(),), 381 398 ' /* enmPrefixKind = */ (unsigned)%s,' % (self.sPfxKind,), 382 399 ' /* enmCpuTest = */ (unsigned)%s,' % (self.sCpu,), -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r67040 r67072 147 147 /** The encoding. */ 148 148 BS3CG1ENC enmEncoding; 149 /** The non-invalid encoding. This differsfrom enmEncoding when149 /** The non-invalid encoding. This may differ from enmEncoding when 150 150 * Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */ 151 151 BS3CG1ENC enmEncodingNonInvalid; … … 167 167 /** Whether to advance the mnemonic pointer or not. */ 168 168 uint8_t fAdvanceMnemonic; 169 /** The opcode map number. */ 170 uint8_t uOpcodeMap; 169 171 /** The number of opcode bytes. */ 170 172 uint8_t cbOpcodes; … … 275 277 /** Set by the encoding method to indicating invalid encoding. */ 276 278 bool fInvalidEncoding; 279 /** The result of Bs3Cg1CpuSetupFirst(). */ 280 bool fCpuSetupFirstResult; 277 281 278 282 /** The context we're working on. */ … … 885 889 AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END); 886 890 887 #ifdef BS3CG1_DEBUG_CTX_MOD888 891 /** Destination field names. */ 889 892 static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] = … … 1157 1160 AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END); 1158 1161 1159 #endif1160 1162 1161 1163 #if 0 … … 2596 2598 2597 2599 /** 2600 * Inserts a 3-byte VEX prefix. 2601 * 2602 * @returns New offDst value. 2603 * @param pThis The state. 2604 * @param offDst The current instruction offset. 2605 * @param uVexL The VEX.L value. 2606 * @param uVexV The VEX.V value (caller inverted it already). 2607 * @param uVexR The VEX.R value (caller inverted it already). 2608 * @param uVexX The VEX.X value (caller inverted it already). 2609 * @param uVexB The VEX.B value (caller inverted it already). 2610 * @param uVexW The VEX.W value (straight). 2611 */ 2612 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL, 2613 uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW) 2614 { 2615 uint8_t b1; 2616 uint8_t b2; 2617 b1 = uVexR << 7; 2618 b1 |= uVexX << 6; 2619 b1 |= uVexB << 5; 2620 b1 |= pThis->uOpcodeMap; 2621 b2 = uVexV << 3; 2622 b2 |= uVexW << 7; 2623 b2 |= uVexL << 2; 2624 switch (pThis->enmPrefixKind) 2625 { 2626 case BS3CG1PFXKIND_NO_F2_F3_66: b2 |= 0; break; 2627 case BS3CG1PFXKIND_REQ_66: b2 |= 1; break; 2628 case BS3CG1PFXKIND_REQ_F3: b2 |= 2; break; 2629 case BS3CG1PFXKIND_REQ_F2: b2 |= 3; break; 2630 default: 2631 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind); 2632 break; 2633 } 2634 2635 pThis->abCurInstr[offDst] = 0xc4; /* vex3 */ 2636 pThis->abCurInstr[offDst + 1] = b1; 2637 pThis->abCurInstr[offDst + 2] = b2; 2638 pThis->uVexL = uVexL; 2639 return offDst + 3; 2640 } 2641 2642 2643 /** 2598 2644 * Inserts a 2-byte VEX prefix. 2645 * 2646 * @note Will switch to 3-byte VEX prefix if uOpcodeMap isn't one. 2599 2647 * 2600 2648 * @returns New offDst value. … … 2608 2656 uint8_t uVexV, uint8_t uVexL, uint8_t uVexR) 2609 2657 { 2610 uint8_t b = uVexR << 7; 2611 b |= uVexV << 3; 2612 b |= uVexL << 2; 2613 switch (pThis->enmPrefixKind) 2614 { 2615 case BS3CG1PFXKIND_NO_F2_F3_66: b |= 0; break; 2616 case BS3CG1PFXKIND_REQ_66: b |= 1; break; 2617 case BS3CG1PFXKIND_REQ_F3: b |= 2; break; 2618 case BS3CG1PFXKIND_REQ_F2: b |= 3; break; 2619 default: 2620 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n"); 2621 break; 2622 } 2623 2624 pThis->abCurInstr[offDst] = 0xc5; /* vex2 */ 2625 pThis->abCurInstr[offDst + 1] = b; 2626 pThis->uVexL = uVexL; 2627 return offDst + 2; 2628 } 2629 2630 2631 /** 2632 * Inserts a 3-byte VEX prefix. 2633 * 2634 * @returns New offDst value. 2635 * @param pThis The state. 2636 * @param offDst The current instruction offset. 2637 * @param uVexL The VEX.L value. 2638 * @param uVexV The VEX.V value (caller inverted it already). 2639 * @param uVexR The VEX.R value (caller inverted it already). 2640 * @param uVexR The VEX.X value (caller inverted it already). 2641 * @param uVexR The VEX.B value (caller inverted it already). 2642 * @param uVexR The VEX.W value (straight). 2643 */ 2644 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL, 2645 uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW) 2646 { 2647 uint8_t b1; 2648 uint8_t b2; 2649 b1 = uVexR << 7; 2650 b1 |= uVexX << 6; 2651 b1 |= uVexB << 5; 2652 b1 |= 1; /* VEX.mmmmm = 1*/ /** @todo three byte opcode tables */ 2653 b2 = uVexV << 3; 2654 b2 |= uVexW << 7; 2655 b2 |= uVexL << 2; 2656 switch (pThis->enmPrefixKind) 2657 { 2658 case BS3CG1PFXKIND_NO_F2_F3_66: b2 |= 0; break; 2659 case BS3CG1PFXKIND_REQ_66: b2 |= 1; break; 2660 case BS3CG1PFXKIND_REQ_F3: b2 |= 2; break; 2661 case BS3CG1PFXKIND_REQ_F2: b2 |= 3; break; 2662 default: 2663 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind); 2664 break; 2665 } 2666 2667 pThis->abCurInstr[offDst] = 0xc4; /* vex3 */ 2668 pThis->abCurInstr[offDst + 1] = b1; 2669 pThis->abCurInstr[offDst + 2] = b2; 2670 pThis->uVexL = uVexL; 2671 return offDst + 3; 2658 if (pThis->uOpcodeMap == 1) 2659 { 2660 uint8_t b = uVexR << 7; 2661 b |= uVexV << 3; 2662 b |= uVexL << 2; 2663 switch (pThis->enmPrefixKind) 2664 { 2665 case BS3CG1PFXKIND_NO_F2_F3_66: b |= 0; break; 2666 case BS3CG1PFXKIND_REQ_66: b |= 1; break; 2667 case BS3CG1PFXKIND_REQ_F3: b |= 2; break; 2668 case BS3CG1PFXKIND_REQ_F2: b |= 3; break; 2669 default: 2670 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n"); 2671 break; 2672 } 2673 2674 pThis->abCurInstr[offDst] = 0xc5; /* vex2 */ 2675 pThis->abCurInstr[offDst + 1] = b; 2676 pThis->uVexL = uVexL; 2677 return offDst + 2; 2678 } 2679 return Bs3Cg1InsertVex3bPrefix(pThis, offDst, uVexV, uVexL, uVexR, 1 /*uVexX*/, 1 /*uVexB*/, 0/*uVexW*/); 2672 2680 } 2673 2681 … … 3432 3440 */ 3433 3441 static unsigned BS3_NEAR_CODE 3434 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L 0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)3442 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3435 3443 { 3436 3444 unsigned off; … … 3520 3528 return iEncoding + 1; 3521 3529 } 3530 3531 3532 /** 3533 * Wip - VEX.W ignored. 3534 */ 3535 static unsigned BS3_NEAR_CODE 3536 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding, uint8_t uVexL) 3537 { 3538 unsigned off; 3539 switch (iEncoding) 3540 { 3541 case 0: 3542 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/); 3543 off = Bs3Cg1InsertOpcodes(pThis, off); 3544 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 3545 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0; 3546 break; 3547 #if ARCH_BITS == 64 3548 case 1: 3549 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/); 3550 off = Bs3Cg1InsertOpcodes(pThis, off); 3551 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0); 3552 break; 3553 #endif 3554 case 2: 3555 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, uVexL, 1 /*~R*/); 3556 off = Bs3Cg1InsertOpcodes(pThis, off); 3557 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 3558 pThis->fInvalidEncoding = true; 3559 break; 3560 case 3: 3561 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3562 off = Bs3Cg1InsertOpcodes(pThis, off); 3563 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 3564 break; 3565 case 4: 3566 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/); 3567 off = Bs3Cg1InsertOpcodes(pThis, off); 3568 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 3569 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0; 3570 break; 3571 #if ARCH_BITS == 64 3572 case 5: 3573 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3574 off = Bs3Cg1InsertOpcodes(pThis, off); 3575 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0); 3576 break; 3577 case 6: 3578 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/); 3579 off = Bs3Cg1InsertOpcodes(pThis, off); 3580 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 3581 break; 3582 case 7: 3583 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/); 3584 off = Bs3Cg1InsertOpcodes(pThis, off); 3585 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0); 3586 break; 3587 #endif 3588 case 8: 3589 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3590 off = Bs3Cg1InsertOpcodes(pThis, off); 3591 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 3592 pThis->fInvalidEncoding = true; 3593 break; 3594 case 9: 3595 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3596 off = Bs3Cg1InsertOpcodes(pThis, off); 3597 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0); 3598 pThis->fInvalidEncoding = true; 3599 break; 3600 default: 3601 return 0; 3602 } 3603 pThis->cbCurInstr = off; 3604 return iEncoding + 1; 3605 } 3606 3607 3608 /** 3609 * Wip - VEX.W ignored. 3610 * L0 - VEX.L is zero (encoding may exist where it isn't). 3611 */ 3612 static unsigned BS3_NEAR_CODE 3613 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3614 { 3615 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 0 /*uVexL*/); 3616 } 3617 3618 3619 /** 3620 * Wip - VEX.W ignored. 3621 * L1 - VEX.L is one (encoding may exist where it isn't). 3622 */ 3623 static unsigned BS3_NEAR_CODE 3624 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3625 { 3626 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 1 /*uVexL*/); 3627 } 3628 3522 3629 3523 3630 … … 3716 3823 /** 3717 3824 * Wip = VEX.W ignored. 3718 * L 0= VEX.L must be zero.3825 * Lmbz = VEX.L must be zero. 3719 3826 */ 3720 3827 static unsigned BS3_NEAR_CODE 3721 Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L 0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)3828 Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3722 3829 { 3723 3830 unsigned off; … … 4729 4836 break; 4730 4837 4838 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0: 4839 BS3_ASSERT(!(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO)); 4840 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa; 4841 pThis->iRegOp = 0; 4842 pThis->iRmOp = 1; 4843 pThis->aOperands[0].cbOp = 16; 4844 pThis->aOperands[1].cbOp = 16; 4845 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 4846 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 4847 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0; 4848 break; 4849 4850 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1: 4851 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa; 4852 pThis->iRegOp = 0; 4853 pThis->iRmOp = 1; 4854 pThis->aOperands[0].cbOp = 32; 4855 pThis->aOperands[1].cbOp = 32; 4856 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 4857 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 4858 pThis->aOperands[0].idxFieldBase = BS3CG1DST_YMM0; 4859 break; 4860 4731 4861 case BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd: 4732 4862 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa; … … 4775 4905 4776 4906 case BS3CG1ENC_VEX_MODRM_Vq_WO_Wq: 4777 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L0_OR_ViceVersa; 4907 BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO); 4908 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa; 4778 4909 pThis->iRegOp = 0; 4779 4910 pThis->iRmOp = 1; … … 4850 4981 4851 4982 case BS3CG1ENC_VEX_MODRM_Mq_WO_Vq: 4983 BS3_ASSERT(pThis->fFlags & (BS3CG1INSTR_F_VEX_L_ZERO | BS3CG1INSTR_F_VEX_L_IGNORED)); 4852 4984 pThis->pfnEncoder = pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO 4853 ? Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L 0_OR_ViceVersa4985 ? Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa 4854 4986 : Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa; 4855 4987 pThis->iRmOp = 0; … … 4933 5065 4934 5066 case BS3CG1ENC_VEX_MODRM_Wq_WO_Vq: 4935 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L0_OR_ViceVersa; 5067 BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO); 5068 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa; 4936 5069 pThis->iRegOp = 1; 4937 5070 pThis->iRmOp = 0; … … 5542 5675 && offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15])) 5543 5676 { 5544 if (!pThis->fWorkExtCtx) 5545 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst); 5546 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX); 5677 if (pThis->fWorkExtCtx) 5678 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX); 5679 else if (!pThis->fCpuSetupFirstResult) 5680 { 5681 BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification (<=8)\n")); 5682 goto l_advance_to_next; 5683 } 5684 else 5685 return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n", 5686 idxField, g_aszBs3Cg1DstFields[idxField].sz, offField, cbDst); 5547 5687 } 5548 5688 /** @todo other FPU fields and FPU state formats. */ 5549 5689 else 5550 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x (<= 8)", cbDst, idxField, offField); 5690 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d %s offField=%#x (<= 8)", 5691 cbDst, idxField, g_aszBs3Cg1DstFields[idxField].sz, offField); 5551 5692 5552 5693 #ifdef BS3CG1_DEBUG_CTX_MOD … … 5661 5802 * Deal with larger field (FPU, SSE, AVX, ...). 5662 5803 */ 5663 else 5804 else if (pThis->fWorkExtCtx) 5664 5805 { 5665 5806 union … … 5675 5816 unsigned const offField = g_aoffBs3Cg1DstFields[idxField]; 5676 5817 unsigned iReg; 5677 5678 if (!pThis->fWorkExtCtx)5679 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);5680 5818 5681 5819 /* Copy the value into the union, doing the zero padding / extending. */ … … 5829 5967 Bs3MemCpy(pbMemCopy, PtrField.pv, cbDst); 5830 5968 } 5969 /* !pThis->fWorkExtCtx: */ 5970 else if (pThis->fCpuSetupFirstResult) 5971 return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n", 5972 idxField, g_aszBs3Cg1DstFields[idxField].sz, g_aoffBs3Cg1DstFields[idxField], cbDst); 5973 else 5974 BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification [> 8]\n")); 5831 5975 5832 5976 /* … … 6439 6583 Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic); 6440 6584 pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic; 6585 pThis->uOpcodeMap = pInstr->uOpcodeMap; 6441 6586 pThis->cOperands = pInstr->cOperands; 6442 6587 pThis->cbOpcodes = pInstr->cbOpcodes; … … 6459 6604 * Check if the CPU supports the instruction. 6460 6605 */ 6461 if ( !Bs3Cg1CpuSetupFirst(pThis) 6606 pThis->fCpuSetupFirstResult = Bs3Cg1CpuSetupFirst(pThis); 6607 if ( !pThis->fCpuSetupFirstResult 6462 6608 || (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID))) 6463 6609 fOuterInvalidInstr = true; … … 6566 6712 else 6567 6713 { 6568 Bs3TestPrintf("Bs3Cg1RunContextModifier(out): iEncoding=%u iTest=%u\n", iEncoding, pThis->iTest); 6714 Bs3TestPrintf("Bs3Cg1RunContextModifier(out): iEncoding=%u iTest=%RU32 iInstr=%u %.*s\n", 6715 iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic); 6569 6716 ASMHalt(); 6570 6717 } … … 6604 6751 else 6605 6752 { 6606 Bs3TestPrintf("Bs3Cg1RunContextModifier(in): iEncoding=%u iTest=%u\n", iEncoding, pThis->iTest); 6753 Bs3TestPrintf("Bs3Cg1RunContextModifier(in): iEncoding=%u iTest=%u iInstr=%RU32 %.*s\n", 6754 iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic); 6607 6755 ASMHalt(); 6608 6756 } -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r67040 r67072 123 123 BS3CG1OP_Mps_WO, 124 124 BS3CG1OP_Mpd_WO, 125 BS3CG1OP_Mx, 125 126 BS3CG1OP_Mx_WO, 126 127 … … 195 196 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md, 196 197 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq, 198 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0, 199 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1, 197 200 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx, 198 201 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ, … … 335 338 /** BS3CG1ENC values. */ 336 339 uint32_t enmEncoding : 10; 340 /** The VEX, EVEX or XOP opcode map number (VEX.mmmm). */ 341 uint32_t uOpcodeMap : 4; 337 342 /** BS3CG1PFXKIND values. */ 338 343 uint32_t enmPrefixKind : 4; … … 342 347 uint32_t enmXcptType : 5; 343 348 /** Currently unused bits. */ 344 uint32_t uUnused : 6;349 uint32_t uUnused : 3; 345 350 /** BS3CG1INSTR_F_XXX. */ 346 351 uint32_t fFlags; … … 366 371 /** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */ 367 372 #define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020) 373 /** VEX.L is ignored (IEMOPHINT_VEX_L_IGNORED). */ 374 #define BS3CG1INSTR_F_VEX_L_IGNORED UINT32_C(0x00000040) 368 375 /** @} */ 369 376
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