VirtualBox

Ignore:
Timestamp:
May 9, 2018 4:18:56 PM (7 years ago)
Author:
vboxsync
Message:

VMM: Nested hw.virt: Implemented saved-states for nested SVM. Bumps the CPUM and HM SSM versions.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r72085 r72178  
    53815381                }
    53825382
    5383                 /** @todo Needed when restoring saved-state when saved state support wasn't yet
    5384                  *        added. Perhaps it won't be required later. */
    5385 #if 0
    53865383                case SVM_EXIT_NPF:
    53875384                {
    53885385                    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
    5389                     if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
    5390                         return HM_SVM_VMEXIT_NESTED(pVCpu, SVM_EXIT_XCPT_14, RT_LO_U32(uExitInfo1), uExitInfo2);
    5391                     hmR0SvmSetPendingXcptPF(pVCpu, pCtx, RT_LO_U32(uExitInfo1), uExitInfo2);
    5392                     return VINF_SUCCESS;
     5386                    return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
    53935387                }
    5394 #else
    5395                 case SVM_EXIT_NPF:
    5396 #endif
     5388
    53975389                case SVM_EXIT_INIT:  /* We shouldn't get INIT signals while executing a nested-guest. */
    5398                 {
    53995390                    return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
    5400                 }
    54015391
    54025392                default:
     
    70177007{
    70187008    HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
    7019     HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
    70207009
    70217010    PVM pVM = pVCpu->CTX_SUFF(pVM);
     
    70257014
    70267015    /* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
    7027     PSVMVMCB pVmcb           = pVCpu->hm.s.svm.pVmcb;
    7028     uint32_t u32ErrCode      = pVmcb->ctrl.u64ExitInfo1;    /** @todo Make it more explicit that high bits can be non-zero. */
     7016    PSVMVMCB pVmcb           = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
    70297017    RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
     7018    uint32_t u32ErrCode      = pVmcb->ctrl.u64ExitInfo1;    /* Note! High bits in EXITINFO1 may contain additional info and are
     7019                                                               thus intentionally not copied into u32ErrCode. */
    70307020
    70317021    Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
    70327022
    7033 #ifdef VBOX_HM_WITH_GUEST_PATCHING
    7034     /* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.  */
     7023    /*
     7024     * TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
     7025     */
    70357026    if (   pVM->hm.s.fTprPatchingAllowed
    70367027        && (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
     
    70527043        }
    70537044    }
    7054 #endif
    70557045
    70567046    /*
     
    72927282    Assert(!pVM->hm.s.fNestedPaging);
    72937283
    7294 #ifdef VBOX_HM_WITH_GUEST_PATCHING
    7295     /* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
     7284    /*
     7285     * TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
     7286     */
    72967287    if (   pVM->hm.s.fTprPatchingAllowed
    72977288        && (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
     
    73177308        }
    73187309    }
    7319 #endif
    73207310
    73217311    Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
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