Changeset 72590 in vbox

Timestamp:

Jun 17, 2018 7:26:27 PM (6 years ago)

Author:

vboxsync

Message:

HM,IEM,EM: Added IEMExecDecodedRdtsc and IEMExecDecodedRdtscp for replacing incomplete EM APIs. Hooked up HM, but code not enabled yet. bugref:6973

Location:

trunk

Files:

• include/VBox/vmm/em.h (modified) (1 diff)
• include/VBox/vmm/iem.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/EMAll.cpp (modified) (2 diffs)
• src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h (modified) (4 diffs)
• src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (6 diffs)
• src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (5 diffs)

trunk/include/VBox/vmm/em.h

@@ -313 +313 @@
 #endif
 VMM_INT_DECL(int)               EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+#if 1 /** @todo Remove after testing and enabling @bugref{6973}. */
 VMM_INT_DECL(int)               EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMM_INT_DECL(int)               EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+#endif
 VMM_INT_DECL(int)               EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
-VMM_INT_DECL(int)               EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
 VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
 VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);

trunk/include/VBox/vmm/iem.h

@@ -252 +252 @@
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedInvlpg(PVMCPU pVCpu,  uint8_t cbInstr, RTGCPTR GCPtrPage);
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedInvpcid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t uType, RTGCPTR GCPtrInvpcidDesc);
+VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedRdtsc(PVMCPU pVCpu, uint8_t cbInstr);
+VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedRdtscp(PVMCPU pVCpu, uint8_t cbInstr);
+
 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedClgi(PVMCPU pVCpu, uint8_t cbInstr);

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -1866 +1866 @@
 
 
+#if 1 /** @todo Remove after testing and enabling @bugref{6973}. */
+
 /**
  * Interpret RDTSC.
@@ -1939 +1941 @@
     return VINF_SUCCESS;
 }
+
+#endif /* Trying to use IEM APIs instead. */
 
 /**

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -14944 +14944 @@
 
 /**
+ * Interface for HM and EM to emulate the RDTSC instruction.
+ *
+ * @returns Strict VBox status code.
+ * @retval  VINF_EM_RESCHEDULE (VINF_IEM_RAISED_XCPT) if exception is raised.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   cbInstr             The instruction length in bytes.
+ *
+ * @remarks Not all of the state needs to be synced in.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPU pVCpu, uint8_t cbInstr)
+{
+    IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
+
+    iemInitExec(pVCpu, false /*fBypassHandlers*/);
+    VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_rdtsc);
+    Assert(!pVCpu->iem.s.cActiveMappings);
+    return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
+}
+
+
+/**
+ * Interface for HM and EM to emulate the RDTSCP instruction.
+ *
+ * @returns Strict VBox status code.
+ * @retval  VINF_EM_RESCHEDULE (VINF_IEM_RAISED_XCPT) if exception is raised.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   cbInstr             The instruction length in bytes.
+ *
+ * @remarks Not all of the state needs to be synced in.  Recommended
+ *          to include CPUMCTX_EXTRN_TSC_AUX, to avoid extra fetch call.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPU pVCpu, uint8_t cbInstr)
+{
+    IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
+
+    iemInitExec(pVCpu, false /*fBypassHandlers*/);
+    VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_rdtscp);
+    Assert(!pVCpu->iem.s.cActiveMappings);
+    return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
+}
+
+
+/**
  * Checks if IEM is in the process of delivering an event (interrupt or
  * exception).

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -6094 +6094 @@
         return iemRaiseUndefinedOpcode(pVCpu);
 
-    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
-    if (   (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
-        && pVCpu->iem.s.uCpl != 0)
-    {
-        Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
-        return iemRaiseGeneralProtectionFault0(pVCpu);
+    if (pVCpu->iem.s.uCpl != 0)
+    {
+        IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
+        if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
+        {
+            Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
+            return iemRaiseGeneralProtectionFault0(pVCpu);
+        }
     }
 
@@ -6118 +6120 @@
     pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
     pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
+    pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
     iemRegAddToRipAndClearRF(pVCpu, cbInstr);
     return VINF_SUCCESS;
@@ -6134 +6137 @@
         return iemRaiseUndefinedOpcode(pVCpu);
 
-    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
-    if (   (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
-        && pVCpu->iem.s.uCpl != 0)
-    {
-        Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
-        return iemRaiseGeneralProtectionFault0(pVCpu);
+    if (pVCpu->iem.s.uCpl != 0)
+    {
+        IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
+        if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
+        {
+            Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
+            return iemRaiseGeneralProtectionFault0(pVCpu);
+        }
     }
 
@@ -6166 +6171 @@
         pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
         pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
+        pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
         iemRegAddToRipAndClearRF(pVCpu, cbInstr);
     }

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -6124 +6124 @@
 
 
-#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
 /**
  * Gets the length of the current instruction if the CPU supports the NRIP_SAVE
@@ -6146 +6145 @@
     return cbLikely;
 }
-#endif
 
 
@@ -6257 +6255 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
-    int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
-    if (RT_LIKELY(rc == VINF_SUCCESS))
-    {
+#if 0 /** @todo Needs testing. @bugref{6973} */
+    VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 2));
+    if (rcStrict == VINF_SUCCESS)
         pSvmTransient->fUpdateTscOffsetting = true;
-        hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
+    else if (rcStrict == VINF_EM_RESCHEDULE)
+        rcStrict = VINF_SUCCESS;
+    HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
+    return VBOXSTRICTRC_TODO(rcStrict);
+#else
+    int rc = EMInterpretRdtsc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
+    if (RT_LIKELY(rcStrict == VINF_SUCCESS))
+    {
+        pSvmTransient->fUpdateTscOffsetting = true;
         HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
     }
@@ -6272 +6278 @@
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
     return rc;
+#endif
 }
 
@@ -6281 +6288 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
+#if 0 /** @todo Needs testing. @bugref{6973} */
+    VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 2));
+    if (rcStrict == VINF_SUCCESS)
+        pSvmTransient->fUpdateTscOffsetting = true;
+    else if (rcStrict == VINF_EM_RESCHEDULE)
+        rcStrict = VINF_SUCCESS;
+    HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
+    return VBOXSTRICTRC_TODO(rcStrict);
+#else
     int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
     if (RT_LIKELY(rc == VINF_SUCCESS))
@@ -6295 +6312 @@
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
     return rc;
+#endif
 }
 

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -7100 +7100 @@
     if (fNeedRsp)
         rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
-    rc     |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
+    rc     |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /** @todo Only CS and SS are required here. */
     if (!fMemory)
         rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
@@ -11829 +11829 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+#if 0 /** @todo Needs testing. @bugref{6973} */
+    int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);      /* Needed for CPL < 0 only, really. */
+    rc    |= hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, false /*fNeedRsp*/);
+    AssertRCReturn(rc, rc);
+    VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, pVmxTransient->cbInstr);
+    if (RT_LIKELY(rcStrict == VINF_SUCCESS))
+    {
+        /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
+            pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
+    }
+    else if (rcStrict == VINF_EM_RESCHEDULE)
+        rcStrict = VINF_SUCCESS;
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
+    return rcStrict;
+#else
     int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
     AssertRCReturn(rc, rc);
@@ -11846 +11862 @@
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
     return rc;
+#endif
 }
 
@@ -11855 +11872 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+#if 0 /** @todo Needs testing. @bugref{6973} */
+    int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);      /* Needed for CPL < 0 only, really. */
+    rc    |= hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, false /*fNeedRsp*/);
+    rc    |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);  /* For MSR_K8_TSC_AUX */
+    AssertRCReturn(rc, rc);
+    VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, pVmxTransient->cbInstr);
+    if (RT_LIKELY(rcStrict == VINF_SUCCESS))
+    {
+        /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
+            pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
+    }
+    else if (rcStrict == VINF_EM_RESCHEDULE)
+        rcStrict = VINF_SUCCESS;
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
+    return rcStrict;
+#else
     int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
     rc    |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);  /* For MSR_K8_TSC_AUX */
@@ -11874 +11908 @@
         rc = VERR_EM_INTERPRETER;
     }
-    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
     return rc;
+#endif
 }