Changeset 72805 in vbox for trunk/src/VBox/VMM

Timestamp:

Jul 3, 2018 4:05:43 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

123348

Message:

VMM/HM: bugref:9193 Fixes honoring pending VMCPU_FF_HM_UPDATE_CR3 and VMCPU_FF_HM_UPDATE_PAE_PDPES
before re-entering guest execution with VT-x R0 code.
Avoid a couple of VMWRITES because we already have cache's of the values (CR4 Mask, CR0 mask).
Parameter cleanup.

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/HMR0.cpp (modified) (14 diffs)
• VMMR0/HMSVMR0.cpp (modified) (64 diffs)
• VMMR0/HMSVMR0.h (modified) (1 diff)
• VMMR0/HMVMXR0.cpp (modified) (137 diffs)
• VMMR0/HMVMXR0.h (modified) (2 diffs)
• VMMR0/VMMR0.cpp (modified) (1 diff)
• VMMR3/HM.cpp (modified) (19 diffs)
• include/HMInternal.h (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0.cpp

@@ -88 +88 @@
     /** @name Ring-0 method table for AMD-V and VT-x specific operations.
      * @{ */
-    DECLR0CALLBACKMEMBER(int,  pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
+    DECLR0CALLBACKMEMBER(int,  pfnEnterSession, (PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
     DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
     DECLR0CALLBACKMEMBER(int,  pfnExportHostState, (PVMCPU pVCpu));
-    DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
+    DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu, PCPUMCTX pCtx));
     DECLR0CALLBACKMEMBER(int,  pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
                                               bool fEnabledByHost, void *pvArg));
@@ -234 +234 @@
  * @{ */
 
-static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
-{
-    RT_NOREF3(pVM, pVCpu, pCpu);
+static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
+{
+    RT_NOREF2(pVCpu, pCpu);
     return VINF_SUCCESS;
 }
@@ -276 +276 @@
 }
 
-static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
-    RT_NOREF3(pVM, pVCpu, pCtx);
+static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx)
+{
+    RT_NOREF2(pVCpu, pCtx);
     return VINF_SUCCESS;
 }
@@ -1389 +1389 @@
  * @remarks No-long-jump zone!!!
  */
-VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
+VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
 {
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -1418 +1418 @@
  *
  * @returns VBox status code.
- * @param   pVM        The cross context VM structure.
  * @param   pVCpu      The cross context virtual CPU structure.
  *
  * @remarks This is called with preemption disabled.
  */
-VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
+VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
 {
     /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
@@ -1430 +1429 @@
 
     /* Load the bare minimum state required for entering HM. */
-    int rc = HMR0EnterCpu(pVCpu);
+    int rc = hmR0EnterCpu(pVCpu);
     AssertRCReturn(rc, rc);
 
@@ -1452 +1451 @@
     }
 
-    rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
+    rc = g_HmR0.pfnEnterSession(pVCpu, pCpu);
     AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
 
@@ -1537 +1536 @@
 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
 {
+    RT_NOREF(pVM);
+
 #ifdef VBOX_STRICT
     /* With thread-context hooks we would be running this code with preemption enabled. */
@@ -1554 +1555 @@
 #endif
 
-    VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVM, pVCpu, &pVCpu->cpum.GstCtx);
+    VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu, &pVCpu->cpum.GstCtx);
 
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
@@ -1669 +1670 @@
     PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (pVM->hm.s.vmx.fSupported)
-        return VMXR0InvalidatePage(pVM, pVCpu, GCVirt);
-    return SVMR0InvalidatePage(pVM, pVCpu, GCVirt);
+        return VMXR0InvalidatePage(pVCpu, GCVirt);
+    return SVMR0InvalidatePage(pVCpu, GCVirt);
 }
 
@@ -1728 +1729 @@
 
 #ifdef VBOX_WITH_RAW_MODE
-
 /**
  * Raw-mode switcher hook - disable VT-x if it's active *and* the current
@@ -1823 +1823 @@
     }
 }
-
 #endif /* VBOX_WITH_RAW_MODE */
+
+
 #ifdef VBOX_STRICT
-
 /**
  * Dumps a descriptor.
@@ -1953 +1953 @@
  * Formats a full register dump.
  *
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the CPU context.
  */
-VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
-    NOREF(pVM);
-
+VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu, PCPUMCTX pCtx)
+{
     /*
      * Format the flags.
@@ -2098 +2095 @@
     NOREF(pFpuCtx);
 }
-
 #endif /* VBOX_STRICT */
 

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -73 +73 @@
 # endif
 #endif /* !VBOX_WITH_STATISTICS */
-
 
 /** If we decide to use a function table approach this can be useful to
@@ -528 +527 @@
  *
  * @returns VBox status code.
- * @param   pCpu            Pointer to the CPU info struct.
+ * @param   pHostCpu        Pointer to the CPU info struct.
  * @param   pVM             The cross context VM structure. Can be
  *                          NULL after a resume!
@@ -536 +535 @@
  * @param   pvArg           Unused on AMD-V.
  */
-VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
+VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
                               void *pvArg)
 {
@@ -560 +559 @@
         if (   pVM
             && pVM->hm.s.svm.fIgnoreInUseError)
-            pCpu->fIgnoreAMDVInUseError = true;
-
-        if (!pCpu->fIgnoreAMDVInUseError)
+            pHostCpu->fIgnoreAMDVInUseError = true;
+
+        if (!pHostCpu->fIgnoreAMDVInUseError)
         {
             ASMSetFlags(fEFlags);
@@ -584 +583 @@
      * entirely with before executing any guest code.
      */
-    pCpu->fFlushAsidBeforeUse = true;
+    pHostCpu->fFlushAsidBeforeUse = true;
 
     /*
      * Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
      */
-    ++pCpu->cTlbFlushes;
+    ++pHostCpu->cTlbFlushes;
 
     return VINF_SUCCESS;
@@ -599 +598 @@
  *
  * @returns VBox status code.
- * @param   pCpu            Pointer to the CPU info struct.
+ * @param   pHostCpu        Pointer to the CPU info struct.
  * @param   pvCpuPage       Pointer to the global CPU page.
  * @param   HCPhysCpuPage   Physical address of the global CPU page.
  */
-VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
+VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -609 +608 @@
                  && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
     AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
-    NOREF(pCpu);
+    RT_NOREF(pHostCpu);
 
     /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
@@ -1169 +1168 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   GCVirt      Guest virtual address of the page to invalidate.
  */
-VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
-{
-    AssertReturn(pVM, VERR_INVALID_PARAMETER);
-    Assert(pVM->hm.s.svm.fSupported);
-
-    bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
+VMMR0DECL(int) SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
+{
+    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
+
+    bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
 
     /* Skip it if a TLB flush is already pending. */
@@ -1610 +1607 @@
     pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
-    Assert(RT_HI_U32(uShadowCr0) == 0);
+    Assert(!RT_HI_U32(uShadowCr0));
     if (pVmcb->guest.u64CR0 != uShadowCr0)
     {
@@ -1723 +1720 @@
 
     /* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
-    Assert(RT_HI_U32(uShadowCr4) == 0);
+    Assert(!RT_HI_U32(uShadowCr4));
     pVmcb->guest.u64CR4 = uShadowCr4;
     pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER | HMSVM_VMCB_CLEAN_INTERCEPTS);
@@ -2337 +2334 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
- * @param   pCpu        Pointer to the CPU info struct.
- */
-VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
-{
-    AssertPtr(pVM);
+ * @param   pHostCpu    Pointer to the CPU info struct.
+ */
+VMMR0DECL(int) SVMR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
+{
     AssertPtr(pVCpu);
-    Assert(pVM->hm.s.svm.fSupported);
+    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
-    NOREF(pVM); NOREF(pCpu);
-
-    LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
+    RT_NOREF(pHostCpu);
+
+    LogFlowFunc(("pVCpu=%p\n", pVCpu));
     Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
                                    == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
@@ -2410 +2405 @@
              * initializing AMD-V if necessary (onlined CPUs, local init etc.)
              */
-            int rc = HMR0EnterCpu(pVCpu);
+            int rc = hmR0EnterCpu(pVCpu);
             AssertRC(rc); NOREF(rc);
             Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
@@ -3126 +3121 @@
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
-    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
-    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
+    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
+    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
 
@@ -3255 +3250 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -3261 +3255 @@
  *                      VINF_VMM_UNKNOWN_RING3_CALL.
  */
-static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
-{
-    Assert(pVM);
+static int hmR0SvmExitToRing3(PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
+{
     Assert(pVCpu);
     Assert(pCtx);
@@ -3270 +3263 @@
     /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
     VMMRZCallRing3Disable(pVCpu);
-    Log4Func(("rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", rcExit, pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
+    Log4Func(("rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", rcExit, pVCpu->fLocalForcedActions,
+              pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
 
     /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
@@ -3290 +3284 @@
                                | CPUM_CHANGED_TR
                                | CPUM_CHANGED_HIDDEN_SEL_REGS);
-    if (   pVM->hm.s.fNestedPaging
+    if (   pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
         && CPUMIsGuestPagingEnabledEx(pCtx))
     {
@@ -3331 +3325 @@
  * intercepts.
  *
- * @param   pVM         The cross context VM structure.
- * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU or nested-guest-CPU context.
  * @param   pVmcb       Pointer to the VM control block.
@@ -3338 +3330 @@
  * @remarks No-long-jump zone!!!
  */
-static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PCCPUMCTX pCtx, PSVMVMCB pVmcb)
+static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu, PCCPUMCTX pCtx, PSVMVMCB pVmcb)
 {
     /*
@@ -3347 +3339 @@
     bool       fParavirtTsc;
     uint64_t   uTscOffset;
-    bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
+    bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
 
     bool fIntercept;
@@ -4079 +4071 @@
  * Reports world-switch error and dumps some useful debug info.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   rcVMRun         The return code from VMRUN (or
@@ -4086 +4077 @@
  * @param   pCtx            Pointer to the guest-CPU context.
  */
-static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
-{
-    NOREF(pCtx);
+static void hmR0SvmReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
+{
     HMSVM_ASSERT_PREEMPT_SAFE();
     HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
     HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
 
-    PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
     if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
     {
-        hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
-        /** @todo We probably don't need to dump this anymore or we can expand
-         *        hmR0DumpRegs()? */
 #ifdef VBOX_STRICT
+        hmR0DumpRegs(pVCpu, pCtx);
+        PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
         Log4(("ctrl.u32VmcbCleanBits                 %#RX32\n",   pVmcb->ctrl.u32VmcbCleanBits));
         Log4(("ctrl.u16InterceptRdCRx                %#x\n",      pVmcb->ctrl.u16InterceptRdCRx));
@@ -4225 +4213 @@
         Log4Func(("rcVMRun=%d\n", rcVMRun));
 
-    NOREF(pVmcb);
+    NOREF(pCtx);
 }
 
@@ -4245 +4233 @@
  *         to the EM loop.
  *
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
  */
-static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+static int hmR0SvmCheckForceFlags(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
@@ -4262 +4249 @@
         APICUpdatePendingInterrupts(pVCpu);
 
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (   VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
                             ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
@@ -4324 +4312 @@
  * @retval VINF_* scheduling changes, we have to go back to ring-3.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pCtx            Pointer to the nested-guest-CPU context.
@@ -4332 +4319 @@
  * @sa      hmR0SvmPreRunGuest.
  */
-static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
+static int hmR0SvmPreRunGuestNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
 {
     HMSVM_ASSERT_PREEMPT_SAFE();
@@ -4343 +4330 @@
 
     /* Check force flag actions that might require us to go back to ring-3. */
-    int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
+    int rc = hmR0SvmCheckForceFlags(pVCpu, pCtx);
     if (rc != VINF_SUCCESS)
         return rc;
@@ -4364 +4351 @@
      * NB: If we could continue a task switch exit we wouldn't need to do this.
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (RT_UNLIKELY(   !pVM->hm.s.svm.u32Features
                     &&  pVCpu->hm.s.Event.fPending
@@ -4446 +4434 @@
  * @retval VINF_* scheduling changes, we have to go back to ring-3.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pCtx            Pointer to the guest-CPU context.
  * @param   pSvmTransient   Pointer to the SVM transient structure.
  */
-static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
+static int hmR0SvmPreRunGuest(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
 {
     HMSVM_ASSERT_PREEMPT_SAFE();
@@ -4457 +4444 @@
 
     /* Check force flag actions that might require us to go back to ring-3. */
-    int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
+    int rc = hmR0SvmCheckForceFlags(pVCpu, pCtx);
     if (rc != VINF_SUCCESS)
         return rc;
@@ -4471 +4458 @@
      * NB: If we could continue a task switch exit we wouldn't need to do this.
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
         if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
@@ -4604 +4592 @@
         || fMigratedHostCpu)
     {
-        hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pCtx, pVmcb);
+        hmR0SvmUpdateTscOffsetting(pVCpu, pCtx, pVmcb);
         pSvmTransient->fUpdateTscOffsetting = false;
     }
@@ -4687 +4675 @@
 
 /**
- * Wrapper for running the guest code in AMD-V.
+ * Wrapper for running the guest (or nested-guest) code in AMD-V.
  *
  * @returns VBox strict status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
+ * @param   HCPhysVmcb  The host physical address of the VMCB.
  *
  * @remarks No-long-jump zone!!!
  */
-DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+DECLINLINE(int) hmR0SvmRunGuest(PVMCPU pVCpu, PCPUMCTX pCtx, RTHCPHYS HCPhysVmcb)
 {
     /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
@@ -4708 +4696 @@
      * Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
 #ifdef VBOX_WITH_KERNEL_USING_XMM
-    return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
-                             pVCpu->hm.s.svm.pfnVMRun);
+    return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
 #else
-    return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
-#endif
-}
-
-
-#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
-/**
- * Wrapper for running the nested-guest code in AMD-V.
- *
- * @returns VBox strict status code.
- * @param   pVM         The cross context VM structure.
- * @param   pVCpu       The cross context virtual CPU structure.
- * @param   pCtx        Pointer to the guest-CPU context.
- *
- * @remarks No-long-jump zone!!!
- */
-DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
-    /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
-    pCtx->fExtrn |= HMSVM_CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_HM;
-
-    /*
-     * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
-     * floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
-     * callee-saved and thus the need for this XMM wrapper.
-     *
-     * Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
-     */
-#ifdef VBOX_WITH_KERNEL_USING_XMM
-    return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
-                             pVCpu->hm.s.svm.pfnVMRun);
-#else
-    return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
+    return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
 #endif
 }
@@ -4768 +4724 @@
     return uTicks - pVmcbNstGstCache->u64TSCOffset;
 }
-#endif
+
 
 /**
@@ -4819 +4775 @@
     }
 
-    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
+    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
     TMNotifyEndOfExecution(pVCpu);                              /* Notify TM that the guest is no longer running. */
     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
@@ -4908 +4864 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
  * @param   pcLoops     Pointer to the number of executed loops.
  */
-static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
-{
-    uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
+static int hmR0SvmRunGuestCodeNormal(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
+{
+    uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
     Assert(pcLoops);
     Assert(*pcLoops <= cMaxResumeLoops);
@@ -4933 +4888 @@
            ring-3.  This bugger disables interrupts on VINF_SUCCESS! */
         STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
-        rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
+        rc = hmR0SvmPreRunGuest(pVCpu, pCtx, &SvmTransient);
         if (rc != VINF_SUCCESS)
             break;
@@ -4944 +4899 @@
          */
         hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
-        rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
+        rc = hmR0SvmRunGuest(pVCpu, pCtx, pVCpu->hm.s.svm.HCPhysVmcb);
 
         /* Restore any residual host-state and save any bits shared between host and guest
@@ -4955 +4910 @@
             if (rc == VINF_SUCCESS)
                 rc = VERR_SVM_INVALID_GUEST_STATE;
-            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
-            hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
+            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
+            hmR0SvmReportWorldSwitchError(pVCpu, rc, pCtx);
             break;
         }
@@ -4962 +4917 @@
         /* Handle the #VMEXIT. */
         HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
-        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
         VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
         rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
-        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
         if (rc != VINF_SUCCESS)
             break;
@@ -4985 +4940 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
  * @param   pcLoops     Pointer to the number of executed loops.
  */
-static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
-{
-    uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
+static int hmR0SvmRunGuestCodeStep(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
+{
+    uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
     Assert(pcLoops);
     Assert(*pcLoops <= cMaxResumeLoops);
@@ -5015 +4969 @@
            ring-3.  This bugger disables interrupts on VINF_SUCCESS! */
         STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
-        rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
+        rc = hmR0SvmPreRunGuest(pVCpu, pCtx, &SvmTransient);
         if (rc != VINF_SUCCESS)
             break;
@@ -5029 +4983 @@
         hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
 
-        rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
+        rc = hmR0SvmRunGuest(pVCpu, pCtx, pVCpu->hm.s.svm.HCPhysVmcb);
 
         /* Restore any residual host-state and save any bits shared between host and guest
@@ -5040 +4994 @@
             if (rc == VINF_SUCCESS)
                 rc = VERR_SVM_INVALID_GUEST_STATE;
-            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
-            hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
+            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
+            hmR0SvmReportWorldSwitchError(pVCpu, rc, pCtx);
             return rc;
         }
@@ -5047 +5001 @@
         /* Handle the #VMEXIT. */
         HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
-        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
         VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
         rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
-        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
         if (rc != VINF_SUCCESS)
             break;
@@ -5091 +5045 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -5098 +5051 @@
  *                      execution loop pass the remainder value, else pass 0.
  */
-static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
+static int hmR0SvmRunGuestCodeNested(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
 {
     HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
     Assert(pcLoops);
-    Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
+    Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
 
     SVMTRANSIENT SvmTransient;
@@ -5119 +5072 @@
            ring-3.  This bugger disables interrupts on VINF_SUCCESS! */
         STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
-        rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
+        rc = hmR0SvmPreRunGuestNested(pVCpu, pCtx, &SvmTransient);
         if (    rc != VINF_SUCCESS
             || !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
@@ -5134 +5087 @@
         hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
 
-        rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
+        rc = hmR0SvmRunGuest(pVCpu, pCtx, pCtx->hwvirt.svm.HCPhysVmcb);
 
         /* Restore any residual host-state and save any bits shared between host and guest
@@ -5158 +5111 @@
         /* Handle the #VMEXIT. */
         HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
-        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
         VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
         rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
-        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
         if (    rc != VINF_SUCCESS
             || !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
             break;
-        if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
+        if (++(*pcLoops) >= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
         {
             STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
@@ -5185 +5138 @@
  *
  * @returns Strict VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
  */
-VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
@@ -5202 +5154 @@
     {
         if (!pVCpu->hm.s.fSingleInstruction)
-            rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
+            rc = hmR0SvmRunGuestCodeNormal(pVCpu, pCtx, &cLoops);
         else
-            rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
+            rc = hmR0SvmRunGuestCodeStep(pVCpu, pCtx, &cLoops);
     }
 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
@@ -5216 +5168 @@
     if (rc == VINF_SVM_VMRUN)
     {
-        rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
+        rc = hmR0SvmRunGuestCodeNested(pVCpu, pCtx, &cLoops);
         if (rc == VINF_SVM_VMEXIT)
             rc = VINF_SUCCESS;
@@ -5229 +5181 @@
 
     /* Prepare to return to ring-3. This will remove longjmp notifications. */
-    rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
+    rc = hmR0SvmExitToRing3(pVCpu, pCtx, rc);
     Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
     return rc;
@@ -5954 +5906 @@
  * @retval  VERR_*                  Fatal errors.
  *
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        The guest CPU context.
@@ -5960 +5911 @@
  * @remarks Updates the RIP if the instruction was executed successfully.
  */
-static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+static int hmR0SvmInterpretInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     /* Only allow 32 & 64 bit code. */
@@ -5966 +5917 @@
     {
         PDISSTATE pDis = &pVCpu->hm.s.DisState;
-        int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
+        int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, NULL /* pcbInstr */);
         if (   RT_SUCCESS(rc)
             && pDis->pCurInstr->uOpcode == OP_INVLPG)
@@ -6447 +6398 @@
 {
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
-    Assert(!pVM->hm.s.fNestedPaging);
+    Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
 
     bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
@@ -6465 +6415 @@
 
     HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
-    int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx);    /* Updates RIP if successful. */
+    int rc = hmR0SvmInterpretInvlpg(pVCpu, pCtx);    /* Updates RIP if successful. */
     Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
     HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
@@ -6997 +6947 @@
     static uint32_t const s_aIOSize[8]  = { 0, 1, 2, 0, 4, 0, 0, 0 };                   /* Size of the I/O accesses in bytes. */
     static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 };  /* AND masks for saving
-                                                                                            the result (in AL/AX/EAX). */
+                                                                                           the result (in AL/AX/EAX). */
     Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
 
@@ -7243 +7193 @@
      */
     if (   pVM->hm.s.fTprPatchingAllowed
-        && !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
         && (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
         && (   !(u32ErrCode & X86_TRAP_PF_P)                                                             /* Not present */
             || (u32ErrCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD))  /* MMIO page. */
+        && !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
         && !CPUMIsGuestInLongModeEx(pCtx)
         && !CPUMGetGuestCPL(pVCpu)
@@ -8049 +7999 @@
     return VINF_SUCCESS;
 }
-
 #endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
 
-
 /** @} */
 

trunk/src/VBox/VMM/VMMR0/HMSVMR0.h

@@ -40 +40 @@
 VMMR0DECL(int)          SVMR0GlobalInit(void);
 VMMR0DECL(void)         SVMR0GlobalTerm(void);
-VMMR0DECL(int)          SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
+VMMR0DECL(int)          SVMR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu);
 VMMR0DECL(void)         SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
-VMMR0DECL(int)          SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS HCPhysCpuPage,
+VMMR0DECL(int)          SVMR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvPageCpu, RTHCPHYS HCPhysCpuPage,
                                        bool fEnabledBySystem, void *pvArg);
-VMMR0DECL(int)          SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int)          SVMR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 VMMR0DECL(int)          SVMR0InitVM(PVM pVM);
 VMMR0DECL(int)          SVMR0TermVM(PVM pVM);
 VMMR0DECL(int)          SVMR0SetupVM(PVM pVM);
-VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx);
 VMMR0DECL(int)          SVMR0ExportHostState(PVMCPU pVCpu);
 VMMR0DECL(int)          SVMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
-VMMR0DECL(int)          SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
+VMMR0DECL(int)          SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
 
 #if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -371 +371 @@
 *********************************************************************************************************************************/
 static void               hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush);
-static void               hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
+static void               hmR0VmxFlushVpid(PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
 static void               hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
 static int                hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat);
@@ -377 +377 @@
                                                  RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState);
 #if HC_ARCH_BITS == 32
-static int                hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu);
+static int                hmR0VmxInitVmcsReadCache(PVMCPU pVCpu);
 #endif
 #ifndef HMVMX_USE_FUNCTION_TABLE
@@ -446 +446 @@
 static int          hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
 static int          hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
-static uint32_t     hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+static uint32_t     hmR0VmxCheckGuestState(PVMCPU pVCpu, PCPUMCTX pCtx);
 
 
@@ -570 +570 @@
  * updates VCPU's last error record as well.
  *
- * @param   pVM     The cross context VM structure.
  * @param   pVCpu   The cross context virtual CPU structure of the calling EMT.
  *                  Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
@@ -576 +575 @@
  * @param   rc      The error code.
  */
-static void hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc)
-{
-    AssertPtr(pVM);
+static void hmR0VmxUpdateErrorRecord(PVMCPU pVCpu, int rc)
+{
     if (   rc == VERR_VMX_INVALID_VMCS_FIELD
         || rc == VERR_VMX_UNABLE_TO_START_VM)
@@ -585 +583 @@
         VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
     }
-    pVM->hm.s.lLastError = rc;
+    pVCpu->CTX_SUFF(pVM)->hm.s.lLastError = rc;
 }
 
@@ -1089 +1087 @@
  *
  * @returns VBox status code.
- * @param   pCpu            Pointer to the global CPU info struct.
+ * @param   pHostCpu        Pointer to the global CPU info struct.
  * @param   pVM             The cross context VM structure.  Can be
  *                          NULL after a host resume operation.
@@ -1100 +1098 @@
  * @param   pvMsrs          Opaque pointer to VMXMSRS struct.
  */
-VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
+VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
                               void *pvMsrs)
 {
-    Assert(pCpu);
+    Assert(pHostCpu);
     Assert(pvMsrs);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -1124 +1122 @@
     {
         hmR0VmxFlushEpt(NULL /* pVCpu */, VMXFLUSHEPT_ALL_CONTEXTS);
-        pCpu->fFlushAsidBeforeUse = false;
+        pHostCpu->fFlushAsidBeforeUse = false;
     }
     else
-        pCpu->fFlushAsidBeforeUse = true;
+        pHostCpu->fFlushAsidBeforeUse = true;
 
     /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
-    ++pCpu->cTlbFlushes;
+    ++pHostCpu->cTlbFlushes;
 
     return VINF_SUCCESS;
@@ -1140 +1138 @@
  *
  * @returns VBox status code.
- * @param   pCpu            Pointer to the global CPU info struct.
+ * @param   pHostCpu        Pointer to the global CPU info struct.
  * @param   pvCpuPage       Pointer to the VMXON region.
  * @param   HCPhysCpuPage   Physical address of the VMXON region.
@@ -1147 +1145 @@
  *          similar was used to enable VT-x on the host.
  */
-VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
-{
-    NOREF(pCpu);
-    NOREF(pvCpuPage);
-    NOREF(HCPhysCpuPage);
+VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
+{
+    RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
 
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -1787 +1783 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure of the calling
  *                      EMT.  Can be NULL depending on @a enmFlush.
@@ -1796 +1791 @@
  * @remarks Can be called with interrupts disabled.
  */
-static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
-{
-    NOREF(pVM);
-    AssertPtr(pVM);
-    Assert(pVM->hm.s.vmx.fVpid);
+static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
+{
+    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid);
 
     uint64_t au64Descriptor[2];
@@ -1817 +1810 @@
     }
 
-    int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]); NOREF(rc);
-    AssertMsg(rc == VINF_SUCCESS,
-              ("VMXR0InvVPID %#x %u %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
+    int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]);
+    AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmFlush,
+                                   pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
     if (   RT_SUCCESS(rc)
         && pVCpu)
@@ -1825 +1818 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
     }
+    NOREF(rc);
 }
 
@@ -1833 +1827 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   GCVirt      Guest virtual address of the page to invalidate.
  */
-VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
-{
-    AssertPtr(pVM);
+VMMR0DECL(int) VMXR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
+{
     AssertPtr(pVCpu);
-    LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
+    LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
 
     bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
@@ -1853 +1845 @@
          * as this function maybe called in a loop with individual addresses.
          */
+        PVM pVM = pVCpu->CTX_SUFF(pVM);
         if (pVM->hm.s.vmx.fVpid)
         {
@@ -1869 +1862 @@
             if (fVpidFlush)
             {
-                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
+                hmR0VmxFlushVpid(pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
             }
@@ -1887 +1880 @@
  * case where neither EPT nor VPID is supported by the CPU.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pCpu            Pointer to the global HM struct.
@@ -1893 +1885 @@
  * @remarks Called with interrupts disabled.
  */
-static void hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
+static void hmR0VmxFlushTaggedTlbNone(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
 {
     AssertPtr(pVCpu);
     AssertPtr(pCpu);
-    NOREF(pVM);
 
     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
@@ -1912 +1903 @@
  * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
  *
- * @param    pVM            The cross context VM structure.
  * @param    pVCpu          The cross context virtual CPU structure.
  * @param    pCpu           Pointer to the global HM CPU struct.
- * @remarks All references to "ASID" in this function pertains to "VPID" in
- *          Intel's nomenclature. The reason is, to avoid confusion in compare
- *          statements since the host-CPU copies are named "ASID".
- *
- * @remarks Called with interrupts disabled.
- */
-static void hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
+ *
+ * @remarks  All references to "ASID" in this function pertains to "VPID" in Intel's
+ *           nomenclature. The reason is, to avoid confusion in compare statements
+ *           since the host-CPU copies are named "ASID".
+ *
+ * @remarks  Called with interrupts disabled.
+ */
+static void hmR0VmxFlushTaggedTlbBoth(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
 {
 #ifdef VBOX_WITH_STATISTICS
@@ -1935 +1926 @@
 #endif
 
-    AssertPtr(pVM);
     AssertPtr(pCpu);
     AssertPtr(pVCpu);
     Assert(pCpu->idCpu != NIL_RTCPUID);
 
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
               ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
@@ -2017 +2008 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCpu        Pointer to the global HM CPU struct.
@@ -2023 +2013 @@
  * @remarks Called with interrupts disabled.
  */
-static void hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
-{
-    AssertPtr(pVM);
+static void hmR0VmxFlushTaggedTlbEpt(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
+{
     AssertPtr(pVCpu);
     AssertPtr(pCpu);
     Assert(pCpu->idCpu != NIL_RTCPUID);
-    AssertMsg(pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with NestedPaging disabled."));
-    AssertMsg(!pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID enabled."));
+    AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked without NestedPaging."));
+    AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID."));
 
     /*
@@ -2055 +2044 @@
     if (pVCpu->hm.s.fForceTLBFlush)
     {
-        hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
+        hmR0VmxFlushEpt(pVCpu, pVCpu->CTX_SUFF(pVM)->hm.s.vmx.enmFlushEpt);
         pVCpu->hm.s.fForceTLBFlush = false;
     }
@@ -2065 +2054 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCpu        Pointer to the global HM CPU struct.
@@ -2071 +2059 @@
  * @remarks Called with interrupts disabled.
  */
-static void hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
-{
-    AssertPtr(pVM);
+static void hmR0VmxFlushTaggedTlbVpid(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
+{
     AssertPtr(pVCpu);
     AssertPtr(pCpu);
     Assert(pCpu->idCpu != NIL_RTCPUID);
-    AssertMsg(pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked with VPID disabled."));
-    AssertMsg(!pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging enabled"));
+    AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked without VPID."));
+    AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging"));
 
     /*
-     * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
-     * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
-     * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
+     * Force a TLB flush for the first world switch if the current CPU differs from the one we
+     * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
+     * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
+     * cannot reuse the current ASID anymore.
      */
     if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
@@ -2096 +2084 @@
     {
         /*
-         * If we ever support VPID flush combinations other than ALL or SINGLE-context (see hmR0VmxSetupTaggedTlb())
-         * we would need to explicitly flush in this case (add an fExplicitFlush = true here and change the
-         * pCpu->fFlushAsidBeforeUse check below to include fExplicitFlush's too) - an obscure corner case.
+         * If we ever support VPID flush combinations other than ALL or SINGLE-context (see
+         * hmR0VmxSetupTaggedTlb()) we would need to explicitly flush in this case (add an
+         * fExplicitFlush = true here and change the pCpu->fFlushAsidBeforeUse check below to
+         * include fExplicitFlush's too) - an obscure corner case.
          */
         pVCpu->hm.s.fForceTLBFlush = true;
@@ -2104 +2093 @@
     }
 
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     pVCpu->hm.s.idLastCpu = pCpu->idCpu;
     if (pVCpu->hm.s.fForceTLBFlush)
@@ -2121 +2111 @@
         {
             if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
-                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
+                hmR0VmxFlushVpid(pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
             else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
             {
-                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
+                hmR0VmxFlushVpid(pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
                 pCpu->fFlushAsidBeforeUse = false;
             }
@@ -2162 +2152 @@
     switch (pVM->hm.s.vmx.uFlushTaggedTlb)
     {
-        case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu, pCpu); break;
-        case HMVMX_FLUSH_TAGGED_TLB_EPT:      hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu, pCpu);  break;
-        case HMVMX_FLUSH_TAGGED_TLB_VPID:     hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu, pCpu); break;
-        case HMVMX_FLUSH_TAGGED_TLB_NONE:     hmR0VmxFlushTaggedTlbNone(pVM, pVCpu, pCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVCpu, pCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_EPT:      hmR0VmxFlushTaggedTlbEpt(pVCpu, pCpu);  break;
+        case HMVMX_FLUSH_TAGGED_TLB_VPID:     hmR0VmxFlushTaggedTlbVpid(pVCpu, pCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_NONE:     hmR0VmxFlushTaggedTlbNone(pVCpu, pCpu); break;
         default:
             AssertMsgFailed(("Invalid flush-tag function identifier\n"));
@@ -2279 +2269 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  */
-static int hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu)
-{
-    AssertPtr(pVM);
+static int hmR0VmxSetupPinCtls(PVMCPU pVCpu)
+{
     AssertPtr(pVCpu);
 
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     uint32_t fVal = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;         /* Bits set here must always be set. */
     uint32_t fZap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;            /* Bits cleared here must always be cleared. */
@@ -2333 +2322 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  */
-static int hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu)
-{
-    AssertPtr(pVM);
+static int hmR0VmxSetupProcCtls(PVMCPU pVCpu)
+{
     AssertPtr(pVCpu);
 
     int rc = VERR_INTERNAL_ERROR_5;
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     uint32_t fVal = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
     uint32_t fZap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;    /* Bits cleared here must be cleared in the VMCS. */
@@ -2555 +2543 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  */
-static int hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu)
-{
-    NOREF(pVM);
-    AssertPtr(pVM);
+static int hmR0VmxSetupMiscCtls(PVMCPU pVCpu)
+{
     AssertPtr(pVCpu);
 
@@ -2627 +2612 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  */
-static int hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu)
-{
-    AssertPtr(pVM);
+static int hmR0VmxInitXcptBitmap(PVMCPU pVCpu)
+{
     AssertPtr(pVCpu);
 
-    LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
-
-    uint32_t u32XcptBitmap = 0;
+    uint32_t u32XcptBitmap;
 
     /* Must always intercept #AC to prevent the guest from hanging the CPU. */
-    u32XcptBitmap |= RT_BIT_32(X86_XCPT_AC);
+    u32XcptBitmap = RT_BIT_32(X86_XCPT_AC);
 
     /* Because we need to maintain the DR6 state even when intercepting DRx reads
@@ -2648 +2629 @@
 
     /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
-    if (!pVM->hm.s.fNestedPaging)
+    if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
         u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
 
-    pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
+    /* Commit it to the VMCS. */
     int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
     AssertRCReturn(rc, rc);
-    return rc;
+
+    /* Update our cache of the exception bitmap. */
+    pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
+    return VINF_SUCCESS;
 }
 
@@ -2767 +2751 @@
         /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
         rc  = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
 
         /* Load this VMCS as the current VMCS. */
         rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
-
-        rc = hmR0VmxSetupPinCtls(pVM, pVCpu);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
-
-        rc = hmR0VmxSetupProcCtls(pVM, pVCpu);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
-
-        rc = hmR0VmxSetupMiscCtls(pVM, pVCpu);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
-
-        rc = hmR0VmxInitXcptBitmap(pVM, pVCpu);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
+
+        rc = hmR0VmxSetupPinCtls(pVCpu);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
+
+        rc = hmR0VmxSetupProcCtls(pVCpu);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
+
+        rc = hmR0VmxSetupMiscCtls(pVCpu);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
+
+        rc = hmR0VmxInitXcptBitmap(pVCpu);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
 
 #if HC_ARCH_BITS == 32
-        rc = hmR0VmxInitVmcsReadCache(pVM, pVCpu);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
+        rc = hmR0VmxInitVmcsReadCache(pVCpu);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
 #endif
 
         /* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
         rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
-        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
-                                    hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
+        AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc\n", rc),
+                                    hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
 
         pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
 
-        hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc);
+        hmR0VmxUpdateErrorRecord(pVCpu, rc);
     }
 
@@ -2981 +2965 @@
 
     /*
-     * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT"
-     * and Intel spec. 6.2 "Exception and Interrupt Vectors".)  Therefore if the host has the
-     * limit as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU
-     * behavior.  However, several hosts either insists on 0xfff being the limit (Windows
-     * Patch Guard) or uses the limit for other purposes (darwin puts the CPU ID in there
-     * but botches sidt alignment in at least one consumer).  So, we're only allowing the
-     * IDTR.LIMIT to be left at 0xffff on hosts where we are sure it won't cause trouble.
+     * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT" and
+     * Intel spec. 6.2 "Exception and Interrupt Vectors".)  Therefore if the host has the limit
+     * as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU behavior.
+     * However, several hosts either insists on 0xfff being the limit (Windows Patch Guard) or
+     * uses the limit for other purposes (darwin puts the CPU ID in there but botches sidt
+     * alignment in at least one consumer).  So, we're only allowing the IDTR.LIMIT to be left
+     * at 0xffff on hosts where we are sure it won't cause trouble.
      */
 # if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
@@ -3598 +3582 @@
         /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
            Let us assert it as such and use 32-bit VMWRITE. */
-        Assert(!(pMixedCtx->rflags.u64 >> 32));
+        Assert(!RT_HI_U32(pMixedCtx->rflags.u64));
         X86EFLAGS fEFlags = pMixedCtx->eflags;
         Assert(fEFlags.u32 & X86_EFL_RA1_MASK);
@@ -3770 +3754 @@
             uCr0Mask &= ~X86_CR0_PE;
 #endif
-        /* Update the HMCPU's copy of the CR0 mask. */
-        pVCpu->hm.s.vmx.u32CR0Mask = uCR0Mask;
-
         /*
          * Finally, update VMCS fields with the CR0 values.
@@ -3778 +3759 @@
         int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, uGuestCR0);
         rc    |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, uShadowCR0);
-        rc    |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, uCR0Mask);
+        if (uCR0Mask != pVCpu->hm.s.vmx.u32CR0Mask)
+            rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, uCR0Mask);
         if (uProcCtls != pVCpu->hm.s.vmx.u32ProcCtls)
             rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
         AssertRCReturn(rc, rc);
+
+        pVCpu->hm.s.vmx.u32CR0Mask  = uCR0Mask;
         pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
 
@@ -3922 +3906 @@
     {
         Assert(!RT_HI_U32(pMixedCtx->cr4));
-        uint32_t uGuestCR4 = pMixedCtx->cr4;
-
-        /* The guest's view of its CR4 is unblemished. */
-        rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, uGuestCR4);
-        AssertRCReturn(rc, rc);
-        Log4Func(("uShadowCR4=%#RX32\n", uGuestCR4));
+        uint32_t       uGuestCR4  = pMixedCtx->cr4;
+        uint32_t const uShadowCR4 = pMixedCtx->cr4;
 
         /*
@@ -3997 +3977 @@
         uGuestCR4 &= fZapCR4;
 
-        /* Write VT-x's view of the guest CR4 into the VMCS. */
-        Log4Func(("uGuestCR4=%#RX32 (fSetCR4=%#RX32 fZapCR4=%#RX32)\n", uGuestCR4, fSetCR4, fZapCR4));
-        rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, uGuestCR4);
-        AssertRCReturn(rc, rc);
-
         /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM-exit. */
         uint32_t u32CR4Mask = X86_CR4_VME
@@ -4012 +3987 @@
         if (pVM->cpum.ro.GuestFeatures.fPcid)
             u32CR4Mask |= X86_CR4_PCIDE;
+
+        /* Write VT-x's view of the guest CR4, the CR4 modify mask and the read-only CR4 shadow into the VMCS. */
+        rc  = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, uGuestCR4);
+        rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, uShadowCR4);
+        if (pVCpu->hm.s.vmx.u32CR4Mask != u32CR4Mask)
+            rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
+        AssertRCReturn(rc, rc);
         pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
-        rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
-        AssertRCReturn(rc, rc);
 
         /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
@@ -4020 +4000 @@
 
         ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR4);
+
+        Log4Func(("uGuestCR4=%#RX32 uShadowCR4=%#RX32 (fSetCR4=%#RX32 fZapCR4=%#RX32)\n", uGuestCR4, uShadowCR4, fSetCR4,
+                  fZapCR4));
     }
     return rc;
@@ -4185 +4168 @@
  * Strict function to validate segment registers.
  *
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pCtx        Pointer to the guest-CPU context.
+ *
  * @remarks Will import guest CR0 on strict builds during validation of
  *          segments.
  */
-static void hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCCPUMCTX pCtx)
+static void hmR0VmxValidateSegmentRegs(PVMCPU pVCpu, PCCPUMCTX pCtx)
 {
     /*
@@ -4197 +4183 @@
      * and doesn't change the guest-context value.
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
     if (   !pVM->hm.s.vmx.fUnrestrictedGuest
@@ -4298 +4285 @@
         /* 64-bit capable CPUs. */
 # if HC_ARCH_BITS == 64
-        Assert(!(pCtx->cs.u64Base >> 32));
-        Assert(!pCtx->ss.Attr.u || !(pCtx->ss.u64Base >> 32));
-        Assert(!pCtx->ds.Attr.u || !(pCtx->ds.u64Base >> 32));
-        Assert(!pCtx->es.Attr.u || !(pCtx->es.u64Base >> 32));
+        Assert(!RT_HI_U32(pCtx->cs.u64Base));
+        Assert(!pCtx->ss.Attr.u || !RT_HI_U32(pCtx->ss.u64Base));
+        Assert(!pCtx->ds.Attr.u || !RT_HI_U32(pCtx->ds.u64Base));
+        Assert(!pCtx->es.Attr.u || !RT_HI_U32(pCtx->es.u64Base));
 # endif
     }
@@ -4347 +4334 @@
         /* 64-bit capable CPUs. */
 # if HC_ARCH_BITS == 64
-        Assert(!(pCtx->cs.u64Base >> 32));
-        Assert(!u32SSAttr || !(pCtx->ss.u64Base >> 32));
-        Assert(!u32DSAttr || !(pCtx->ds.u64Base >> 32));
-        Assert(!u32ESAttr || !(pCtx->es.u64Base >> 32));
+        Assert(!RT_HI_U32(pCtx->cs.u64Base));
+        Assert(!u32SSAttr || !RT_HI_U32(pCtx->ss.u64Base));
+        Assert(!u32DSAttr || !RT_HI_U32(pCtx->ds.u64Base));
+        Assert(!u32ESAttr || !RT_HI_U32(pCtx->es.u64Base));
 # endif
     }
@@ -4475 +4462 @@
 
 #ifdef VBOX_STRICT
-        /* Validate. */
-        hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
+        hmR0VmxValidateSegmentRegs(pVCpu, pMixedCtx);
 #endif
 
@@ -4494 +4480 @@
     {
         /*
-         * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is achieved
-         * using the interrupt redirection bitmap (all bits cleared to let the guest handle INT-n's) in the TSS.
-         * See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
+         * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is
+         * achieved using the interrupt redirection bitmap (all bits cleared to let the guest
+         * handle INT-n's) in the TSS. See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
          */
         uint16_t u16Sel          = 0;
@@ -4882 +4868 @@
  *
  * @returns VBox status code, no informational status codes.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -4888 +4873 @@
  * @remarks No-long-jump zone!!!
  */
-DECLINLINE(int) hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+DECLINLINE(int) hmR0VmxRunGuest(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
@@ -4902 +4887 @@
     bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
     /** @todo Add stats for resume vs launch. */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
 #ifdef VBOX_WITH_KERNEL_USING_XMM
     int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
@@ -4915 +4901 @@
  * Reports world-switch error and dumps some useful debug info.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   rcVMRun         The return code from VMLAUNCH/VMRESUME.
@@ -4922 +4907 @@
  *                          exitReason updated).
  */
-static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
-{
-    Assert(pVM);
+static void hmR0VmxReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
+{
     Assert(pVCpu);
     Assert(pCtx);
@@ -5007 +4991 @@
                 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg);           AssertRC(rc);
                 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW           %#RHr\n", uHCReg));
-                if (pVM->hm.s.fNestedPaging)
+                if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
                 {
                     rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val);             AssertRC(rc);
@@ -5020 +5004 @@
                 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val);         AssertRC(rc);
                 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
-                if (pVM->hm.s.vmx.fVpid)
+                if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid)
                 {
                     rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val);           AssertRC(rc);
@@ -5126 +5110 @@
             break;
     }
-    NOREF(pVM); NOREF(pCtx);
+    NOREF(pCtx);
 }
 
@@ -5341 +5325 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  */
-static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu)
-{
-#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField)       \
-{                                                              \
-    Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0);    \
-    pCache->Read.aField[idxField##_CACHE_IDX] = idxField;      \
-    pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0;          \
-    ++cReadFields;                                             \
-}
-
-    AssertPtr(pVM);
-    AssertPtr(pVCpu);
+static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu)
+{
+#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField)           \
+    do {                                                           \
+        Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0);    \
+        pCache->Read.aField[idxField##_CACHE_IDX]    = idxField;   \
+        pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0;          \
+        ++cReadFields;                                             \
+    } while (0)
+
     PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
     uint32_t cReadFields = 0;
@@ -5411 +5392 @@
 #endif
 
-    if (pVM->hm.s.fNestedPaging)
+    if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
     {
         VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
@@ -5569 +5550 @@
  *
  * @returns VBox status code.
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  *
  * @remarks No-long-jump zone!!!
  */
-static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVM pVM, PVMCPU pVCpu)
+static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPU pVCpu)
 {
     int  rc;
     bool fOffsettedTsc;
     bool fParavirtTsc;
+    PVM  pVM = pVCpu->CTX_SUFF(pVM);
     if (pVM->hm.s.vmx.fUsePreemptTimer)
     {
@@ -6365 +6346 @@
             {
                 uint32_t u32Shadow;
-                /* CR0 required for saving CR3 below, see CPUMIsGuestPagingEnabledEx(). */
                 if (fWhat & CPUMCTX_EXTRN_CR0)
                 {
@@ -6378 +6358 @@
                 }
 
-                /* CR4 required for saving CR3 below, see CPUMIsGuestInPAEModeEx(). */
                 if (fWhat & CPUMCTX_EXTRN_CR4)
                 {
@@ -6391 +6370 @@
                 if (fWhat & CPUMCTX_EXTRN_CR3)
                 {
+                    /* CR0.PG bit changes are always intercepted, so it's up to date. */
                     if (   pVM->hm.s.vmx.fUnrestrictedGuest
                         || (   pVM->hm.s.fNestedPaging
-                            && CPUMIsGuestPagingEnabledEx(pCtx))) /* PG bit changes are always intercepted, so it's up to date. */
+                            && CPUMIsGuestPagingEnabledEx(pCtx)))
                     {
                         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
@@ -6402 +6382 @@
                         }
 
-                        /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
+                        /* If the guest is in PAE mode, sync back the PDPE's into the guest state.
+                           Note: CR4.PAE, CR0.PG, EFER bit changes are always intercepted, so they're up to date. */
                         if (CPUMIsGuestInPAEModeEx(pCtx))
                         {
@@ -6501 +6482 @@
  *         to the EM loop.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pMixedCtx       Pointer to the guest-CPU context. The data may be
@@ -6508 +6488 @@
  * @param   fStepping       Running in hmR0VmxRunGuestCodeStep().
  */
-static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping)
+static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping)
 {
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
+
+    /* Pending HM CR3 sync. */
+    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
+    {
+        Assert(!(ASMAtomicUoReadU64(&pMixedCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
+        int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
+        AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
+                        ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
+        Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
+    }
+
+    /* Pending HM PAE PDPEs. */
+    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
+    {
+        PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
+        Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
+    }
 
     /*
      * Anything pending?  Should be more likely than not if we're doing a good job.
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (  !fStepping
         ?    !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK)
@@ -6521 +6519 @@
           && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
         return VINF_SUCCESS;
-
-#if 0
-    /* We need the control registers now, make sure the guest-CPU context is updated. */
-    int rc3 = hmR0VmxImportGuestStatae(pVCpu, CPUMCTX_EXTRN_CR0);
-    AssertRCReturn(rc3, rc3);
-
-    /** @todo  r=ramshankar: VMCPU_FF_HM_UPDATE_CR3 and VMCPU_FF_HM_UPDATE_PAE_PDPES
-     *         are not part of VMCPU_FF_HP_R0_PRE_HM_MASK. Hence, the two if
-     *         statements below won't ever be entered. Consider removing it or
-     *         determine if it is necessary to add these flags to VMCPU_FF_HP_R0_PRE_HM_MASK. */
-    /* Pending HM CR3 sync. */
-    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
-    {
-        int rc2 = PGMUpdateCR3(pVCpu, pMixedCtx->cr3);
-        AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
-                        ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
-        Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
-    }
-
-    /* Pending HM PAE PDPEs. */
-    if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
-    {
-        PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
-        Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
-    }
-#endif
 
     /* Pending PGM C3 sync. */
@@ -6813 +6785 @@
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
-    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
-    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
+    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
+    STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
     STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
@@ -6915 +6887 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pMixedCtx   Pointer to the guest-CPU context. The data may be
@@ -6923 +6894 @@
  *                      VINF_VMM_UNKNOWN_RING3_CALL.
  */
-static int hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, VBOXSTRICTRC rcExit)
-{
-    Assert(pVM);
+static int hmR0VmxExitToRing3(PVMCPU pVCpu, PCPUMCTX pMixedCtx, VBOXSTRICTRC rcExit)
+{
     Assert(pVCpu);
     Assert(pMixedCtx);
@@ -6973 +6943 @@
                               | CPUM_CHANGED_TR
                               | CPUM_CHANGED_HIDDEN_SEL_REGS);
-    if (   pVM->hm.s.fNestedPaging
+    if (   pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
         && CPUMIsGuestPagingEnabledEx(pMixedCtx))
     {
@@ -7314 +7284 @@
         }
 #endif
-        Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#x\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
-              (uint8_t)uIntType));
+        Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
+              uIntType));
         rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
                                           pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress, fStepping,
@@ -7583 +7553 @@
  *                              directly (register modified by us, not by
  *                              hardware on VM-entry).
- *
- * @remarks Requires CR0!
  */
 static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
@@ -7590 +7558 @@
 {
     /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
-    AssertMsg(u64IntInfo >> 32 == 0, ("%#RX64\n", u64IntInfo));
+    AssertMsg(!RT_HI_U32(u64IntInfo), ("%#RX64\n", u64IntInfo));
     Assert(pfIntrState);
 
@@ -7601 +7569 @@
     /*
      * Validate the error-code-valid bit for hardware exceptions.
-     * No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling"
+     * No error codes for exceptions in real-mode.
+     *
+     * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
      */
     if (   uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
@@ -7630 +7600 @@
     STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
 
-    /* We require CR0 to check if the guest is in real-mode. */
-    /** @todo No we don't, since CR0.PE is always intercepted. */
-    int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
-    AssertRCReturn(rc, rc);
-
     /*
      * Hardware interrupts & exceptions cannot be delivered through the software interrupt
@@ -7643 +7608 @@
      * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
      */
-    if (CPUMIsGuestInRealModeEx(pMixedCtx))
+    if (CPUMIsGuestInRealModeEx(pMixedCtx))     /* CR0.PE bit changes are always intercepted, so it's up to date. */
     {
         if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest)
         {
             /*
-             * For unrestricted execution enabled CPUs running real-mode guests, we must not                              .
-             * set the deliver-error-code bit                                                                             .
-             *                                                                                                            .
+             * For unrestricted execution enabled CPUs running real-mode guests, we must not
+             * set the deliver-error-code bit.
+             *
              * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
              */
@@ -7662 +7627 @@
 
             /* We require RIP, RSP, RFLAGS, CS, IDTR, import them. */
-            rc = hmR0VmxImportGuestState(pVCpu,   CPUMCTX_EXTRN_SREG_MASK
-                                                | CPUMCTX_EXTRN_TABLE_MASK
-                                                | CPUMCTX_EXTRN_RIP
-                                                | CPUMCTX_EXTRN_RSP
-                                                | CPUMCTX_EXTRN_RFLAGS);
-            AssertRCReturn(rc, rc);
+            int rc2 = hmR0VmxImportGuestState(pVCpu,   CPUMCTX_EXTRN_SREG_MASK
+                                                     | CPUMCTX_EXTRN_TABLE_MASK
+                                                     | CPUMCTX_EXTRN_RIP
+                                                     | CPUMCTX_EXTRN_RSP
+                                                     | CPUMCTX_EXTRN_RFLAGS);
+            AssertRCReturn(rc2, rc2);
 
             /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
@@ -7681 +7646 @@
                     return hmR0VmxInjectXcptDF(pVCpu, pMixedCtx, fStepping, pfIntrState);
 
-                /* If we're injecting an interrupt/exception with no valid IDT entry, inject a general-protection fault. */
-                /* No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling" */
-                return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid */, 0 /* u32ErrCode */,
-                                           fStepping, pfIntrState);
+                /*
+                 * If we're injecting an event with no valid IDT entry, inject a #GP.
+                 * No error codes for exceptions in real-mode.
+                 *
+                 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
+                 */
+                return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid */, 0 /* u32ErrCode */, fStepping,
+                                           pfIntrState);
             }
 
@@ -7701 +7670 @@
             X86IDTR16 IdtEntry;
             RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
-            rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
-            AssertRCReturn(rc, rc);
+            rc2 = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
+            AssertRCReturn(rc2, rc2);
 
             /* Construct the stack frame for the interrupt/exception handler. */
@@ -7763 +7732 @@
 
     /* Inject. */
-    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
+    int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
     if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo))
         rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
@@ -7769 +7738 @@
     AssertRCReturn(rc, rc);
 
+    /* Update CR2. */
     if (   VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
         && uVector == X86_XCPT_PF)
         pMixedCtx->cr2 = GCPtrFaultAddress;
 
-    Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x pMixedCtx->uCR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr,
-          pMixedCtx->cr2));
+    Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x CR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
 
     return VINF_SUCCESS;
@@ -7811 +7780 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
- * @param   pCpu        Pointer to the CPU info struct.
- */
-VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
-{
-    AssertPtr(pVM);
+ * @param   pHostCpu    Pointer to the global CPU info struct.
+ */
+VMMR0DECL(int) VMXR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
+{
     AssertPtr(pVCpu);
-    Assert(pVM->hm.s.vmx.fSupported);
+    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
-    NOREF(pCpu); NOREF(pVM);
-
-    LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
+    RT_NOREF(pHostCpu);
+
+    LogFlowFunc(("pVCpu=%p\n", pVCpu));
     Assert((pVCpu->hm.s.fCtxChanged &  (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
                                     == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
@@ -7912 +7879 @@
             /* Initialize the bare minimum state required for HM. This takes care of
                initializing VT-x if necessary (onlined CPUs, local init etc.) */
-            int rc = HMR0EnterCpu(pVCpu);
+            int rc = hmR0EnterCpu(pVCpu);
             AssertRC(rc);
             Assert((pVCpu->hm.s.fCtxChanged &  (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
@@ -8009 +7976 @@
  *          mapped (e.g. EFI32).
  *
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pMixedCtx   Pointer to the guest-CPU context. The data may be
@@ -8017 +7983 @@
  * @remarks No-long-jump zone!!!
  */
-static VBOXSTRICTRC hmR0VmxExportGuestState(PVM pVM, PVMCPU pVCpu, PCCPUMCTX pMixedCtx)
-{
-    AssertPtr(pVM);
+static VBOXSTRICTRC hmR0VmxExportGuestState(PVMCPU pVCpu, PCCPUMCTX pMixedCtx)
+{
     AssertPtr(pVCpu);
     AssertPtr(pMixedCtx);
     HMVMX_ASSERT_PREEMPT_SAFE();
 
-    LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
+    LogFlowFunc(("pVCpu=%p\n", pVCpu));
 
     STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
@@ -8030 +7995 @@
     /* Determine real-on-v86 mode. */
     pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
-    if (   !pVM->hm.s.vmx.fUnrestrictedGuest
-        && CPUMIsGuestInRealModeEx(pMixedCtx))
+    if (   !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
+        &&  CPUMIsGuestInRealModeEx(pMixedCtx))
     {
         pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
@@ -8108 +8073 @@
  * Exports the state shared between the host and guest into the VMCS.
  *
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -8114 +8078 @@
  * @remarks No-long-jump zone!!!
  */
-static void hmR0VmxExportSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
-    NOREF(pVM);
-
+static void hmR0VmxExportSharedState(PVMCPU pVCpu, PCPUMCTX pCtx)
+{
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
@@ -8154 +8116 @@
  *          mapped (e.g. EFI32).
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pMixedCtx       Pointer to the guest-CPU context. The data may be
@@ -8162 +8123 @@
  * @remarks No-long-jump zone!!!
  */
-static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCCPUMCTX pMixedCtx)
+static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPU pVCpu, PCCPUMCTX pMixedCtx)
 {
     HMVMX_ASSERT_PREEMPT_SAFE();
@@ -8189 +8150 @@
     else if (fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
     {
-        rcStrict = hmR0VmxExportGuestState(pVM, pVCpu, pMixedCtx);
+        rcStrict = hmR0VmxExportGuestState(pVCpu, pMixedCtx);
         if (RT_LIKELY(rcStrict == VINF_SUCCESS))
         { /* likely */}
@@ -8236 +8197 @@
  * @retval  VINF_* scheduling changes, we have to go back to ring-3.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pMixedCtx       Pointer to the guest-CPU context. The data may be
@@ -8247 +8207 @@
  *                          dispatching took place.
  */
-static VBOXSTRICTRC hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping)
+static VBOXSTRICTRC hmR0VmxPreRunGuest(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping)
 {
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
@@ -8256 +8216 @@
 
     /* Check force flag actions that might require us to go back to ring-3. */
-    VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVM, pVCpu, pMixedCtx, fStepping);
+    VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVCpu, pMixedCtx, fStepping);
     if (rcStrict == VINF_SUCCESS)
     { /* FFs doesn't get set all the time. */ }
@@ -8270 +8230 @@
      * This is the reason we do it here and not in hmR0VmxExportGuestState().
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (   !pVCpu->hm.s.vmx.u64MsrApicBase
         && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
@@ -8298 +8259 @@
 
     /*
-     * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus needs to be done with
-     * longjmps or interrupts + preemption enabled. Event injection might also result in triple-faulting the VM.
+     * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
+     * needs to be done with longjmps or interrupts + preemption enabled. Event injection might
+     * also result in triple-faulting the VM.
      */
     rcStrict = hmR0VmxInjectPendingEvent(pVCpu, pMixedCtx, fIntrState, fStepping);
@@ -8329 +8291 @@
      * Hence, loading of the guest state needs to be done -after- injection of events.
      */
-    rcStrict = hmR0VmxExportGuestStateOptimal(pVM, pVCpu, pMixedCtx);
+    rcStrict = hmR0VmxExportGuestStateOptimal(pVCpu, pMixedCtx);
     if (RT_LIKELY(rcStrict == VINF_SUCCESS))
     { /* likely */ }
@@ -8339 +8301 @@
 
     /*
-     * We disable interrupts so that we don't miss any interrupts that would flag
-     * preemption (IPI/timers etc.) when thread-context hooks aren't used and we've
-     * been running with preemption disabled for a while.  Since this is purly to aid
-     * the RTThreadPreemptIsPending code, it doesn't matter that it may temporarily
-     * reenable and disable interrupt on NT.
+     * We disable interrupts so that we don't miss any interrupts that would flag preemption
+     * (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
+     * preemption disabled for a while.  Since this is purly to aid the
+     * RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
+     * disable interrupt on NT.
      *
-     * We need to check for force-flags that could've possible been altered since we last checked them (e.g.
-     * by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
+     * We need to check for force-flags that could've possible been altered since we last
+     * checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
+     * see @bugref{6398}).
      *
-     * We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
-     * executing guest code.
+     * We also check a couple of other force-flags as a last opportunity to get the EMT back
+     * to ring-3 before executing guest code.
      */
     pVmxTransient->fEFlags = ASMIntDisableFlags();
@@ -8392 +8355 @@
  * point.
  *
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pMixedCtx       Pointer to the guest-CPU context. The data may be
@@ -8402 +8364 @@
  * @remarks No-long-jump zone!!!
  */
-static void hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
+static void hmR0VmxPreRunGuestCommitted(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
 {
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
@@ -8414 +8376 @@
     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
 
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (!CPUMIsGuestFPUStateActive(pVCpu))
     {
@@ -8449 +8412 @@
      */
     if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)
-        hmR0VmxExportSharedState(pVM, pVCpu, pMixedCtx);
+        hmR0VmxExportSharedState(pVCpu, pMixedCtx);
     AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
 
@@ -8477 +8440 @@
         || idCurrentCpu != pVCpu->hm.s.idLastCpu)
     {
-        hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVM, pVCpu);
+        hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu);
         pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
     }
@@ -8532 +8495 @@
 #endif
 #ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
-    uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVM, pVCpu, pMixedCtx);
+    uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu, pMixedCtx);
     if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
         Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
@@ -8567 +8530 @@
         TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.u64TSCOffset);
 
-    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
+    STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
     TMNotifyEndOfExecution(pVCpu);                                    /* Notify TM that the guest is no longer running. */
     Assert(!ASMIntAreEnabled());
@@ -8664 +8627 @@
  *
  * @returns VBox status code.
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -8670 +8632 @@
  * @note    Mostly the same as hmR0VmxRunGuestCodeStep().
  */
-static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     VMXTRANSIENT VmxTransient;
@@ -8685 +8647 @@
            to ring-3.  This bugger disables interrupts on VINF_SUCCESS! */
         STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
-        rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, false /* fStepping */);
+        rcStrict = hmR0VmxPreRunGuest(pVCpu, pCtx, &VmxTransient, false /* fStepping */);
         if (rcStrict != VINF_SUCCESS)
             break;
 
-        hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
-        int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
+        hmR0VmxPreRunGuestCommitted(pVCpu, pCtx, &VmxTransient);
+        int rcRun = hmR0VmxRunGuest(pVCpu, pCtx);
         /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
 
@@ -8702 +8664 @@
         else
         {
-            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
-            hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
+            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
+            hmR0VmxReportWorldSwitchError(pVCpu, rcRun, pCtx, &VmxTransient);
             return rcRun;
         }
@@ -8711 +8673 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
         STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
-        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
         HMVMX_START_EXIT_DISPATCH_PROF();
 
@@ -8722 +8684 @@
         rcStrict = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
 #endif
-        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
         if (rcStrict == VINF_SUCCESS)
         {
-            if (cLoops <= pVM->hm.s.cMaxResumeLoops)
+            if (cLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
                 continue; /* likely */
             STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
@@ -9229 +9191 @@
  *
  * @returns Strict VBox status code (i.e. informational status codes too).
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   pMixedCtx       Pointer to the guest-CPU context.
@@ -9238 +9199 @@
  *          and to the point. No longer than 33 chars long, please.
  */
-static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx,
-                                                  PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
+static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
+                                                  uint32_t uExitReason)
 {
     /*
@@ -9586 +9547 @@
      *       one, in order to avoid event nesting.
      */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (   enmEvent1 != DBGFEVENT_END
         && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
@@ -9613 +9575 @@
  *
  * @returns Strict VBox status code (i.e. informational status codes too).
- * @param   pVM             The cross context VM structure.
  * @param   pVCpu           The cross context virtual CPU structure of the calling EMT.
  * @param   pMixedCtx       Pointer to the guest-CPU context. The data may be
@@ -9622 +9583 @@
  * @param   pDbgState       The debug state.
  */
-DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
+DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
                                                    uint32_t uExitReason, PVMXRUNDBGSTATE pDbgState)
 {
@@ -9748 +9709 @@
         && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
     {
-        VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVM, pVCpu, pMixedCtx, pVmxTransient, uExitReason);
+        VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVCpu, pMixedCtx, pVmxTransient, uExitReason);
         if (rcStrict != VINF_SUCCESS)
             return rcStrict;
@@ -9768 +9729 @@
  *
  * @returns Strict VBox status code (i.e. informational status codes too).
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
@@ -9774 +9734 @@
  * @note    Mostly the same as hmR0VmxRunGuestCodeNormal().
  */
-static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     VMXTRANSIENT VmxTransient;
@@ -9806 +9766 @@
         STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
         hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
-        rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, fStepping);
+        rcStrict = hmR0VmxPreRunGuest(pVCpu, pCtx, &VmxTransient, fStepping);
         if (rcStrict != VINF_SUCCESS)
             break;
 
-        hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
+        hmR0VmxPreRunGuestCommitted(pVCpu, pCtx, &VmxTransient);
         hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
 
@@ -9816 +9776 @@
          * Now we can run the guest code.
          */
-        int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
+        int rcRun = hmR0VmxRunGuest(pVCpu, pCtx);
 
         /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
@@ -9831 +9791 @@
         else
         {
-            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
-            hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
+            STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
+            hmR0VmxReportWorldSwitchError(pVCpu, rcRun, pCtx, &VmxTransient);
             return rcRun;
         }
@@ -9840 +9800 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
         STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
-        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
+        STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
         HMVMX_START_EXIT_DISPATCH_PROF();
 
@@ -9848 +9808 @@
          * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
          */
-        rcStrict = hmR0VmxRunDebugHandleExit(pVM, pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason, &DbgState);
-        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
+        rcStrict = hmR0VmxRunDebugHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason, &DbgState);
+        STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
         if (rcStrict != VINF_SUCCESS)
             break;
-        if (cLoops > pVM->hm.s.cMaxResumeLoops)
+        if (cLoops > pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
         {
             STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
@@ -10058 +10018 @@
  *
  * @returns Strict VBox status code (i.e. informational status codes too).
- * @param   pVM         The cross context VM structure.
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pCtx        Pointer to the guest-CPU context.
  */
-VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
@@ -10074 +10033 @@
         && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
         && !DBGFIsStepping(pVCpu)
-        && !pVM->dbgf.ro.cEnabledInt3Breakpoints)
-        rcStrict = hmR0VmxRunGuestCodeNormal(pVM, pVCpu, pCtx);
+        && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
+        rcStrict = hmR0VmxRunGuestCodeNormal(pVCpu, pCtx);
     else
-        rcStrict = hmR0VmxRunGuestCodeDebug(pVM, pVCpu, pCtx);
+        rcStrict = hmR0VmxRunGuestCodeDebug(pVCpu, pCtx);
 
     if (rcStrict == VERR_EM_INTERPRETER)
@@ -10084 +10043 @@
         rcStrict = VINF_EM_TRIPLE_FAULT;
 
-    int rc2 = hmR0VmxExitToRing3(pVM, pVCpu, pCtx, rcStrict);
+    int rc2 = hmR0VmxExitToRing3(pVCpu, pCtx, rcStrict);
     if (RT_FAILURE(rc2))
     {
@@ -10297 +10256 @@
  *         wrong with the guest state.
  *
- * @param   pVM     The cross context VM structure.
  * @param   pVCpu   The cross context virtual CPU structure.
  * @param   pCtx    Pointer to the guest-CPU state.
@@ -10304 +10262 @@
  *          are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
  */
-static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
 #define HMVMX_ERROR_BREAK(err)              { uError = (err); break; }
@@ -10312 +10270 @@
                                             } else do { } while (0)
 
-    int      rc;
-    uint32_t uError             = VMX_IGS_ERROR;
-    uint32_t u32Val;
-    bool     fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
+    int        rc;
+    PVM        pVM = pVCpu->CTX_SUFF(pVM);
+    uint32_t   uError = VMX_IGS_ERROR;
+    uint32_t   u32Val;
+    bool const fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
 
     do
@@ -10628 +10587 @@
             HMVMX_CHECK_BREAK(   (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
                               || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
-            HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
+            HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
+            HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
                               VMX_IGS_LONGMODE_SS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
+            HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
                               VMX_IGS_LONGMODE_DS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
+            HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
                               VMX_IGS_LONGMODE_ES_BASE_INVALID);
 #endif
@@ -10684 +10643 @@
             HMVMX_CHECK_BREAK(   (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
                               || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
-            HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
+            HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
+            HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
                               VMX_IGS_LONGMODE_SS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
+            HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
                               VMX_IGS_LONGMODE_DS_BASE_INVALID);
-            HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
+            HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
                               VMX_IGS_LONGMODE_ES_BASE_INVALID);
 #endif
@@ -11607 +11566 @@
     AssertRCReturn(rc, rc);
 
-    uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
+    uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu, pMixedCtx);
     NOREF(uInvalidReason);
 
@@ -11640 +11599 @@
     rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val);                 AssertRC(rc);
     Log4(("VMX_VMCS64_CTRL_EPTP_FULL                  %#RX64\n", u64Val));
+
+    hmR0DumpRegs(pVCpu, pMixedCtx);
 #else
     NOREF(pVmxTransient);
 #endif
 
-    hmR0DumpRegs(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
     return VERR_VMX_INVALID_GUEST_STATE;
 }

trunk/src/VBox/VMM/VMMR0/HMVMXR0.h

@@ -29 +29 @@
 #ifdef IN_RING0
 
-VMMR0DECL(int)          VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
+VMMR0DECL(int)          VMXR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu);
 VMMR0DECL(void)         VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
-VMMR0DECL(int)          VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys,
+VMMR0DECL(int)          VMXR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys,
                                        bool fEnabledBySystem, void *pvMsrs);
-VMMR0DECL(int)          VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int)          VMXR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 VMMR0DECL(int)          VMXR0GlobalInit(void);
 VMMR0DECL(void)         VMXR0GlobalTerm(void);
@@ -40 +40 @@
 VMMR0DECL(int)          VMXR0SetupVM(PVM pVM);
 VMMR0DECL(int)          VMXR0ExportHostState(PVMCPU pVCpu);
-VMMR0DECL(int)          VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
+VMMR0DECL(int)          VMXR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
 VMMR0DECL(int)          VMXR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
-VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu, PCPUMCTX pCtx);
 DECLASM(int)            VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
 DECLASM(int)            VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);

trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

@@ -1237 +1237 @@
                      * Enter HM context.
                      */
-                    rc = HMR0Enter(pVM, pVCpu);
+                    rc = HMR0Enter(pVCpu);
                     if (RT_SUCCESS(rc))
                     {

trunk/src/VBox/VMM/VMMR3/HM.cpp

@@ -140 +140 @@
     EXIT_REASON(VMX_EXIT_INVPCID                ,  58, "INVPCID instruction."),
     EXIT_REASON(VMX_EXIT_VMFUNC                 ,  59, "VMFUNC instruction."),
-    EXIT_REASON(VMX_EXIT_ENCLS                  ,  60, "ENCLS instrunction."),
+    EXIT_REASON(VMX_EXIT_ENCLS                  ,  60, "ENCLS instruction."),
     EXIT_REASON(VMX_EXIT_RDSEED                 ,  61, "RDSEED instruction."),
     EXIT_REASON(VMX_EXIT_PML_FULL               ,  62, "Page-modification log full."),
@@ -258 +258 @@
     EXIT_REASON(SVM_EXIT_INIT         ,   99, "Physical INIT signal (host)."),
     EXIT_REASON(SVM_EXIT_VINTR        ,  100, "Virtual interrupt-window exit."),
-    EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE,  101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
-    EXIT_REASON(SVM_EXIT_IDTR_READ    ,  102, "Read IDTR"),
-    EXIT_REASON(SVM_EXIT_GDTR_READ    ,  103, "Read GDTR"),
+    EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE,  101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
+    EXIT_REASON(SVM_EXIT_IDTR_READ    ,  102, "Read IDTR."),
+    EXIT_REASON(SVM_EXIT_GDTR_READ    ,  103, "Read GDTR."),
     EXIT_REASON(SVM_EXIT_LDTR_READ    ,  104, "Read LDTR."),
     EXIT_REASON(SVM_EXIT_TR_READ      ,  105, "Read TR."),
@@ -280 +280 @@
     EXIT_REASON(SVM_EXIT_INVLPG       ,  121, "INVLPG instruction."),
     EXIT_REASON(SVM_EXIT_INVLPGA      ,  122, "INVLPGA instruction."),
-    EXIT_REASON(SVM_EXIT_IOIO         ,  123, "IN/OUT accessing protected port."),
+    EXIT_REASON(SVM_EXIT_IOIO         ,  123, "IN/OUT/INS/OUTS instruction."),
     EXIT_REASON(SVM_EXIT_MSR          ,  124, "RDMSR or WRMSR access to protected MSR."),
     EXIT_REASON(SVM_EXIT_TASK_SWITCH  ,  125, "Task switch."),
-    EXIT_REASON(SVM_EXIT_FERR_FREEZE  ,  126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
+    EXIT_REASON(SVM_EXIT_FERR_FREEZE  ,  126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
     EXIT_REASON(SVM_EXIT_SHUTDOWN     ,  127, "Shutdown."),
     EXIT_REASON(SVM_EXIT_VMRUN        ,  128, "VMRUN instruction."),
@@ -883 +883 @@
                              "/PROF/CPU%d/HM/StatEntry", i);
         AssertRC(rc);
-        rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
-                             "Profiling of VMXR0RunGuestCode exit part 1",
+        rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
+                             "Profiling of pre-exit processing after returning from GC",
                              "/PROF/CPU%d/HM/SwitchFromGC_1", i);
         AssertRC(rc);
-        rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
-                             "Profiling of VMXR0RunGuestCode exit part 2",
+        rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
+                             "Profiling of exit handling (longjmps not included!)",
                              "/PROF/CPU%d/HM/SwitchFromGC_2", i);
         AssertRC(rc);
@@ -958 +958 @@
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF,            "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk,        "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt,                "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr,              "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr,              "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait,              "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor,            "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite,           "/HM/CPU%d/Exit/Instr/DR-Write", "Guest attempted to write a debug register.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead,            "/HM/CPU%d/Exit/Instr/DR-Read", "Guest attempted to read a debug register.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "Guest attempted to read CR0.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "Guest attempted to read CR2.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "Guest attempted to read CR3.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "Guest attempted to read CR4.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "Guest attempted to read CR8.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "Guest attempted to write CR0.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "Guest attempted to write CR2.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "Guest attempted to write CR3.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "Guest attempted to write CR4.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "Guest attempted to write CR8.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts,               "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw,               "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli,                "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti,                "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf,              "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf,               "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret,               "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt,                "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess,         "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt,                "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr,              "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr,              "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait,              "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor,            "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite,           "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead,            "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read,            "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write,           "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts,               "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw,               "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli,                "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti,                "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf,              "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf,               "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret,               "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt,                "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess,         "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite,            "/HM/CPU%d/Exit/IO/Write", "I/O write.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead,             "/HM/CPU%d/Exit/IO/Read", "I/O read.");
@@ -989 +989 @@
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead,       "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow,          "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt,             "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt,             "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
 #endif
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC,        "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
@@ -995 +995 @@
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer,       "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold,  "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
-        HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch,         "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
+        HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch,         "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf,                "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
         HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess,         "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
@@ -1590 +1590 @@
 
             /*
-             * Construct a 1024 element page directory with 4 MB pages for
-             * the identity mapped page table used in real and protected mode
-             * without paging with EPT.
+             * Construct a 1024 element page directory with 4 MB pages for the identity mapped
+             * page table used in real and protected mode without paging with EPT.
              */
             pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
@@ -2104 +2103 @@
 #ifdef LOG_ENABLED
         char            szOutput[256];
-
         rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                                 szOutput, sizeof(szOutput), NULL);
@@ -2473 +2471 @@
              * pop ECX                       [59]
              * jmp return_address            [E9 return_address]
-             *
              */
             bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
@@ -2524 +2521 @@
              * pop ECX                       [59]
              * jmp return_address            [E9 return_address]
-             *
              */
             Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
@@ -2730 +2726 @@
                         /*
                          * The following two requirements are VT-x specific:
-                         *  - G bit must be set if any high limit bits are set.
-                         *  - G bit must be clear if any low limit bits are clear.
+                         *   - G bit must be set if any high limit bits are set.
+                         *   - G bit must be clear if any low limit bits are clear.
                          */
                         if (   ((pSel->u32Limit & 0xfff00000) == 0x00000000 ||  pSel->Attr.n.u1Granularity)
@@ -2773 +2769 @@
     AssertMsgReturn(   (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
                     ==                 (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
-                    ("%#x\n", pSel->Attr.u),
-                    false);
+                    ("%#x\n", pSel->Attr.u), false);
 
     /* DPL must equal RPL.
        Note! This is also a hard requirement like above. */
     AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
-                    ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
-                    false);
+                    ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel), false);
 
     /*
      * The following two requirements are VT-x specific:
-     *  - G bit must be set if any high limit bits are set.
-     *  - G bit must be clear if any low limit bits are clear.
+     *   - G bit must be set if any high limit bits are set.
+     *   - G bit must be clear if any low limit bits are clear.
      */
     if (   ((pSel->u32Limit & 0xfff00000) == 0x00000000 ||  pSel->Attr.n.u1Granularity)
@@ -2843 +2837 @@
 
     /* If we're still executing the IO code, then return false. */
-    if (    RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
-        &&  pCtx->rip <  pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
-        &&  pCtx->rip >  pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
-        &&  pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
+    if (   RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
+        && pCtx->rip <  pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
+        && pCtx->rip >  pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
+        && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
         return false;
 
@@ -2875 +2869 @@
             if (CPUMIsGuestInRealModeEx(pCtx))
             {
-                /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
+                /*
+                 * In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
                  * bases and limits, i.e. limit must be 64K and base must be selector * 16.
                  * If this is not true, we cannot execute real mode as V86 and have to fall
@@ -2904 +2899 @@
             else
             {
-                /* Verify the requirements for executing code in protected
-                   mode. VT-x can't handle the CPU state right after a switch
-                   from real to protected mode. (all sorts of RPL & DPL assumptions). */
+                /*
+                 * Verify the requirements for executing code in protected mode. VT-x can't
+                 * handle the CPU state right after a switch from real to protected mode
+                 * (all sorts of RPL & DPL assumptions).
+                 */
                 if (pVCpu->hm.s.vmx.fWasInRealMode)
                 {
@@ -2945 +2942 @@
         else
         {
-            if (    !CPUMIsGuestInLongModeEx(pCtx)
-                &&  !pVM->hm.s.vmx.fUnrestrictedGuest)
+            if (   !CPUMIsGuestInLongModeEx(pCtx)
+                && !pVM->hm.s.vmx.fUnrestrictedGuest)
             {
                 if (   !pVM->hm.s.fNestedPaging        /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
@@ -2956 +2953 @@
                     return false;
 
-                /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
-                /* Windows XP; switch to protected mode; all selectors are marked not present in the
-                 * hidden registers (possible recompiler bug; see load_seg_vm) */
+                /*
+                 * The guest is about to complete the switch to protected mode. Wait a bit longer.
+                 * Windows XP; switch to protected mode; all selectors are marked not present
+                 * in the hidden registers (possible recompiler bug; see load_seg_vm).
+                 */
                 /** @todo Is this supposed recompiler bug still relevant with IEM? */
                 if (pCtx->cs.Attr.n.u1Present == 0)
@@ -2965 +2964 @@
                     return false;
 
-                /* Windows XP: possible same as above, but new recompiler requires new heuristics?
-                   VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
+                /*
+                 * Windows XP: possible same as above, but new recompiler requires new
+                 * heuristics? VT-x doesn't seem to like something about the guest state and
+                 * this stuff avoids it.
+                 */
                 /** @todo This check is actually wrong, it doesn't take the direction of the
                  *        stack segment into account. But, it does the job for now. */

trunk/src/VBox/VMM/include/HMInternal.h

@@ -921 +921 @@
     } EmulateIoBlock;
 
-    /* */
+    /* Pending IO operation. */
     struct
     {
@@ -957 +957 @@
 
     STAMPROFILEADV          StatEntry;
-    STAMPROFILEADV          StatExit1;
-    STAMPROFILEADV          StatExit2;
+    STAMPROFILEADV          StatPreExit;
+    STAMPROFILEADV          StatExitHandling;
     STAMPROFILEADV          StatExitIO;
     STAMPROFILEADV          StatExitMovCRx;
@@ -1114 +1114 @@
 #ifdef IN_RING0
 VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
+VMMR0_INT_DECL(int)              hmR0EnterCpu(PVMCPU pVCpu);
 
 # ifdef VBOX_STRICT
-VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu, PCPUMCTX pCtx);
 VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
-# else
-#  define hmR0DumpRegs(a, b ,c)          do { } while (0)
-#  define hmR0DumpDescriptor(a, b, c)    do { } while (0)
-# endif /* VBOX_STRICT */
+# endif
 
 # ifdef VBOX_WITH_KERNEL_USING_XMM
@@ -1127 +1125 @@
 DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
 # endif
-
 #endif /* IN_RING0 */