VirtualBox

Changeset 72854 in vbox for trunk/include


Ignore:
Timestamp:
Jul 4, 2018 7:46:06 AM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
123399
Message:

VMM/HM: spaces, cleanup.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/hm_vmx.h

    r72750 r72854  
    735735/** @} */
    736736
    737 /** VMX VPID flush types.
     737/**
     738 * VMX VPID flush types.
    738739 * @note Valid enum members are in accordance to the VT-x spec.
    739740 */
    … …  
    755756AssertCompileSize(VMXFLUSHVPID, 4);
    756757
    757 /** VMX EPT flush types.
     758/**
     759 * VMX EPT flush types.
    758760 * @note Valid enums values are in accordance to the VT-x spec.
    759761 */
    … …  
    771773AssertCompileSize(VMXFLUSHEPT, 4);
    772774
    773 /** VMX Posted Interrupt Descriptor.
     775/**
     776 * VMX Posted Interrupt Descriptor.
    774777 * In accordance to the VT-x spec.
    775778 */
    … …  
    788791typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
    789792
    790 /** VMX MSR autoload/store element.
     793/**
     794 * VMX MSR autoload/store element.
    791795 * In accordance to the VT-x spec.
    792796 */
    … …  
    807811
    808812/**
    809  * VMX-capability qword
     813 * VMX-capability qword.
    810814 */
    811815typedef union
    … …  
    828832typedef struct VMXMSRS
    829833{
    830     uint64_t                u64FeatureCtrl;
    831     uint64_t                u64BasicInfo;
    832     VMXCAPABILITY           VmxPinCtls;
    833     VMXCAPABILITY           VmxProcCtls;
    834     VMXCAPABILITY           VmxProcCtls2;
    835     VMXCAPABILITY           VmxExit;
    836     VMXCAPABILITY           VmxEntry;
    837     uint64_t                u64Misc;
    838     uint64_t                u64Cr0Fixed0;
    839     uint64_t                u64Cr0Fixed1;
    840     uint64_t                u64Cr4Fixed0;
    841     uint64_t                u64Cr4Fixed1;
    842     uint64_t                u64VmcsEnum;
    843     uint64_t                u64Vmfunc;
    844     uint64_t                u64EptVpidCaps;
     834    uint64_t        u64FeatureCtrl;
     835    uint64_t        u64BasicInfo;
     836    VMXCAPABILITY   VmxPinCtls;
     837    VMXCAPABILITY   VmxProcCtls;
     838    VMXCAPABILITY   VmxProcCtls2;
     839    VMXCAPABILITY   VmxExit;
     840    VMXCAPABILITY   VmxEntry;
     841    uint64_t        u64Misc;
     842    uint64_t        u64Cr0Fixed0;
     843    uint64_t        u64Cr0Fixed1;
     844    uint64_t        u64Cr4Fixed0;
     845    uint64_t        u64Cr4Fixed1;
     846    uint64_t        u64VmcsEnum;
     847    uint64_t        u64Vmfunc;
     848    uint64_t        u64EptVpidCaps;
    845849} VMXMSRS;
    846850AssertCompileSizeAlignment(VMXMSRS, 8);
    847851/** Pointer to a VMXMSRS struct. */
    848852typedef VMXMSRS *PVMXMSRS;
    849 
    850 /** @name VMX EFLAGS reserved bits.
    851  * @{
    852  */
    853 /** And-mask for setting reserved bits to zero */
    854 #define VMX_EFLAGS_RESERVED_0                                   (X86_EFL_1 | X86_EFL_LIVE_MASK)
    855 /** Or-mask for setting reserved bits to 1 */
    856 #define VMX_EFLAGS_RESERVED_1                                   X86_EFL_1
    857 /** @} */
    858853
    859854/** @name VMX Basic Exit Reasons.
    … …  
    944939/** 43 TPR below threshold. Guest software executed MOV to CR8. */
    945940#define VMX_EXIT_TPR_BELOW_THRESHOLD                            43
    946 /** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
     941/** 44 APIC access. Guest software attempted to access memory at a physical
     942 *  address on the APIC-access page. */
    947943#define VMX_EXIT_APIC_ACCESS                                    44
    948 /** 45 Virtualized EOI. EOI virtualization was performed for a virtual interrupt
    949 whose vector indexed a bit set in the EOI-exit bitmap. */
     944/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
     945 *  interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
    950946#define VMX_EXIT_VIRTUALIZED_EOI                                45
    951 /** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
     947/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
     948 *  SGDT, or SIDT. */
    952949#define VMX_EXIT_XDTR_ACCESS                                    46
    953 /** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
     950/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
     951 *  SLDT, or STR. */
    954952#define VMX_EXIT_TR_ACCESS                                      47
    955 /** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
     953/** 48 EPT violation. An attempt to access memory with a guest-physical address
     954 *  was disallowed by the configuration of the EPT paging structures. */
    956955#define VMX_EXIT_EPT_VIOLATION                                  48
    957 /** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
     956/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
     957 *  address encountered a misconfigured EPT paging-structure entry. */
    958958#define VMX_EXIT_EPT_MISCONFIG                                  49
    959959/** 50 INVEPT. Guest software attempted to execute INVEPT. */
    … …  
    10641064 */
    10651065#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a)              (((a) >> 48) & 1)
    1066 /** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
     1066/** Whether the processor supports the dual-monitor treatment of
     1067 *  system-management interrupts and system-management code. (always 1) */
    10671068#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a)                (((a) >> 49) & 1)
    10681069/** Memory type that must be used for the VMCS. */
    10691070#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a)                (((a) >> 50) & 0xF)
    1070 /** Whether the processor provides additional information for exits due to INS/OUTS. */
     1071/** Whether the processor provides additional information for exits due to
     1072 *  INS/OUTS. */
    10711073#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a)                ((a) & RT_BIT_64(54))
    10721074/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
    … …  
    10791081 * @{
    10801082 */
    1081 /** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
     1083/** Relationship between the preemption timer and tsc; count down every time bit
     1084 *  x of the tsc changes. */
    10821085#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a)                    ((a) & 0x1f)
    10831086/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
    … …  
    11451148
    11461149
    1147 /** @name VMCS field encoding - 16 bits guest fields
     1150/** @name VMCS field encoding: 16-bit guest fields.
    11481151 * @{
    11491152 */
    … …  
    11621165/** @} */
    11631166
    1164 /** @name VMCS field encoding - 16 bits host fields
     1167/** @name VMCS field encoding: 16-bits host fields.
    11651168 * @{
    11661169 */
    … …  
    11741177/** @}          */
    11751178
    1176 /** @name VMCS field encoding - 64 bits host fields
     1179/** @name VMCS field encoding: 64-bit host fields.
    11771180 * @{
    11781181 */
    … …  
    11861189
    11871190
    1188 /** @name VMCS field encoding - 64 Bits control fields
     1191/** @name VMCS field encoding: 64-bit control fields.
    11891192 * @{
    11901193 */
    … …  
    11931196#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL                        0x2002
    11941197#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH                        0x2003
    1195 
    1196 /* Optional */
    11971198#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL                         0x2004
    11981199#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH                         0x2005
    1199 
    12001200#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL                     0x2006
    12011201#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH                     0x2007
    12021202#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL                      0x2008
    12031203#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH                      0x2009
    1204 
    12051204#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL                     0x200A
    12061205#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH                     0x200B
    1207 
    12081206#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL                      0x200C
    12091207#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH                      0x200D
    1210 
    12111208#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL                         0x2010
    12121209#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH                         0x2011
    1213 
    1214 /** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
    12151210#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL                     0x2012
    12161211#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH                     0x2013
    1217 
    1218 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
    12191212#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL                    0x2014
    12201213#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH                    0x2015
    1221 
    1222 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
    12231214#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL                   0x2016
    12241215#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH                   0x2017
    1225 
    1226 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
    12271216#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL                       0x2018
    12281217#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH                       0x2019
    1229 
    1230 /** Extended page table pointer. */
    12311218#define VMX_VMCS64_CTRL_EPTP_FULL                               0x201A
    12321219#define VMX_VMCS64_CTRL_EPTP_HIGH                               0x201B
    1233 
    1234 /** EOI-exit bitmap 0. */
    12351220#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL                       0x201C
    12361221#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH                       0x201D
    1237 
    1238 /** EOI-exit bitmap 1. */
    12391222#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL                       0x201E
    12401223#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH                       0x201F
    1241 
    1242 /** EOI-exit bitmap 2. */
    12431224#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL                       0x2020
    12441225#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH                       0x2021
    1245 
    1246 /** EOI-exit bitmap 3. */
    12471226#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL                       0x2022
    12481227#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH                       0x2023
    1249 
    1250 /** Extended page table pointer lists. */
    12511228#define VMX_VMCS64_CTRL_EPTP_LIST_FULL                          0x2024
    12521229#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH                          0x2025
    1253 
    1254 /** VM-read bitmap. */
    12551230#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL                      0x2026
    12561231#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH                      0x2027
    1257 
    1258 /** VM-write bitmap. */
    12591232#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL                     0x2028
    12601233#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH                     0x2029
    1261 
    1262 /** Virtualization-exception information address. */
    12631234#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL                 0x202A
    12641235#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH                 0x202B
    1265 
    1266 /** XSS-exiting bitmap. */
    12671236#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL                 0x202C
    12681237#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH                 0x202D
    1269 
    1270 /** TSC multiplier. */
    12711238#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL                     0x2032
    12721239#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH                     0x2033
    1273 
    1274 /** VM-exit guest physical address. */
    12751240#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL                    0x2400
    12761241#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH                    0x2401
    … …  
    12781243
    12791244
    1280 /** @name VMCS field encoding - 64 Bits guest fields
     1245/** @name VMCS field encoding: 64-bit guest fields.
    12811246 * @{
    12821247 */
    … …  
    13021267
    13031268
    1304 /** @name VMCS field encoding - 32 Bits control fields
     1269/** @name VMCS field encoding: 32-bit control fields.
    13051270 * @{
    13061271 */
    … …  
    13291294 * @{
    13301295 */
    1331 /** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
     1296/** External interrupts cause VM-exits if set; otherwise dispatched through the
     1297 *  guest's IDT. */
    13321298#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT                     RT_BIT(0)
    1333 /** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
     1299/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
     1300 *  the guest's IDT. */
    13341301#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT                         RT_BIT(3)
    13351302/** Virtual NMIs. */
    … …  
    13601327/** VM-exit when executing the RDTSC/RDTSCP instruction. */
    13611328#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT                      RT_BIT(12)
    1362 /** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     1329/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
     1330 *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    13631331#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT                   RT_BIT(15)
    1364 /** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     1332/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
     1333 *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    13651334#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT                  RT_BIT(16)
    13661335/** VM-exit on CR8 loads. */
    … …  
    13861355/** VM-exit when executing the PAUSE instruction. */
    13871356#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT                      RT_BIT(30)
    1388 /** Determines whether the secondary processor based VM-execution controls are used. */
     1357/** Whether the secondary processor based VM-execution controls are used. */
    13891358#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL         RT_BIT(31)
    13901359/** @} */
    … …  
    14381407/** Use TSC scaling. */
    14391408#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING                    RT_BIT(25)
    1440 
    14411409/** @} */
    14421410
    … …  
    14451413 * @{
    14461414 */
    1447 /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     1415/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
     1416 *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    14481417#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG                          RT_BIT(2)
    14491418/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
    … …  
    14651434 * @{
    14661435 */
    1467 /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     1436/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
     1437 *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    14681438#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG                           RT_BIT(2)
    14691439/** Return to long mode after a VM-exit. */
    … …  
    14941464
    14951465
    1496 /** @name VMCS field encoding - 32 Bits read-only fields
     1466/** @name VMCS field encoding: 32-bits read-only fields.
    14971467 * @{
    14981468 */
    … …  
    15351505#define VMX_EXIT_INTERRUPTION_INFO_VALID                        RT_BIT(31)
    15361506#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a)                  RT_BOOL((a) & RT_BIT(31))
    1537 /** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
     1507/** Construct an irq event injection value from the exit interruption info value
     1508 *  (same except that bit 12 is reserved). */
    15381509#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a)      ((a) & ~RT_BIT(12))
    15391510/** @} */
    … …  
    15771548
    15781549
    1579 /** @name VMCS field encoding - 32 Bits guest state fields
     1550/** @name VMCS field encoding: 32-bit guest-state fields.
    15801551 * @{
    15811552 */
    … …  
    16291600
    16301601
    1631 /** @name VMCS field encoding - 32 Bits host state fields
     1602/** @name VMCS field encoding: 32-bit host-state fields.
    16321603 * @{
    16331604 */
    … …  
    16661637 */
    16671638/** 0-2:  Debug register number */
    1668 #define VMX_EXIT_QUAL_DRX_REGISTER(a)                  ((a) & 7)
     1639#define VMX_EXIT_QUAL_DRX_REGISTER(a)                           ((a) & 7)
    16691640/** 3:    Reserved; cleared to 0. */
    1670 #define VMX_EXIT_QUAL_DRX_RES1(a)                      (((a) >> 3) & 1)
     1641#define VMX_EXIT_QUAL_DRX_RES1(a)                               (((a) >> 3) & 1)
    16711642/** 4:    Direction of move (0 = write, 1 = read) */
    1672 #define VMX_EXIT_QUAL_DRX_DIRECTION(a)                 (((a) >> 4) & 1)
     1643#define VMX_EXIT_QUAL_DRX_DIRECTION(a)                          (((a) >> 4) & 1)
    16731644/** 5-7:  Reserved; cleared to 0. */
    1674 #define VMX_EXIT_QUAL_DRX_RES2(a)                      (((a) >> 5) & 7)
     1645#define VMX_EXIT_QUAL_DRX_RES2(a)                               (((a) >> 5) & 7)
    16751646/** 8-11: General purpose register number. */
    1676 #define VMX_EXIT_QUAL_DRX_GENREG(a)                    (((a) >> 8) & 0xF)
     1647#define VMX_EXIT_QUAL_DRX_GENREG(a)                             (((a) >> 8) & 0xF)
    16771648/** Rest: reserved. */
    16781649/** @} */
    … …  
    17971768 * @{
    17981769 */
    1799 /** 0-11:   If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
     1770/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
     1771 *  access within the APIC page. */
    18001772#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a)            ((a) & 0xfff)
    1801 /** 12-15:  Access type. */
     1773/** 12-15: Access type. */
    18021774#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a)              (((a) & 0xf000) >> 12)
    18031775/* Rest reserved. */
    … …  
    19331905
    19341906
    1935 /** @name VMCS field encoding - Natural width guest state fields
     1907/** @name VMCS field encoding: Natural width guest-state fields.
    19361908 * @{
    19371909 */
    … …  
    19771949/** @} */
    19781950
    1979 /** @name VMCS field encoding - Natural width host state fields
     1951
     1952/** @name VMCS field encoding: Natural width host-state fields.
    19801953 * @{
    19811954 */
    … …  
    22222195#endif
    22232196
     2197
    22242198/**
    22252199 * Executes VMPTRST.
    … …  
    22302204 */
    22312205DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
     2206
    22322207
    22332208/**
    … …  
    23482323DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
    23492324
     2325
    23502326/**
    23512327 * Invalidate a page using INVVPID.
    … …  
    23562332 */
    23572333DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
     2334
    23582335
    23592336/**
    … …  
    24842461#endif
    24852462
     2463
    24862464/**
    24872465 * Gets the last instruction error value from the current VMCS.
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette