VirtualBox

Ignore:
Timestamp:
Jul 4, 2018 2:27:12 PM (6 years ago)
Author:
vboxsync
Message:

EM,HM,IEM: Replaced EMInterpretWrmsr with IEMExecDecodedWrmsr.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r72820 r72877  
    67276727{
    67286728    PCPUMCTX pCtx  = &pVCpu->cpum.GstCtx;
     6729    uint32_t const idMsr = pCtx->ecx;
     6730    /** @todo Optimize this: We don't need to get much of the MSR state here
     6731     * since we're only updating.  CPUMAllMsrs.cpp can ask for what it needs and
     6732     * clear the applicable extern flags. */
    67296733    HMSVM_CPUMCTX_IMPORT_STATE(pVCpu,   CPUMCTX_EXTRN_CR0
    67306734                                      | CPUMCTX_EXTRN_RFLAGS
    67316735                                      | CPUMCTX_EXTRN_SS
    6732                                       | CPUMCTX_EXTRN_ALL_MSRS);
     6736                                      | CPUMCTX_EXTRN_ALL_MSRS
     6737                                      | IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    67336738
    67346739    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
    6735     Log4Func(("idMsr=%#RX32\n", pCtx->ecx));
     6740    Log4Func(("idMsr=%#RX32\n", idMsr));
    67366741
    67376742    /*
     
    67406745     */
    67416746    if (   pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
    6742         && pCtx->ecx == MSR_K8_LSTAR)
     6747        && idMsr == MSR_K8_LSTAR)
    67436748    {
    67446749        if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
     
    67596764     * Handle regular MSR writes.
    67606765     */
    6761     int rc;
     6766    VBOXSTRICTRC rcStrict;
    67626767    bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
    67636768    if (fSupportsNextRipSave)
    67646769    {
    6765         rc = EMInterpretWrmsr(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
    6766         if (RT_LIKELY(rc == VINF_SUCCESS))
    6767         {
    6768             pCtx->rip = pVmcb->ctrl.u64NextRIP;
    6769             HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
    6770         }
     6770        rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmcb->ctrl.u64NextRIP - pCtx->rip);
     6771        if (RT_LIKELY(rcStrict == VINF_SUCCESS))
     6772            HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
    67716773        else
    6772             AssertMsg(   rc == VERR_EM_INTERPRETER
    6773                       || rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
     6774            AssertMsg(   rcStrict == VINF_IEM_RAISED_XCPT
     6775                      || rcStrict == VINF_CPUM_R3_MSR_WRITE,
     6776                      ("Unexpected IEMExecDecodedWrmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
    67746777    }
    67756778    else
    67766779    {
    6777         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
    6778         rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
    6779         if (RT_LIKELY(rc == VINF_SUCCESS))
    6780             HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);     /* RIP updated by EMInterpretInstruction(). */
     6780        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
     6781        rcStrict = IEMExecOne(pVCpu);
     6782        if (RT_LIKELY(rcStrict == VINF_SUCCESS))
     6783            HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);     /* RIP updated by EMInterpretInstruction(). */
    67816784        else
    6782             AssertMsg(   rc == VERR_EM_INTERPRETER
    6783                       || rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
    6784     }
    6785 
    6786     if (rc == VINF_SUCCESS)
     6785            AssertMsg(   rcStrict == VINF_IEM_RAISED_XCPT
     6786                      || rcStrict == VINF_CPUM_R3_MSR_WRITE, ("Unexpected IEMExecOne status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
     6787    }
     6788
     6789    if (rcStrict == VINF_SUCCESS)
    67876790    {
    67886791        /* If this is an X2APIC WRMSR access, update the APIC TPR state. */
    6789         if (   pCtx->ecx >= MSR_IA32_X2APIC_START
    6790             && pCtx->ecx <= MSR_IA32_X2APIC_END)
     6792        if (   idMsr >= MSR_IA32_X2APIC_START
     6793            && idMsr <= MSR_IA32_X2APIC_END)
    67916794        {
    67926795            /*
     
    67996802        else
    68006803        {
    6801             switch (pCtx->ecx)
     6804            switch (idMsr)
    68026805            {
    68036806                case MSR_IA32_TSC:          pSvmTransient->fUpdateTscOffsetting = true;                                     break;
     
    68136816
    68146817    /* RIP has been updated by above after EMInterpretWrmsr() or by EMInterpretInstruction(). */
    6815     return rc;
     6818    return VBOXSTRICTRC_TODO(rcStrict);
    68166819}
    68176820
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