Changeset 72877 in vbox for trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
- Timestamp:
- Jul 4, 2018 2:27:12 PM (6 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r72820 r72877 6727 6727 { 6728 6728 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 6729 uint32_t const idMsr = pCtx->ecx; 6730 /** @todo Optimize this: We don't need to get much of the MSR state here 6731 * since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and 6732 * clear the applicable extern flags. */ 6729 6733 HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0 6730 6734 | CPUMCTX_EXTRN_RFLAGS 6731 6735 | CPUMCTX_EXTRN_SS 6732 | CPUMCTX_EXTRN_ALL_MSRS); 6736 | CPUMCTX_EXTRN_ALL_MSRS 6737 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK); 6733 6738 6734 6739 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr); 6735 Log4Func(("idMsr=%#RX32\n", pCtx->ecx));6740 Log4Func(("idMsr=%#RX32\n", idMsr)); 6736 6741 6737 6742 /* … … 6740 6745 */ 6741 6746 if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive 6742 && pCtx->ecx== MSR_K8_LSTAR)6747 && idMsr == MSR_K8_LSTAR) 6743 6748 { 6744 6749 if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr) … … 6759 6764 * Handle regular MSR writes. 6760 6765 */ 6761 int rc;6766 VBOXSTRICTRC rcStrict; 6762 6767 bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx); 6763 6768 if (fSupportsNextRipSave) 6764 6769 { 6765 rc = EMInterpretWrmsr(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx)); 6766 if (RT_LIKELY(rc == VINF_SUCCESS)) 6767 { 6768 pCtx->rip = pVmcb->ctrl.u64NextRIP; 6769 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); 6770 } 6770 rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmcb->ctrl.u64NextRIP - pCtx->rip); 6771 if (RT_LIKELY(rcStrict == VINF_SUCCESS)) 6772 HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict); 6771 6773 else 6772 AssertMsg( rc == VERR_EM_INTERPRETER 6773 || rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc)); 6774 AssertMsg( rcStrict == VINF_IEM_RAISED_XCPT 6775 || rcStrict == VINF_CPUM_R3_MSR_WRITE, 6776 ("Unexpected IEMExecDecodedWrmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 6774 6777 } 6775 6778 else 6776 6779 { 6777 HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);6778 rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));6779 if (RT_LIKELY(rc == VINF_SUCCESS))6780 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc ); /* RIP updated by EMInterpretInstruction(). */6780 HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK); 6781 rcStrict = IEMExecOne(pVCpu); 6782 if (RT_LIKELY(rcStrict == VINF_SUCCESS)) 6783 HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict); /* RIP updated by EMInterpretInstruction(). */ 6781 6784 else 6782 AssertMsg( rc == VERR_EM_INTERPRETER6783 || rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));6784 } 6785 6786 if (rc == VINF_SUCCESS)6785 AssertMsg( rcStrict == VINF_IEM_RAISED_XCPT 6786 || rcStrict == VINF_CPUM_R3_MSR_WRITE, ("Unexpected IEMExecOne status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 6787 } 6788 6789 if (rcStrict == VINF_SUCCESS) 6787 6790 { 6788 6791 /* If this is an X2APIC WRMSR access, update the APIC TPR state. */ 6789 if ( pCtx->ecx>= MSR_IA32_X2APIC_START6790 && pCtx->ecx<= MSR_IA32_X2APIC_END)6792 if ( idMsr >= MSR_IA32_X2APIC_START 6793 && idMsr <= MSR_IA32_X2APIC_END) 6791 6794 { 6792 6795 /* … … 6799 6802 else 6800 6803 { 6801 switch ( pCtx->ecx)6804 switch (idMsr) 6802 6805 { 6803 6806 case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break; … … 6813 6816 6814 6817 /* RIP has been updated by above after EMInterpretWrmsr() or by EMInterpretInstruction(). */ 6815 return rc;6818 return VBOXSTRICTRC_TODO(rcStrict); 6816 6819 } 6817 6820
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