Changeset 72877 in vbox for trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

Timestamp:

Jul 4, 2018 2:27:12 PM (6 years ago)

Author:

vboxsync

Message:

EM,HM,IEM: Replaced EMInterpretWrmsr with IEMExecDecodedWrmsr.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -11895 +11895 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
-    int rc = VINF_SUCCESS;
-
-    /* EMInterpretWrmsr() requires CR0, EFLAGS and SS segment register. FS, GS (base) can be accessed by MSR writes. */
-    rc  = hmR0VmxImportGuestState(pVCpu,   CPUMCTX_EXTRN_CR0
-                                         | CPUMCTX_EXTRN_RFLAGS
-                                         | CPUMCTX_EXTRN_SS
-                                         | CPUMCTX_EXTRN_FS
-                                         | CPUMCTX_EXTRN_GS);
-    if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
-        rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
+
+    /** @todo Optimize this: We currently drag in in the whole MSR state
+     * (CPUMCTX_EXTRN_ALL_MSRS) here.  We should optimize this to only get
+     * MSRs required.  That would require changes to IEM and possibly CPUM too.
+     * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
+    uint32_t const idMsr = pMixedCtx->ecx; /* Save it. */
+    int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
+    rc    |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
     AssertRCReturn(rc, rc);
-    Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", pMixedCtx->ecx, pMixedCtx->edx, pMixedCtx->eax));
-
-    rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
-    AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0VmxExitWrmsr: failed, invalid error code %Rrc\n", rc));
+
+    Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", idMsr, pMixedCtx->edx, pMixedCtx->eax));
+
+    VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbInstr);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
 
-    if (RT_SUCCESS(rc))
-    {
-        rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
-
+    if (rcStrict == VINF_SUCCESS)
+    {
         /* If this is an X2APIC WRMSR access, update the APIC state as well. */
-        if (    pMixedCtx->ecx == MSR_IA32_APICBASE
-            || (   pMixedCtx->ecx >= MSR_IA32_X2APIC_START
-                && pMixedCtx->ecx <= MSR_IA32_X2APIC_END))
+        if (    idMsr == MSR_IA32_APICBASE
+            || (   idMsr >= MSR_IA32_X2APIC_START
+                && idMsr <= MSR_IA32_X2APIC_END))
         {
             /*
@@ -11929 +11924 @@
             ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
         }
-        else if (pMixedCtx->ecx == MSR_IA32_TSC)        /* Windows 7 does this during bootup. See @bugref{6398}. */
+        else if (idMsr == MSR_IA32_TSC)        /* Windows 7 does this during bootup. See @bugref{6398}. */
             pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
-        else if (pMixedCtx->ecx == MSR_K6_EFER)
+        else if (idMsr == MSR_K6_EFER)
         {
             /*
@@ -11946 +11941 @@
         if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
         {
-            switch (pMixedCtx->ecx)
+            switch (idMsr)
             {
                 case MSR_IA32_SYSENTER_CS:  ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR);   break;
@@ -11956 +11951 @@
                 default:
                 {
-                    if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
+                    if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
                         ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
-                    else if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
+                    else if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
                         ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_LAZY_MSRS);
                     break;
@@ -11968 +11963 @@
         {
             /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
-            switch (pMixedCtx->ecx)
+            switch (idMsr)
             {
                 case MSR_IA32_SYSENTER_CS:
@@ -11976 +11971 @@
                 case MSR_K8_GS_BASE:
                 {
-                    AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", pMixedCtx->ecx));
+                    AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", idMsr));
                     HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
                 }
@@ -11983 +11978 @@
                 default:
                 {
-                    if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
+                    if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
                     {
                         /* EFER writes are always intercepted, see hmR0VmxExportGuestMsrs(). */
-                        if (pMixedCtx->ecx != MSR_K6_EFER)
+                        if (idMsr != MSR_K6_EFER)
                         {
                             AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
-                                             pMixedCtx->ecx));
+                                             idMsr));
                             HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
                         }
                     }
 
-                    if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
+                    if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
                     {
                         VMXMSREXITREAD  enmRead;
                         VMXMSREXITWRITE enmWrite;
-                        int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
+                        int rc2 = hmR0VmxGetMsrPermission(pVCpu, idMsr, &enmRead, &enmWrite);
                         AssertRCReturn(rc2, rc2);
                         if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
                         {
-                            AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
+                            AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", idMsr));
                             HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
                         }
@@ -12012 +12007 @@
 #endif  /* VBOX_STRICT */
     }
-    return rc;
+    else
+        AssertMsg(   rcStrict == VINF_CPUM_R3_MSR_WRITE
+                  || rcStrict == VINF_IEM_RAISED_XCPT,
+                  ("Unexpected IEMExecDecodedWrmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
+
+    return rcStrict;
 }