Changeset 73294 in vbox

Timestamp:

Jul 21, 2018 3:26:11 PM (7 years ago)

Author:

vboxsync

Message:

VMM/HM: Doxygen, nits.

File:

• trunk/src/VBox/VMM/VMMR3/HM.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/VMMR3/HM.cpp

@@ -1557 +1557 @@
  * Reports MSR_IA32_VMX_MISC MSR to the log.
  *
+ * @param   pVM      Pointer to the VM.
  * @param   fMisc    The VMX misc. MSR value.
  */
@@ -1677 +1678 @@
 
     /*
-     * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
+     * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
      */
     AssertLogRelReturn(   !pVM->hm.s.fNestedPaging
@@ -2907 +2908 @@
 
 /**
- * Checks if we can currently use hardware accelerated raw mode.
+ * Checks if we can currently use hardware accelerated mode.
  *
  * @returns true if we can currently use hardware acceleration, otherwise false.
  * @param   pVM         The cross context VM structure.
- * @param   pCtx        Partial VM execution context.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
@@ -3061 +3062 @@
     if (pVM->hm.s.vmx.fEnabled)
     {
-        uint32_t uCR0Mask;
+        uint32_t uCr0Mask;
 
         /* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
-        uCR0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
+        uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
 
         /* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
-        uCR0Mask &= ~X86_CR0_NE;
+        uCr0Mask &= ~X86_CR0_NE;
 
         if (fSupportsRealMode)
         {
             /* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
-            uCR0Mask &= ~(X86_CR0_PG|X86_CR0_PE);
+            uCr0Mask &= ~(X86_CR0_PG|X86_CR0_PE);
         }
         else
         {
             /* We support protected mode without paging using identity mapping. */
-            uCR0Mask &= ~X86_CR0_PG;
+            uCr0Mask &= ~X86_CR0_PG;
         }
-        if ((pCtx->cr0 & uCR0Mask) != uCR0Mask)
+        if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
             return false;
 
         /* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
-        uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
-        if ((pCtx->cr0 & uCR0Mask) != 0)
+        uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
+        if ((pCtx->cr0 & uCr0Mask) != 0)
             return false;
 
         /* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
-        uCR0Mask  = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
-        uCR0Mask &= ~X86_CR4_VMXE;
-        if ((pCtx->cr4 & uCR0Mask) != uCR0Mask)
+        uCr0Mask  = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
+        uCr0Mask &= ~X86_CR4_VMXE;
+        if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
             return false;
 
         /* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
-        uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
-        if ((pCtx->cr4 & uCR0Mask) != 0)
+        uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
+        if ((pCtx->cr4 & uCr0Mask) != 0)
             return false;
 
@@ -3349 +3350 @@
 VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
 {
-    return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
+    return HMIsEnabled(pVCpu->pVMR3)
+        && pVCpu->hm.s.Event.fPending;
 }