Changeset 75301 in vbox for trunk/include/VBox/vmm

Timestamp:

Nov 7, 2018 10:28:57 AM (6 years ago)

Author:

vboxsync

Message:

VMM: Nested VMX: bugref:9180 VM-exit bits; APIC-access and APIC-write infrastructure. Handling of instruction/event boundary
pending APIC bits todo.

Location:

trunk/include/VBox/vmm

Files:

• cpumctx.h (modified) (2 diffs)
• hm_vmx.h (modified) (5 diffs)
• vm.h (modified) (3 diffs)

trunk/include/VBox/vmm/cpumctx.h

@@ -661 +661 @@
                 /** 0x398 - Guest TSC timestamp of VM-entry (used for VMX-preemption timer). */
                 uint64_t                uVmentryTick;
-                /** 0x3a0 - Padding. */
-                uint8_t             abPadding[0x3f0 - 0x3a0];
+                /** 0x3a0 - Virtual-APIC write offset (until trap-like VM-exit). */
+                uint16_t                offVirtApicWrite;
+                /** 0x3a2 - Padding. */
+                uint8_t             abPadding[0x3f0 - 0x3a2];
             } vmx;
         } CPUM_UNION_NM(s);
@@ -773 +775 @@
 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uPrevPauseTick,         0x390);
 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uVmentryTick,           0x398);
+AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.offVirtApicWrite,       0x3a0);
 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR0,           8);
 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR0,     8);

trunk/include/VBox/vmm/hm_vmx.h

@@ -2079 +2079 @@
  * @{
  */
-/** Virtualize APIC access. */
+/** Virtualize APIC accesses. */
 #define VMX_PROC_CTLS2_VIRT_APIC_ACCESS                         RT_BIT(0)
 /** EPT supported/enabled. */
@@ -2852 +2852 @@
 #define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a)                       (((a) & 0xf000) >> 12)
 /* Rest reserved. */
+
+/** Bit fields for Exit qualification for APIC-access VM-exits. */
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT               0
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK                UINT64_C(0x0000000000000fff)
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT                 12
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK                  UINT64_C(0x000000000000f000)
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT           16
+#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK            UINT64_C(0xffffffffffff0000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
+                            (OFFSET, TYPE, RSVD_16_63));
 /** @} */
 
@@ -2858 +2868 @@
  * @{
  */
-/** Linear read access. */
+/** Linear access for a data read during instruction execution. */
 #define VMX_APIC_ACCESS_TYPE_LINEAR_READ                        0
-/** Linear write access. */
+/** Linear access for a data write during instruction execution. */
 #define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE                       1
-/** Linear instruction fetch access. */
+/** Linear access for an instruction fetch. */
 #define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH                 2
 /** Linear read/write access during event delivery. */
@@ -2870 +2880 @@
 /** Physical access for an instruction fetch or during instruction execution. */
 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR                     15
+
+/**
+ * APIC-access type.
+ */
+typedef enum
+{
+    VMXAPICACCESS_LINEAR_READ             = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
+    VMXAPICACCESS_LINEAR_WRITE            = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
+    VMXAPICACCESS_LINEAR_INSTR_FETCH      = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
+    VMXAPICACCESS_LINEAR_EVENT_DELIVERY   = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
+    VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
+    VMXAPICACCESS_PHYSICAL_INSTR          = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
+} VMXAPICACCESS;
+AssertCompileSize(VMXAPICACCESS, 4);
 /** @} */
 
@@ -3803 +3827 @@
     /* VMLAUNCH/VMRESUME. */
     kVmxVDiag_Vmentry_AddrApicAccess,
+    kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
     kVmxVDiag_Vmentry_AddrEntryMsrLoad,
     kVmxVDiag_Vmentry_AddrExitMsrLoad,

trunk/include/VBox/vmm/vm.h

@@ -366 +366 @@
  *
  * Available VMCPU bits:
- *      14, 15, 33 to 63
+ *      11, 14, 15, 35 to 63
  *
  * @todo If we run low on VMCPU, we may consider merging the SELM bits
@@ -471 +471 @@
 /** The bit number for VMCPU_FF_DBGF. */
 #define VMCPU_FF_DBGF_BIT                   10
-/** Pending MTF (Monitor Trap Flag) event - Intel only.  */
-#define VMCPU_FF_MTF                        RT_BIT_64(VMCPU_FF_MTF_BIT)
-/** The bit number for VMCPU_FF_MTF. */
-#define VMCPU_FF_MTF_BIT                    11
 /** This action forces the VM to service any pending updates to CR3 (used only
  *  by HM). */
@@ -550 +546 @@
 /** VMX-preemption timer in effect. */
 #define VMCPU_FF_VMX_PREEMPT_TIMER          RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
+/** Bit number for VMCPU_FF_VMX_PREEMPT_TIMER. */
 #define VMCPU_FF_VMX_PREEMPT_TIMER_BIT      32
+/** Pending MTF (Monitor Trap Flag) event.  */
+#define VMCPU_FF_VMX_MTF                    RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
+/** The bit number for VMCPU_FF_VMX_MTF. */
+#define VMCPU_FF_VMX_MTF_BIT                33
+/** Virtual-APIC operation pending (VTPR, VEOI or APIC-write).  */
+#define VMCPU_FF_VMX_UPDATE_VAPIC           RT_BIT_64(VMCPU_FF_VMX_UPDATE_VAPIC_BIT)
+/** The bit number for VMCPU_FF_VMX_UPDATE_VTPR. */
+#define VMCPU_FF_VMX_UPDATE_VAPIC_BIT       34