VirtualBox

Ignore:
Timestamp:
Nov 20, 2018 11:20:25 AM (6 years ago)
Author:
vboxsync
Message:

VMM: Nested VMX: bugref:9180 Move the VMX APIC-access guest-physical page registration into IEM and got rid of the CPUM all context code that does not quite fit because we still have to declare the prototypes in the HM headers anyway, so just keep it in HM all context code for now.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

    r75565 r75611  
    27292729    PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
    27302730    bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
    2731     bool const fVirtApicAccess = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
    27322731
    27332732    /* We cannot return from a long-mode guest to a host that is not in long mode. */
     
    27572756
    27582757    /* De-register the handler for the APIC-access page. */
    2759     if (fVirtApicAccess)
    2760     {
     2758    if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     2759    {
     2760        PVM pVM = pVCpu->CTX_SUFF(pVM);
    27612761        RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
    2762         int rc = CPUMVmxApicAccessPageDeregister(pVCpu, GCPhysApicAccess);
    2763         if (RT_FAILURE(rc))
    2764             return rc;
     2762        if (PGMHandlerPhysicalIsRegistered(pVM, GCPhysApicAccess))
     2763        {
     2764            /** @todo NSTVMX: This is broken! We cannot simply deregister the handler for the
     2765             *        physical address as other VCPUs executing other nested-VCPUs might have
     2766             *        it registered! */
     2767            int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysApicAccess);
     2768            if (RT_FAILURE(rc))
     2769                return rc;
     2770        }
    27652771    }
    27662772
     
    30443050        Assert(pbIoBitmapA);
    30453051        Assert(pbIoBitmapB);
    3046         return CPUMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
     3052        return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
    30473053    }
    30483054
     
    63346340
    63356341        /* Register the handler for the APIC-access page. */
    6336         int rc = CPUMVmxApicAccessPageRegister(pVCpu, GCPhysApicAccess);
     6342        int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
     6343                                            pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
     6344                                            NIL_RTR0PTR /* pvUserR0 */,  NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
    63376345        if (RT_FAILURE(rc))
    63386346            IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
     
    70577065        {
    70587066            VMXMSREXITREAD enmRead;
    7059             int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
     7067            int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
    70607068                                             NULL /* penmWrite */);
    70617069            AssertRC(rc);
     
    70667074        {
    70677075            VMXMSREXITWRITE enmWrite;
    7068             int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
     7076            int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
    70697077                                             &enmWrite);
    70707078            AssertRC(rc);
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette