Changeset 75994 in vbox for trunk/include/iprt/x86.mac
- Timestamp:
- Dec 5, 2018 9:38:19 PM (6 years ago)
- File:
-
- 1 edited
-
trunk/include/iprt/x86.mac (modified) (17 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/iprt/x86.mac
r70606 r75994 177 177 %define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29) 178 178 %define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0) 179 %define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2) 180 %define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3) 181 %define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4) 182 %define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000 183 %define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2) 184 %define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30) 179 185 %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26) 180 186 %define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27) … … 239 245 %define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11) 240 246 %define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12) 247 %define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0) 248 %define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1) 249 %define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2) 250 %define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12) 241 251 %define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0) 242 252 %define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1) … … 274 284 %define X86_CR0_PG RT_BIT_32(31) 275 285 %define X86_CR0_PAGING RT_BIT_32(31) 286 %define X86_CR0_BIT_PG 31 276 287 %define X86_CR3_PWT RT_BIT_32(3) 277 288 %define X86_CR3_PCD RT_BIT_32(4) … … 292 303 %define X86_CR4_VMXE RT_BIT_32(13) 293 304 %define X86_CR4_SMXE RT_BIT_32(14) 305 %define X86_CR4_FSGSBASE RT_BIT_32(16) 294 306 %define X86_CR4_PCIDE RT_BIT_32(17) 295 307 %define X86_CR4_OSXSAVE RT_BIT_32(18) … … 305 317 %define X86_DR6_BS RT_BIT_32(14) 306 318 %define X86_DR6_BT RT_BIT_32(15) 307 %define X86_DR6_INIT_VAL 0xFFFF0FF0 319 %define X86_DR6_RTM RT_BIT_32(16) 320 %define X86_DR6_INIT_VAL 0xffff0ff0 308 321 %define X86_DR6_RA1_MASK 0xffff0ff0 322 %define X86_DR6_RA1_MASK_RTM 0xfffe0ff0 309 323 %define X86_DR6_RAZ_MASK RT_BIT_64(12) 310 324 %define X86_DR6_MBZ_MASK 0xffffffff00000000 … … 322 336 %define X86_DR7_LE_ALL 0x0000000000000055 323 337 %define X86_DR7_GE_ALL 0x00000000000000aa 338 %define X86_DR7_RTM RT_BIT_32(11) 324 339 %define X86_DR7_ICE_IR RT_BIT_32(12) 325 340 %define X86_DR7_GD RT_BIT_32(13) … … 378 393 %endif 379 394 %define MSR_CORE_THREAD_COUNT 0x35 380 %define MSR_IA32_FEATURE_CONTROL 0x3A 381 %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0) 382 %define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1) 383 %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2) 395 %define MSR_IA32_FEATURE_CONTROL 0x3A 396 %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0) 397 %define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1) 398 %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2) 399 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8) 400 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9) 401 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10) 402 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11) 403 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12) 404 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13) 405 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14) 406 %define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15) 407 %define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17) 408 %define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18) 409 %define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20) 384 410 %define MSR_IA32_TSC_ADJUST 0x3B 385 411 %define MSR_IA32_SPEC_CTRL 0x48 … … 391 417 %define MSR_IA32_BIOS_SIGN_ID 0x8B 392 418 %define MSR_IA32_SMM_MONITOR_CTL 0x9B 419 %define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0) 420 %define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2) 421 %define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff) 422 %define MSR_IA32_SMBASE 0x9E 393 423 %define MSR_IA32_PMC0 0xC1 394 424 %define MSR_IA32_PMC1 0xC2 … … 401 431 %define MSR_IA32_APERF 0xE8 402 432 %define MSR_IA32_MTRR_CAP 0xFE 403 %define MSR_IA32_ARCH_CAP 433 %define MSR_IA32_ARCH_CAPABILITIES 0x10a 404 434 %define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0) 405 435 %define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1) … … 414 444 %define MSR_IA32_MCG_CTRL 0x17B 415 445 %define MSR_IA32_CR_PAT 0x277 446 %define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406 416 447 %define MSR_IA32_PERFEVTSEL0 0x186 417 448 %define MSR_IA32_PERFEVTSEL1 0x187 … … 447 478 %define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14) 448 479 %define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15) 480 %define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \ 481 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \ 482 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \ 483 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \ 484 | MSR_IA32_DEBUGCTL_RTM) 449 485 %define MSR_P4_LASTBRANCH_TOS 0x000001da 450 486 %define MSR_P4_LASTBRANCH_0 0x000001db … … 490 526 %define MSR_IA32_MC0_CTL 0x400 491 527 %define MSR_IA32_MC0_STATUS 0x401 492 %define MSR_IA32_VMX_BASIC _INFO0x480528 %define MSR_IA32_VMX_BASIC 0x480 493 529 %define MSR_IA32_VMX_PINBASED_CTLS 0x481 494 530 %define MSR_IA32_VMX_PROCBASED_CTLS 0x482 … … 501 537 %define MSR_IA32_VMX_CR4_FIXED1 0x489 502 538 %define MSR_IA32_VMX_VMCS_ENUM 0x48A 503 %define MSR_IA32_VMX_VMFUNC 0x491504 539 %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B 505 540 %define MSR_IA32_VMX_EPT_VPID_CAP 0x48C … … 508 543 %define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F 509 544 %define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 545 %define MSR_IA32_VMX_VMFUNC 0x491 546 %define MSR_IA32_RTIT_CTL 0x570 510 547 %define MSR_IA32_DS_AREA 0x600 511 548 %define MSR_RAPL_POWER_UNIT 0x606 … … 561 598 %define MSR_K6_EFER_SCE RT_BIT_32(0) 562 599 %define MSR_K6_EFER_LME RT_BIT_32(8) 600 %define MSR_K6_EFER_BIT_LME 8 563 601 %define MSR_K6_EFER_LMA RT_BIT_32(10) 602 %define MSR_K6_EFER_BIT_LMA 10 564 603 %define MSR_K6_EFER_NXE RT_BIT_32(11) 565 604 %define MSR_K6_EFER_BIT_NXE 11 … … 636 675 %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000 637 676 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000 677 %define X86_PAGE_1G_SIZE _1G 678 %define X86_PAGE_1G_SHIFT 30 679 %define X86_PAGE_1G_OFFSET_MASK 0x3fffffff 680 %define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000 638 681 %define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000)) 639 682 %define X86_PTE_BIT_P 0 … … 784 827 %define X86_PML4_SHIFT 39 785 828 %define X86_PML4_MASK 0x1ff 829 %define X86_INVPCID_TYPE_INDV_ADDR 0 830 %define X86_INVPCID_TYPE_SINGLE_CONTEXT 1 831 %define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2 832 %define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3 833 %define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 834 %ifndef VBOX_FOR_DTRACE_LIB 835 %endif 786 836 %ifndef VBOX_FOR_DTRACE_LIB 787 837 %endif
Note:
See TracChangeset
for help on using the changeset viewer.
