Changeset 7666 in vbox for trunk/include

Timestamp:

Mar 31, 2008 3:02:43 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

29178

Message:

Put back the original PAE defines. AMD differs from Intel wrt valid pae & long mode physical address bits.

File:

• trunk/include/VBox/x86.h (modified) (2 diffs)

trunk/include/VBox/x86.h

@@ -899 +899 @@
 #define X86_PTE_PG_MASK                     ( 0xfffff000 )
 
-/** Bits 12-51 - - PAE - Physical Page number of the next level. */
+/** Bits 12-36 - - PAE - Physical Page number of the next level. */
 #if 1 /* we're using this internally and have to mask of the top 16-bit. */
 #define X86_PTE_PAE_PG_MASK                 ( 0x0000fffffffff000ULL )
@@ -1210 +1210 @@
 #define X86_PDE4M_PG_HIGH_SHIFT             19
 
-/** Bits 21-36 - - PAE - Physical Page number. */
-#define X86_PDE2M_PAE_PG_MASK               ( 0x0000000fffe00000ULL )
-/** Bits 63 - NX - PAE - No execution flag. */
-#define X86_PDE2M_PAE_NX                    RT_BIT_64(63)
-
-/** Bits 21-39 - - AMD64 - Physical Page number. (bits 40-51 are reserved) */
-#define X86_PDE2M_AMD64_PG_MASK             ( 0x000000ffffe00000ULL )
-/** Bits 63 - NX - AMD64 - No execution flag. */
-#define X86_PDE2M_AMD64_NX                  X86_PDE2M_PAE_NX
+/** Bits 21-51 - - PAE & AMD64 - Physical Page number. (bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more) */
+#define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000ULL )
+/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
+#define X86_PDE2M_PAE_NX                    X86_PDE2M_PAE_NX
 
 /**