VirtualBox

Changeset 76678 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Jan 7, 2019 1:48:16 PM (6 years ago)
Author:
vboxsync
Message:

Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0:104445,104938,104943,104950,104952-104953,104987-104988,104990,106453
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
        10 /branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,125768,125779-125780,125812
         10/branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
        1111/branches/andy/draganddrop:90781-91268
        1212/branches/andy/guestctrl20:78916,78930

  • trunk/src/VBox

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0/src/VBox:104938,104943,104950,104987-104988,104990,106453
        99/branches/VBox-5.1/src/VBox:112367,116543,116550,116568,116573
        10 /branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,125768,125779-125780,125812
         10/branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124263,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
        1111/branches/andy/draganddrop/src/VBox:90781-91268
        1212/branches/andy/guestctrl20/src/VBox:78916,78930

  • trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

    r76553 r76678  
    214214        uint32_t u32CpuVersion;
    215215        uint32_t u32Dummy;
    216         uint32_t fFeatures;
     216        uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
    217217        ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
    218218        uint32_t const u32Family   = u32CpuVersion >> 8;
    … …  
    264264                }
    265265            }
     266        }
     267
     268        /*
     269         * Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host feature structure.
     270         */
     271        pVM->cpum.s.HostFeatures.fArchRdclNo             = 0;
     272        pVM->cpum.s.HostFeatures.fArchIbrsAll            = 0;
     273        pVM->cpum.s.HostFeatures.fArchRsbOverride        = 0;
     274        pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
     275        uint32_t const cStdRange = ASMCpuId_EAX(0);
     276        if (   ASMIsValidStdRange(cStdRange)
     277            && cStdRange >= 7)
     278        {
     279            uint32_t fEdxFeatures = ASMCpuId_EDX(7);
     280            if (   (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
     281                && (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
     282            {
     283                uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
     284                pVM->cpum.s.HostFeatures.fArchRdclNo             = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
     285                pVM->cpum.s.HostFeatures.fArchIbrsAll            = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
     286                pVM->cpum.s.HostFeatures.fArchRsbOverride        = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
     287                pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
     288            }
     289            else
     290                pVM->cpum.s.HostFeatures.fArchCap = 0;
    266291        }
    267292

  • trunk/src/VBox/VMM/VMMR0/HMR0A.asm

    r76553 r76678  
    252252    wrmsr
    253253%%no_indirect_branch_barrier:
     254%endmacro
     255
     256;;
     257; Creates an indirect branch prediction and L1D barrier on CPUs that need and supports that.
     258; @clobbers eax, edx, ecx
     259; @param    1   How to address CPUMCTX.
     260; @param    2   Which IBPB flag to test for (CPUMCTX_WSF_IBPB_ENTRY or CPUMCTX_WSF_IBPB_EXIT)
     261; @param    3   Which FLUSH flag to test for (CPUMCTX_WSF_L1D_ENTRY)
     262%macro INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER 3
     263    ; Only one test+jmp when disabled CPUs.
     264    test    byte [%1 + CPUMCTX.fWorldSwitcher], (%2 | %3)
     265    jz      %%no_barrier_needed
     266
     267    ; The eax:edx value is the same for both.
     268    AssertCompile(MSR_IA32_PRED_CMD_F_IBPB == MSR_IA32_FLUSH_CMD_F_L1D)
     269    mov     eax, MSR_IA32_PRED_CMD_F_IBPB
     270    xor     edx, edx
     271
     272    ; Indirect branch barrier.
     273    test    byte [%1 + CPUMCTX.fWorldSwitcher], %2
     274    jz      %%no_indirect_branch_barrier
     275    mov     ecx, MSR_IA32_PRED_CMD
     276    wrmsr
     277%%no_indirect_branch_barrier:
     278
     279    ; Level 1 data cache flush.
     280    test    byte [%1 + CPUMCTX.fWorldSwitcher], %3
     281    jz      %%no_cache_flush_barrier
     282    mov     ecx, MSR_IA32_FLUSH_CMD
     283    wrmsr
     284%%no_cache_flush_barrier:
     285
     286%%no_barrier_needed:
    254287%endmacro
    255288
    … …  
    14541487    ; Don't mess with ESP anymore!!!
    14551488
    1456     ; Fight spectre.
    1457     INDIRECT_BRANCH_PREDICTION_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY
     1489    ; Fight spectre and similar.
     1490    INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY
    14581491
    14591492    ; Load guest general purpose registers.
    … …  
    17631796    ; Don't mess with ESP anymore!!!
    17641797
    1765     ; Fight spectre.
    1766     INDIRECT_BRANCH_PREDICTION_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY
     1798    ; Fight spectre and similar.
     1799    INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY
    17671800
    17681801    ; Load guest general purpose registers.

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r76637 r76678  
    25292529#endif
    25302530        /*
    2531          * The IA32_PRED_CMD MSR is write-only and has no state associated with it. We never need to intercept
    2532          * access (writes need to be executed without exiting, reds will #GP-fault anyway).
     2531         * The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state
     2532         * associated with then. We never need to intercept access (writes need to
     2533         * be executed without exiting, reads will #GP-fault anyway).
    25332534         */
    25342535        if (pVM->cpum.ro.GuestFeatures.fIbpb)
    25352536            hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD,     VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
     2537        if (pVM->cpum.ro.GuestFeatures.fFlushCmd)
     2538            hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_FLUSH_CMD,    VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
    25362539
    25372540        /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
    … …  
    80578060        pVCpu->hm.s.fLeaveDone = false;
    80588061        Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
     8062
     8063        /*
     8064         * Do the EMT scheduled L1D flush here if needed.
     8065         */
     8066        if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched)
     8067            ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
    80598068    }
    80608069    return rc;
    … …  
    81358144            }
    81368145            pVCpu->hm.s.fLeaveDone = false;
     8146
     8147            /* Do the EMT scheduled L1D flush if needed. */
     8148            if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched)
     8149                ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
    81378150
    81388151            /* Restore longjmp state. */
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