Changeset 76678 in vbox for trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
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trunk
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old new 8 8 /branches/VBox-5.0:104445,104938,104943,104950,104952-104953,104987-104988,104990,106453 9 9 /branches/VBox-5.1:112367,115992,116543,116550,116568,116573 10 /branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,12 5768,125779-125780,12581210 /branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812 11 11 /branches/andy/draganddrop:90781-91268 12 12 /branches/andy/guestctrl20:78916,78930
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old new 8 8 /branches/VBox-5.0/src/VBox:104938,104943,104950,104987-104988,104990,106453 9 9 /branches/VBox-5.1/src/VBox:112367,116543,116550,116568,116573 10 /branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,12 5768,125779-125780,12581210 /branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124263,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812 11 11 /branches/andy/draganddrop/src/VBox:90781-91268 12 12 /branches/andy/guestctrl20/src/VBox:78916,78930
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r76637 r76678 2529 2529 #endif 2530 2530 /* 2531 * The IA32_PRED_CMD MSR is write-only and has no state associated with it. We never need to intercept 2532 * access (writes need to be executed without exiting, reds will #GP-fault anyway). 2531 * The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state 2532 * associated with then. We never need to intercept access (writes need to 2533 * be executed without exiting, reads will #GP-fault anyway). 2533 2534 */ 2534 2535 if (pVM->cpum.ro.GuestFeatures.fIbpb) 2535 2536 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE); 2537 if (pVM->cpum.ro.GuestFeatures.fFlushCmd) 2538 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_FLUSH_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE); 2536 2539 2537 2540 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */ … … 8057 8060 pVCpu->hm.s.fLeaveDone = false; 8058 8061 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId())); 8062 8063 /* 8064 * Do the EMT scheduled L1D flush here if needed. 8065 */ 8066 if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched) 8067 ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D); 8059 8068 } 8060 8069 return rc; … … 8135 8144 } 8136 8145 pVCpu->hm.s.fLeaveDone = false; 8146 8147 /* Do the EMT scheduled L1D flush if needed. */ 8148 if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched) 8149 ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D); 8137 8150 8138 8151 /* Restore longjmp state. */
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