Changeset 78229 in vbox for trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
- Timestamp:
- Apr 20, 2019 5:20:41 AM (6 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r78228 r78229 2741 2741 * 2742 2742 * @returns VBox status code. 2743 * @param pVCpu The cross context virtual CPU structure. 2743 2744 * @param pVmcsInfo The VMCS info. object. 2744 2745 */ 2745 DECLINLINE(int) hmR0VmxSetupVmcsVirtApicAddr(PCVMXVMCSINFO pVmcsInfo) 2746 { 2746 DECLINLINE(int) hmR0VmxSetupVmcsVirtApicAddr(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo) 2747 { 2748 NOREF(pVCpu); 2747 2749 RTHCPHYS const HCPhysVirtApic = pVmcsInfo->HCPhysVirtApic; 2748 2750 Assert(HCPhysVirtApic != NIL_RTHCPHYS); … … 2756 2758 * 2757 2759 * @returns VBox status code. 2760 * @param pVCpu The cross context virtual CPU structure. 2758 2761 * @param pVmcsInfo The VMCS info. object. 2759 2762 */ 2760 DECLINLINE(int) hmR0VmxSetupVmcsMsrBitmapAddr(PCVMXVMCSINFO pVmcsInfo) 2761 { 2763 DECLINLINE(int) hmR0VmxSetupVmcsMsrBitmapAddr(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo) 2764 { 2765 NOREF(pVCpu); 2762 2766 RTHCPHYS const HCPhysMsrBitmap = pVmcsInfo->HCPhysMsrBitmap; 2763 2767 Assert(HCPhysMsrBitmap != NIL_RTHCPHYS); … … 2786 2790 * 2787 2791 * @returns VBox status code. 2788 * @param pVmcsInfo The VMCS info. object. 2789 */ 2790 DECLINLINE(int) hmR0VmxSetupVmcsLinkPtr(PVMXVMCSINFO pVmcsInfo) 2791 { 2792 * @param pVCpu The cross context virtual CPU structure. 2793 * @param pVmcsInfo The VMCS info. object. 2794 */ 2795 DECLINLINE(int) hmR0VmxSetupVmcsLinkPtr(PVMCPU pVCpu, PVMXVMCSINFO pVmcsInfo) 2796 { 2797 NOREF(pVCpu); 2792 2798 uint64_t const u64VmcsLinkPtr = pVmcsInfo->u64VmcsLinkPtr; 2793 2799 Assert(u64VmcsLinkPtr == UINT64_C(0xffffffffffffffff)); /* Bits 63:0 MB1. */ … … 2801 2807 * 2802 2808 * @returns VBox status code. 2803 * @param pVmcsInfo The VMCS info. object. 2804 */ 2805 DECLINLINE(int) hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(PVMXVMCSINFO pVmcsInfo) 2806 { 2809 * @param pVCpu The cross context virtual CPU structure. 2810 * @param pVmcsInfo The VMCS info. object. 2811 */ 2812 DECLINLINE(int) hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(PVMCPU pVCpu, PVMXVMCSINFO pVmcsInfo) 2813 { 2814 NOREF(pVCpu); 2807 2815 RTHCPHYS const HCPhysGuestMsrLoad = pVmcsInfo->HCPhysGuestMsrLoad; 2808 2816 Assert(HCPhysGuestMsrLoad != NIL_RTHCPHYS); … … 3090 3098 Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT)); 3091 3099 Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT)); 3092 int rc = hmR0VmxSetupVmcsVirtApicAddr(pV mcsInfo);3100 int rc = hmR0VmxSetupVmcsVirtApicAddr(pVCpu, pVmcsInfo); 3093 3101 AssertRCReturn(rc, rc); 3094 3102 } … … 3108 3116 { 3109 3117 fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS; 3110 int rc = hmR0VmxSetupVmcsMsrBitmapAddr(pV mcsInfo);3118 int rc = hmR0VmxSetupVmcsMsrBitmapAddr(pVCpu, pVmcsInfo); 3111 3119 AssertRCReturn(rc, rc); 3112 3120 } … … 3161 3169 { 3162 3170 /* Set the auto-load/store MSR area addresses in the VMCS. */ 3163 int rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pV mcsInfo);3171 int rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVCpu, pVmcsInfo); 3164 3172 if (RT_SUCCESS(rc)) 3165 3173 { 3166 3174 /* Set the VMCS link pointer in the VMCS. */ 3167 rc = hmR0VmxSetupVmcsLinkPtr(pV mcsInfo);3175 rc = hmR0VmxSetupVmcsLinkPtr(pVCpu, pVmcsInfo); 3168 3176 if (RT_SUCCESS(rc)) 3169 3177 { … … 3628 3636 return true; 3629 3637 } 3630 # endif 3638 # endif /* VBOX_ENABLE_64_BITS_GUESTS */ 3639 3640 # ifdef VBOX_STRICT 3641 static bool hmR0VmxIsValidWriteField(uint32_t idxField) 3642 { 3643 switch (idxField) 3644 { 3645 case VMX_VMCS_GUEST_RIP: 3646 case VMX_VMCS_GUEST_RSP: 3647 case VMX_VMCS_GUEST_SYSENTER_EIP: 3648 case VMX_VMCS_GUEST_SYSENTER_ESP: 3649 case VMX_VMCS_GUEST_GDTR_BASE: 3650 case VMX_VMCS_GUEST_IDTR_BASE: 3651 case VMX_VMCS_GUEST_CS_BASE: 3652 case VMX_VMCS_GUEST_DS_BASE: 3653 case VMX_VMCS_GUEST_ES_BASE: 3654 case VMX_VMCS_GUEST_FS_BASE: 3655 case VMX_VMCS_GUEST_GS_BASE: 3656 case VMX_VMCS_GUEST_SS_BASE: 3657 case VMX_VMCS_GUEST_LDTR_BASE: 3658 case VMX_VMCS_GUEST_TR_BASE: 3659 case VMX_VMCS_GUEST_CR3: 3660 return true; 3661 } 3662 return false; 3663 } 3664 3665 static bool hmR0VmxIsValidReadField(uint32_t idxField) 3666 { 3667 switch (idxField) 3668 { 3669 /* Read-only fields. */ 3670 case VMX_VMCS_RO_EXIT_QUALIFICATION: 3671 return true; 3672 } 3673 /* Remaining readable fields should also be writable. */ 3674 return hmR0VmxIsValidWriteField(idxField); 3675 } 3676 # endif /* VBOX_STRICT */ 3677 3631 3678 3632 3679 /** … … 5930 5977 if (pVmcsInfo->pfnStartVM != VMXR0StartVM32) 5931 5978 Log4Func(("Selected 32-bit switcher\n")); 5932 pV Cpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;5979 pVmcsInfo->pfnStartVM = VMXR0StartVM32; 5933 5980 } 5934 5981 else … … 6210 6257 6211 6258 #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) 6212 #ifndef VMX_USE_CACHED_VMCS_ACCESSES 6213 # error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!" 6214 #endif 6215 #ifdef VBOX_STRICT 6216 static bool hmR0VmxIsValidWriteField(uint32_t idxField) 6217 { 6218 switch (idxField) 6219 { 6220 case VMX_VMCS_GUEST_RIP: 6221 case VMX_VMCS_GUEST_RSP: 6222 case VMX_VMCS_GUEST_SYSENTER_EIP: 6223 case VMX_VMCS_GUEST_SYSENTER_ESP: 6224 case VMX_VMCS_GUEST_GDTR_BASE: 6225 case VMX_VMCS_GUEST_IDTR_BASE: 6226 case VMX_VMCS_GUEST_CS_BASE: 6227 case VMX_VMCS_GUEST_DS_BASE: 6228 case VMX_VMCS_GUEST_ES_BASE: 6229 case VMX_VMCS_GUEST_FS_BASE: 6230 case VMX_VMCS_GUEST_GS_BASE: 6231 case VMX_VMCS_GUEST_SS_BASE: 6232 case VMX_VMCS_GUEST_LDTR_BASE: 6233 case VMX_VMCS_GUEST_TR_BASE: 6234 case VMX_VMCS_GUEST_CR3: 6235 return true; 6236 } 6237 return false; 6238 } 6239 6240 static bool hmR0VmxIsValidReadField(uint32_t idxField) 6241 { 6242 switch (idxField) 6243 { 6244 /* Read-only fields. */ 6245 case VMX_VMCS_RO_EXIT_QUALIFICATION: 6246 return true; 6247 } 6248 /* Remaining readable fields should also be writable. */ 6249 return hmR0VmxIsValidWriteField(idxField); 6250 } 6251 #endif /* VBOX_STRICT */ 6252 6259 # ifndef VMX_USE_CACHED_VMCS_ACCESSES 6260 # error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!" 6261 # endif 6253 6262 6254 6263 /**
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