Changeset 78650 in vbox for trunk/include
- Timestamp:
- May 22, 2019 9:41:16 AM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 130718
- File:
-
- 1 edited
-
trunk/include/VBox/vmm/hm_vmx.h (modified) (36 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/hm_vmx.h
r78637 r78650 213 213 /** CS.Attr.P bit invalid. */ 214 214 #define VMX_IGS_CS_ATTR_P_INVALID 516 215 /** CS.Attr reserved bits not set to 0. 215 /** CS.Attr reserved bits not set to 0. */ 216 216 #define VMX_IGS_CS_ATTR_RESERVED 517 217 217 /** CS.Attr.G bit invalid. */ … … 789 789 /* Invalidate all contexts (all EPTs) */ 790 790 VMXTLBFLUSHEPT_ALL_CONTEXTS = 2, 791 /** Unsupported by VirtualBox. 791 /** Unsupported by VirtualBox. */ 792 792 VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0, 793 793 /** Unsupported by CPU. */ … … 915 915 /** Always cleared to 0. */ 916 916 uint32_t u1Cleared0 : 1; 917 /** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. 917 /** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */ 918 918 uint32_t uOperandSize : 1; 919 919 uint32_t u3Undef0 : 3; … … 969 969 uint32_t iReg1 : 4; 970 970 uint32_t u4Undef0 : 4; 971 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. 971 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */ 972 972 uint32_t u2OperandSize : 2; 973 973 uint32_t u19Def0 : 20; … … 986 986 /** Memory or register operand. */ 987 987 uint32_t fIsRegOperand : 1; 988 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. 988 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */ 989 989 uint32_t u4Undef0 : 4; 990 990 /** The segment register (X86_SREG_XXX). */ … … 1017 1017 /** Memory/Register - Always cleared to 0 to indicate memory operand. */ 1018 1018 uint32_t fIsRegOperand : 1; 1019 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. 1019 /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */ 1020 1020 uint32_t uOperandSize : 2; 1021 1021 uint32_t u2Undef0 : 2; … … 1080 1080 #define VMXMSRPM_MASK (VMXMSRPM_RD_MASK | VMXMSRPM_WR_MASK) 1081 1081 /** */ 1082 /** Gets whether the MSR permission is valid or not. 1082 /** Gets whether the MSR permission is valid or not. */ 1083 1083 #define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \ 1084 1084 && ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \ … … 1331 1331 /** 62 - Page-modification log full. */ 1332 1332 #define VMX_EXIT_PML_FULL 62 1333 /** 63 - XSAVES - Guest software attempted to executedXSAVES and exiting was1333 /** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was 1334 1334 * enabled (XSAVES/XRSTORS was enabled too, of course). */ 1335 1335 #define VMX_EXIT_XSAVES 63 1336 /** 6 3 - XRSTORS - Guest software attempted to executedXRSTORS and exiting1336 /** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting 1337 1337 * was enabled (XSAVES/XRSTORS was enabled too, of course). */ 1338 1338 #define VMX_EXIT_XRSTORS 64 1339 /** 66 - SPP-related event. Attempt to determine an access' sub-page write 1340 * permission encountered an SPP miss or misconfiguration. */ 1341 #define VMX_EXIT_SPP_EVENT 66 1342 /* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */ 1343 #define VMX_EXIT_UMWAIT 67 1344 /** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was 1345 * enabled. */ 1346 #define VMX_EXIT_TPAUSE 68 1339 1347 /** The maximum exit value (inclusive). */ 1340 #define VMX_EXIT_MAX (VMX_EXIT_ XRSTORS)1348 #define VMX_EXIT_MAX (VMX_EXIT_TPAUSE) 1341 1349 /** @} */ 1342 1350 … … 1439 1447 #define VMX_BASIC_MEM_TYPE_WB 6 1440 1448 1441 /** Bit fields for MSR_IA32_VMX_BASIC. 1449 /** Bit fields for MSR_IA32_VMX_BASIC. */ 1442 1450 /** VMCS revision identifier used by the processor. */ 1443 1451 #define VMX_BF_BASIC_VMCS_ID_SHIFT 0 … … 1496 1504 #define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff) 1497 1505 1498 /** Bit fields for MSR_IA32_VMX_MISC. 1506 /** Bit fields for MSR_IA32_VMX_MISC. */ 1499 1507 /** Relationship between the preemption timer and tsc. */ 1500 1508 #define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0 … … 1509 1517 #define VMX_BF_MISC_RSVD_9_13_SHIFT 9 1510 1518 #define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00) 1511 /** Whether Intel PT (Processor Trace) can be used in VMX operation. 1519 /** Whether Intel PT (Processor Trace) can be used in VMX operation. */ 1512 1520 #define VMX_BF_MISC_INTEL_PT_SHIFT 14 1513 1521 #define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000) … … 1548 1556 * @{ 1549 1557 */ 1550 /** Bit 0 is reserved and RAZ. 1558 /** Bit 0 is reserved and RAZ. */ 1551 1559 #define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0 1552 1560 #define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001) … … 1554 1562 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1 1555 1563 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe) 1556 /** Bit 10:63 is reserved and RAZ. 1564 /** Bit 10:63 is reserved and RAZ. */ 1557 1565 #define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10 1558 1566 #define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00) … … 2215 2223 #define VMX_PROC_CTLS2_EPT_VE RT_BIT(18) 2216 2224 /** Conceal VMX non-root operation from Intel processor trace (PT). */ 2217 #define VMX_PROC_CTLS2_CONCEAL_ FROM_PTRT_BIT(19)2225 #define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19) 2218 2226 /** Enables XSAVES/XRSTORS instructions. */ 2219 2227 #define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20) … … 2222 2230 #define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22) 2223 2231 /** Enables EPT permissions to be specified at granularity of 128 bytes. */ 2224 #define VMX_PROC_CTLS2_SPPTP RT_BIT(23) 2232 #define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23) 2233 /** Intel PT output addresses are treated as guest-physical addresses and 2234 * translated using EPT. */ 2235 #define VMX_PROC_CTLS2_PT_EPT RT_BIT(24) 2225 2236 /** Use TSC scaling. */ 2226 2237 #define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25) 2238 /** Enables TPAUSE, UMONITOR and UMWAIT instructions. */ 2239 #define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26) 2227 2240 /** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */ 2228 2241 #define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28) … … 2268 2281 #define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18 2269 2282 #define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000) 2270 #define VMX_BF_PROC_CTLS2_CONCEAL_ FROM_PT_SHIFT192271 #define VMX_BF_PROC_CTLS2_CONCEAL_ FROM_PT_MASKUINT32_C(0x00080000)2283 #define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19 2284 #define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000) 2272 2285 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20 2273 2286 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000) … … 2276 2289 #define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22 2277 2290 #define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000) 2278 #define VMX_BF_PROC_CTLS2_SPPTP_ SHIFT232279 #define VMX_BF_PROC_CTLS2_SPPTP_ MASKUINT32_C(0x00800000)2280 #define VMX_BF_PROC_CTLS2_ UNDEF_24_SHIFT242281 #define VMX_BF_PROC_CTLS2_ UNDEF_24_MASKUINT32_C(0x01000000)2291 #define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23 2292 #define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000) 2293 #define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24 2294 #define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000) 2282 2295 #define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25 2283 2296 #define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000) 2284 #define VMX_BF_PROC_CTLS2_UNDEF_26_27_SHIFT 26 2285 #define VMX_BF_PROC_CTLS2_UNDEF_26_27_MASK UINT32_C(0x0c000000) 2297 #define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26 2298 #define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000) 2299 #define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27 2300 #define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000) 2286 2301 #define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28 2287 2302 #define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000) … … 2292 2307 (VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT, 2293 2308 UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC, 2294 VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21, 2295 MODE_BASED_EPT_PERM, SPPTP, UNDEF_24, TSC_SCALING, UNDEF_26_27, ENCLV_EXIT, UNDEF_29_31)); 2309 VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21, 2310 MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT, 2311 UNDEF_29_31)); 2296 2312 /** @} */ 2297 2313 … … 2318 2334 #define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16) 2319 2335 /** Whether to conceal VMX from Intel PT (Processor Trace). */ 2320 #define VMX_ENTRY_CTLS_CONCEAL_VMX_PT RT_BIT(17) 2336 #define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17) 2337 /** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */ 2338 #define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18) 2321 2339 /** Default1 class when true-capability MSRs are not supported. */ 2322 2340 #define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff) … … 2346 2364 #define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16 2347 2365 #define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000) 2348 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_SHIFT 17 2349 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_MASK UINT32_C(0x00020000) 2350 #define VMX_BF_ENTRY_CTLS_UNDEF_18_31_SHIFT 18 2351 #define VMX_BF_ENTRY_CTLS_UNDEF_18_31_MASK UINT32_C(0xfffc0000) 2366 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17 2367 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000) 2368 #define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18 2369 #define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000) 2370 #define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19 2371 #define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000) 2352 2372 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX, 2353 2373 (UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12, 2354 LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_PT, UNDEF_18_31)); 2374 LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, 2375 LOAD_RTIT_CTL_MSR, UNDEF_19_31)); 2355 2376 /** @} */ 2356 2377 … … 2380 2401 /** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */ 2381 2402 #define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23) 2382 /** Default1 class when true-capability MSRs are not supported. */ 2403 /** Whether to conceal VMX from Intel PT. */ 2404 #define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24) 2405 /** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */ 2406 #define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25) 2407 /** Default1 class when true-capability MSRs are not supported. */ 2383 2408 #define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff) 2384 2409 … … 2413 2438 #define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22 2414 2439 #define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000) 2415 #define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23 2416 #define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000) 2440 #define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23 2441 #define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000) 2442 #define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24 2443 #define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000) 2444 #define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25 2445 #define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000) 2446 #define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26 2447 #define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000) 2417 2448 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX, 2418 2449 (UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14, 2419 2450 ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR, 2420 SAVE_PREEMPT_TIMER, UNDEF_23_31));2451 SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31)); 2421 2452 /** @} */ 2422 2453 … … 2484 2515 #define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8 2485 2516 #define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700) 2486 /** Whether this event has an error code. 2517 /** Whether this event has an error code. */ 2487 2518 #define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11 2488 2519 #define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800) … … 2490 2521 #define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12 2491 2522 #define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000) 2492 /** Whether this VM-entry interruption info is valid. 2523 /** Whether this VM-entry interruption info is valid. */ 2493 2524 #define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31 2494 2525 #define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000) … … 2590 2621 * read or write. */ 2591 2622 #define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30) 2592 /** Gets whether the instruction ID is valid or not. 2623 /** Gets whether the instruction ID is valid or not. */ 2593 2624 #define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1) 2594 2625 #define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1) 2595 /** Gets the instruction ID. 2626 /** Gets the instruction ID. */ 2596 2627 #define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)) 2597 2628 /** No instruction ID info. */ … … 3023 3054 #define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c) 3024 3055 /** Address size, only 0(=16), 1(=32) and 2(=64) are defined. 3025 * @remarks anyone's guess why this is a 3 bit field... 3056 * @remarks anyone's guess why this is a 3 bit field... */ 3026 3057 #define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7 3027 3058 #define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380) … … 3082 3113 #define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078) 3083 3114 /** Address size, only 0(=16), 1(=32) and 2(=64) are defined. 3084 * @remarks anyone's guess why this is a 3 bit field... 3115 * @remarks anyone's guess why this is a 3 bit field... */ 3085 3116 #define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7 3086 3117 #define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380) … … 3140 3171 /** A debug exception would have been triggered by single-step execution mode. */ 3141 3172 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14) 3142 /** A debug exception occurred inside an RTM region. 3173 /** A debug exception occurred inside an RTM region. */ 3143 3174 #define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16) 3144 3175 /** Mask of valid bits. */ … … 3191 3222 /** The index. */ 3192 3223 uint32_t u8Index : 8; 3193 /** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. 3224 /** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */ 3194 3225 uint32_t u2Type : 2; 3195 3226 /** Reserved (MBZ). */ … … 3297 3328 3298 3329 /** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible 3299 * changes to the layout of VMXVVMCS is done. Bit 31 MBZ.*/3330 * changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */ 3300 3331 #define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001) 3301 3332 AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31))); … … 3307 3338 #define VMX_V_VMCS_PAGES 1 3308 3339 3309 /** The size of the Virtual-APIC page (in bytes). 3340 /** The size of the Virtual-APIC page (in bytes). */ 3310 3341 #define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE 3311 3342 /** The size of the Virtual-APIC page (in pages). */ … … 3430 3461 typedef struct 3431 3462 { 3432 /** 0x0 - VMX VMCS revision identifier. 3463 /** 0x0 - VMX VMCS revision identifier. */ 3433 3464 VMXVMCSREVID u32VmcsRevId; 3434 3465 /** 0x4 - VMX-abort indicator. */ … … 3544 3575 /** @name 32-bit Read-only Data fields. 3545 3576 * @{ */ 3546 /** 0xec - VM-instruction error. 3577 /** 0xec - VM-instruction error. */ 3547 3578 uint32_t u32RoVmInstrError; 3548 3579 /** 0xf0 - VM-exit reason. */ … … 3649 3680 /** 0x228 - APIC-access address. */ 3650 3681 RTUINT64U u64AddrApicAccess; 3651 /** 0x230 - Posted-interrupt descriptor address. 3682 /** 0x230 - Posted-interrupt descriptor address. */ 3652 3683 RTUINT64U u64AddrPostedIntDesc; 3653 /** 0x238 - VM-functions control. 3684 /** 0x238 - VM-functions control. */ 3654 3685 RTUINT64U u64VmFuncCtls; 3655 /** 0x240 - EPTP pointer. 3686 /** 0x240 - EPTP pointer. */ 3656 3687 RTUINT64U u64EptpPtr; 3657 /** 0x248 - EOI-exit bitmap 0. 3688 /** 0x248 - EOI-exit bitmap 0. */ 3658 3689 RTUINT64U u64EoiExitBitmap0; 3659 /** 0x250 - EOI-exit bitmap 1. 3690 /** 0x250 - EOI-exit bitmap 1. */ 3660 3691 RTUINT64U u64EoiExitBitmap1; 3661 /** 0x258 - EOI-exit bitmap 2. 3692 /** 0x258 - EOI-exit bitmap 2. */ 3662 3693 RTUINT64U u64EoiExitBitmap2; 3663 /** 0x260 - EOI-exit bitmap 3. 3694 /** 0x260 - EOI-exit bitmap 3. */ 3664 3695 RTUINT64U u64EoiExitBitmap3; 3665 /** 0x268 - EPTP-list address. 3696 /** 0x268 - EPTP-list address. */ 3666 3697 RTUINT64U u64AddrEptpList; 3667 /** 0x270 - VMREAD-bitmap address. 3698 /** 0x270 - VMREAD-bitmap address. */ 3668 3699 RTUINT64U u64AddrVmreadBitmap; 3669 /** 0x278 - VMWRITE-bitmap address. 3700 /** 0x278 - VMWRITE-bitmap address. */ 3670 3701 RTUINT64U u64AddrVmwriteBitmap; 3671 /** 0x280 - Virtualization-exception information address. 3702 /** 0x280 - Virtualization-exception information address. */ 3672 3703 RTUINT64U u64AddrXcptVeInfo; 3673 /** 0x288 - XSS-exiting bitmap. 3704 /** 0x288 - XSS-exiting bitmap. */ 3674 3705 RTUINT64U u64XssBitmap; 3675 /** 0x290 - ENCLS-exiting bitmap address. 3706 /** 0x290 - ENCLS-exiting bitmap address. */ 3676 3707 RTUINT64U u64EnclsBitmap; 3677 3708 /** 0x298 - Sub-page-permission-table pointer. */ 3678 3709 RTUINT64U u64SpptPtr; 3679 /** 0x2a0 - TSC multiplier. 3710 /** 0x2a0 - TSC multiplier. */ 3680 3711 RTUINT64U u64TscMultiplier; 3681 3712 /** 0x2a8 - Reserved for future. */ … … 3713 3744 /** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */ 3714 3745 RTUINT64U u64GuestBndcfgsMsr; 3715 /** 0x3b8 - Reserved for future. */ 3716 RTUINT64U au64Reserved2[16]; 3746 /** 0x3b8 - Guest RTIT control MSR (Intel Real Time Instruction Trace). */ 3747 RTUINT64U u64GuestRtitCtlMsr; 3748 /** 0x3c0 - Reserved for future. */ 3749 RTUINT64U au64Reserved2[15]; 3717 3750 /** @} */ 3718 3751 … … 3794 3827 /** 0x710 - Guest TR base. */ 3795 3828 RTUINT64U u64GuestTrBase; 3796 /** 0x718 - Guest GDTR base. 3829 /** 0x718 - Guest GDTR base. */ 3797 3830 RTUINT64U u64GuestGdtrBase; 3798 /** 0x720 - Guest IDTR base. 3831 /** 0x720 - Guest IDTR base. */ 3799 3832 RTUINT64U u64GuestIdtrBase; 3800 /** 0x728 - Guest DR7. 3833 /** 0x728 - Guest DR7. */ 3801 3834 RTUINT64U u64GuestDr7; 3802 /** 0x730 - Guest RSP. 3835 /** 0x730 - Guest RSP. */ 3803 3836 RTUINT64U u64GuestRsp; 3804 /** 0x738 - Guest RIP. 3837 /** 0x738 - Guest RIP. */ 3805 3838 RTUINT64U u64GuestRip; 3806 /** 0x740 - Guest RFLAGS. 3839 /** 0x740 - Guest RFLAGS. */ 3807 3840 RTUINT64U u64GuestRFlags; 3808 /** 0x748 - Guest pending debug exception. 3841 /** 0x748 - Guest pending debug exception. */ 3809 3842 RTUINT64U u64GuestPendingDbgXcpt; 3810 /** 0x750 - Guest SYSENTER ESP. 3843 /** 0x750 - Guest SYSENTER ESP. */ 3811 3844 RTUINT64U u64GuestSysenterEsp; 3812 /** 0x758 - Guest SYSENTER EIP. 3845 /** 0x758 - Guest SYSENTER EIP. */ 3813 3846 RTUINT64U u64GuestSysenterEip; 3814 3847 /** 0x760 - Reserved for future. */
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