Changeset 80274 in vbox for trunk/src/VBox/VMM/VMMR0/HMR0.cpp
- Timestamp:
- Aug 14, 2019 2:34:38 PM (5 years ago)
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- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r80266 r80274 20 20 * Header Files * 21 21 *********************************************************************************************************************************/ 22 #define VBOX_BUGREF_9217_PART_I 22 23 #define LOG_GROUP LOG_GROUP_HM 23 24 #define VMCPU_INCL_CPUM_GST_CTX … … 25 26 #include <VBox/vmm/pgm.h> 26 27 #include "HMInternal.h" 27 #include <VBox/vmm/vm .h>28 #include <VBox/vmm/vmcc.h> 28 29 #include <VBox/vmm/hm_svm.h> 29 30 #include <VBox/vmm/hmvmxinline.h> … … 87 88 /** @name Ring-0 method table for AMD-V and VT-x specific operations. 88 89 * @{ */ 89 DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu));90 DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));91 DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));92 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));93 DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,90 DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu)); 91 DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)); 92 DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu)); 93 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu)); 94 DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, 94 95 bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs)); 95 96 DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (void *pvCpuPage, RTHCPHYS HCPhysCpuPage)); 96 DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));97 DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));98 DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));97 DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM)); 98 DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM)); 99 DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM)); 99 100 /** @} */ 100 101 … … 227 228 * @{ */ 228 229 229 static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu)230 static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu) 230 231 { 231 232 RT_NOREF1(pVCpu); … … 233 234 } 234 235 235 static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)236 static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit) 236 237 { 237 238 RT_NOREF3(enmEvent, pVCpu, fGlobalInit); 238 239 } 239 240 240 static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,241 static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, 241 242 bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs) 242 243 { … … 251 252 } 252 253 253 static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)254 static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM) 254 255 { 255 256 RT_NOREF1(pVM); … … 257 258 } 258 259 259 static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)260 static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM) 260 261 { 261 262 RT_NOREF1(pVM); … … 263 264 } 264 265 265 static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)266 static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM) 266 267 { 267 268 RT_NOREF1(pVM); … … 269 270 } 270 271 271 static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)272 static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu) 272 273 { 273 274 RT_NOREF(pVCpu); … … 275 276 } 276 277 277 static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)278 static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu) 278 279 { 279 280 RT_NOREF1(pVCpu); … … 788 789 * @remarks Maybe called with interrupts disabled! 789 790 */ 790 static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)791 static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu) 791 792 { 792 793 PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu]; … … 824 825 static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2) 825 826 { 826 PVM pVM = (PVM)pvUser1; /* can be NULL! */827 PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */ 827 828 PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; 828 829 AssertReturnVoid(g_HmR0.fGlobalInit); … … 840 841 static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser) 841 842 { 842 PVM pVM = (PVM)pvUser;843 PVMCC pVM = (PVMCC)pvUser; 843 844 844 845 /* … … 956 957 * @param pVM The cross context VM structure. 957 958 */ 958 VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)959 VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM) 959 960 { 960 961 /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */ … … 1042 1043 * @param enmEvent The Mp event. 1043 1044 * @param idCpu The identifier for the CPU the function is called on. 1044 * @param pvData Opaque data (PVM pointer).1045 * @param pvData Opaque data (PVMCC pointer). 1045 1046 */ 1046 1047 static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData) … … 1158 1159 * vmR3InitRing3(). 1159 1160 */ 1160 VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)1161 VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM) 1161 1162 { 1162 1163 AssertReturn(pVM, VERR_INVALID_PARAMETER); … … 1235 1236 * Initialize some per-VCPU fields. 1236 1237 */ 1237 for (VMCPUID i = 0; i < pVM->cCpus; i++)1238 { 1239 PVMCPU pVCpu = &pVM->aCpus[i];1238 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 1239 { 1240 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu); 1240 1241 pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID; 1241 1242 pVCpu->hm.s.idLastCpu = NIL_RTCPUID; … … 1267 1268 * @param pVM The cross context VM structure. 1268 1269 */ 1269 VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)1270 VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM) 1270 1271 { 1271 1272 Log(("HMR0TermVM: %p\n", pVM)); … … 1290 1291 * @param pVM The cross context VM structure. 1291 1292 */ 1292 VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)1293 VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM) 1293 1294 { 1294 1295 Log(("HMR0SetupVM: %p\n", pVM)); … … 1299 1300 1300 1301 /* On first entry we'll sync everything. */ 1301 for (VMCPUID i = 0; i < pVM->cCpus; i++) 1302 { 1303 PVMCPU pVCpu = &pVM->aCpus[i]; 1304 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST; 1305 } 1302 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST); 1306 1303 1307 1304 /* … … 1351 1348 * @remarks No-long-jump zone!!! 1352 1349 */ 1353 VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)1350 VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu) 1354 1351 { 1355 1352 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); … … 1384 1381 * @remarks This is called with preemption disabled. 1385 1382 */ 1386 VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)1383 VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu) 1387 1384 { 1388 1385 /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */ … … 1437 1434 * @remarks No-long-jump zone!!! 1438 1435 */ 1439 VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)1436 VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu) 1440 1437 { 1441 1438 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); … … 1472 1469 VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser) 1473 1470 { 1474 PVMCPU pVCpu = (PVMCPU)pvUser;1471 PVMCPUCC pVCpu = (PVMCPUCC)pvUser; 1475 1472 Assert(pVCpu); 1476 1473 Assert(g_HmR0.pfnThreadCtxCallback); … … 1491 1488 * used!!! 1492 1489 */ 1493 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPUpVCpu)1490 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu) 1494 1491 { 1495 1492 RT_NOREF(pVM); … … 1527 1524 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 1528 1525 */ 1529 VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)1526 VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu) 1530 1527 { 1531 1528 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0); … … 1538 1535 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 1539 1536 */ 1540 VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)1537 VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu) 1541 1538 { 1542 1539 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT); … … 1561 1558 * @param GCVirt Page to invalidate. 1562 1559 */ 1563 VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)1564 { 1565 PVM pVM = pVCpu->CTX_SUFF(pVM);1560 VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt) 1561 { 1562 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 1566 1563 if (pVM->hm.s.vmx.fSupported) 1567 1564 return VMXR0InvalidatePage(pVCpu, GCVirt); … … 1592 1589 * @param fWhat What to import, CPUMCTX_EXTRN_XXX. 1593 1590 */ 1594 VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)1591 VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat) 1595 1592 { 1596 1593 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported) … … 1730 1727 * @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX). 1731 1728 */ 1732 VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu, uint32_t fFlags)1729 VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags) 1733 1730 { 1734 1731 /*
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