Changeset 80943 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Sep 23, 2019 9:36:14 AM (6 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

133523

Message:

Devices/PCI: Device model refactoring, part I. bugref:9218

Location:

trunk/src/VBox/Devices/Bus

Files:

• DevPCI.cpp (modified) (66 diffs)
• DevPciIch9.cpp (modified) (111 diffs)
• DevPciInternal.h (modified) (9 diffs)
• DevPciMerge1.cpp.h (modified) (4 diffs)
• MsiCommon.cpp (modified) (1 diff)

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -84 +84 @@
 RT_C_DECLS_BEGIN
 
-PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
-PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
+static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
 PDMBOTHCBDECL(int)  pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
 PDMBOTHCBDECL(int)  pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
@@ -111 +110 @@
 
 
-static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
-{
-    uint8_t iBus, iDevice;
-    uint32_t config_addr;
-
-    LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
-
-    if (!(pGlobals->uConfigReg & (1 << 31))) {
+static int pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
+{
+    LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
+
+    if (!(pGlobals->uConfigReg & (1 << 31)))
         return VINF_SUCCESS;
-    }
-    if ((pGlobals->uConfigReg & 0x3) != 0) {
+    if ((pGlobals->uConfigReg & 0x3) != 0)
         return VINF_SUCCESS;
-    }
-    iBus = (pGlobals->uConfigReg >> 16) & 0xff;
-    iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
-    config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
+
+    uint8_t  const iBus        = (pGlobals->uConfigReg >> 16) & 0xff;
+    uint8_t  const iDevice     = (pGlobals->uConfigReg >>  8) & 0xff;
+#ifdef IN_RING3
+    uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
+#endif
     RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
+
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     if (iBus != 0)
     {
@@ -137 +136 @@
             {
                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
-                pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
+                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
+                                                                     iDevice, config_addr, cb, u32Value);
             }
 #else
-            RT_NOREF2(val, len);
-            return VINF_IOM_R3_IOPORT_WRITE;
+            RT_NOREF(pDevIns, addr, u32Value, cb);
+            rcStrict = VINF_IOM_R3_IOPORT_WRITE;
 #endif
         }
@@ -147 +147 @@
     else
     {
-        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
-        if (pci_dev)
+        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
+        if (pPciDev)
         {
 #ifdef IN_RING3
-            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
-            return VBOXSTRICTRC_TODO(pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len));
+            LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigWrite)
+                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                                                           pPciDev, config_addr, cb, u32Value);
 #else
-            return VINF_IOM_R3_IOPORT_WRITE;
+            rcStrict = VINF_IOM_R3_IOPORT_WRITE;
 #endif
         }
     }
-    return VINF_SUCCESS;
-}
-
-static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
-{
-    uint8_t iBus, iDevice;
-    uint32_t config_addr;
-
-    *pu32 = 0xffffffff;
+    return rcStrict;
+}
+
+static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
+{
+    *pu32Value = UINT32_MAX;
 
     if (!(pGlobals->uConfigReg & (1 << 31)))
@@ -172 +174 @@
     if ((pGlobals->uConfigReg & 0x3) != 0)
         return VINF_SUCCESS;
-    iBus = (pGlobals->uConfigReg >> 16) & 0xff;
-    iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
-    config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
+    uint8_t const  iBus        = (pGlobals->uConfigReg >> 16) & 0xff;
+    uint8_t const  iDevice     = (pGlobals->uConfigReg >>  8) & 0xff;
+#ifdef IN_RING3
+    uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
+#endif
     RT_UNTRUSTED_VALIDATED_FENCE();
+
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     if (iBus != 0)
     {
@@ -185 +191 @@
             {
                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
-                *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
+                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
+                                                                    iBus, iDevice, config_addr, cb, pu32Value);
             }
 #else
-            NOREF(len);
-            return VINF_IOM_R3_IOPORT_READ;
+            RT_NOREF(addr, cb);
+            rcStrict = VINF_IOM_R3_IOPORT_READ;
 #endif
         }
@@ -195 +202 @@
     else
     {
-        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
-        if (pci_dev)
+        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
+        if (pPciDev)
         {
 #ifdef IN_RING3
-            *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
-            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigRead)
+                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
+            LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
 #else
-            NOREF(len);
-            return VINF_IOM_R3_IOPORT_READ;
+            NOREF(cb);
+            rcStrict = VINF_IOM_R3_IOPORT_READ;
 #endif
         }
     }
 
-    return VINF_SUCCESS;
+    return rcStrict;
 }
 
@@ -234 +245 @@
 }
 
-static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
+static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
+                         uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
 {
     /* This is only allowed to be called with a pointer to the host bus. */
@@ -253 +265 @@
         Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
               R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
-        pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
+        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
 
         if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
@@ -261 +273 @@
             Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
                   R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
-            pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
+            pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
         }
     } else {
         Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
               R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
-        pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
+        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iAcpiIrq, iLevel, uTagSrc);
     }
 }
@@ -278 +290 @@
  * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
  *
- * @param   pGlobals        Device instance of the host PCI Bus.
+ * @param   pPdmDev         The PDM device instance for the PCI bus.
+ * @param   pGlobals        Device instance of the host PCI bus.
+ * @param   pBusCC          Context specific data for the PCI bus.
  * @param   uDevFn          The device number on the host bus which will raise the IRQ
  * @param   pPciDev         The PCI device structure which raised the interrupt.
@@ -288 +302 @@
  *          is needed to calculate the PIRQ value.
  */
-static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
+static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
+                              uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
 {
     PDEVPCIBUS  pBus = &pGlobals->PciBus;
@@ -316 +331 @@
                  * PCI device configuration space).
                  */
-                apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
+                apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
             else
-                apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
+                apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
             return;
         }
@@ -368 +383 @@
         Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
               R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
-        pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
+        pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
 
         /** @todo optimize pci irq flip-flop some rainy day. */
         if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
-            pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
+            pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
     }
 }
@@ -380 +395 @@
  * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
  */
-PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
-{
-    pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
+static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
+{
+    PDEVPCIROOT  pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
+    pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
 }
 
@@ -454 +472 @@
 static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 };   /* bird: added const */
 
-static void pci_bios_init_device(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
+static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
+                                 PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
 {
     uint32_t *paddr;
@@ -474 +493 @@
                 {
                     /* PIIX3, PIIX4 or ICH6 IDE */
-                    devpciR3SetWord(pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
-                    devpciR3SetWord(pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing  */
+                    devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
+                    devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing  */
                     goto default_map;
                 }
@@ -481 +500 @@
                 {
                     /* IDE: we map it as in ISA mode */
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x1f0);
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 1, 0x3f4);
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 2, 0x170);
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 3, 0x374);
-                    devpciR3SetWord(pPciDev, PCI_COMMAND,
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
+                    devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
                                       devpciR3GetWord(pPciDev, PCI_COMMAND)
                                     | PCI_COMMAND_IOACCESS);
@@ -495 +514 @@
                     goto default_map;
                 /* VGA: map frame buffer to default Bochs VBE address */
-                devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0xe0000000);
+                devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0xe0000000);
                 /*
                  * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
@@ -501 +520 @@
                  * devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
                  */
-                devpciR3SetWord(pPciDev, PCI_COMMAND,
+                devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
                                   devpciR3GetWord(pPciDev, PCI_COMMAND)
                                 | PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS);
@@ -516 +535 @@
                     {
                         /* MPIC & MPIC2 */
-                        devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000 + 0x00040000);
-                        devpciR3SetWord(pPciDev, PCI_COMMAND,
+                        devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
+                        devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
                                           devpciR3GetWord(pPciDev, PCI_COMMAND)
                                         | PCI_COMMAND_MEMACCESS);
@@ -528 +547 @@
                 {
                     /* macio bridge */
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000);
-                    devpciR3SetWord(pPciDev, PCI_COMMAND,
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
+                    devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
                                       devpciR3GetWord(pPciDev, PCI_COMMAND)
                                     | PCI_COMMAND_MEMACCESS);
@@ -537 +556 @@
             {
                 /* Init PCI-to-PCI bridge. */
-                devpciR3SetByte(pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
 
                 AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
                 pGlobals->uPciBiosBus++;
-                devpciR3SetByte(pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
-                devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
 
                 /* Add position of this bridge into the array. */
@@ -555 +574 @@
                     pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
                 LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
-                devpciR3SetByte(pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
 
                 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
@@ -561 +580 @@
                     pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
                 LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
-                devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
+                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
 
                 /* Save values to compare later to. */
@@ -573 +592 @@
                     PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
                     if (pChildPciDev)
-                        pci_bios_init_device(pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
+                        pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
                 }
 
                 /* The number of bridges behind the this one is now available. */
-                devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
 
                 /*
@@ -590 +609 @@
                     pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
                 }
-                devpciR3SetByte(pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
+                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
 
                 /* Same with the MMIO limit register but with 1MB boundary here. */
@@ -598 +617 @@
                     pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
                 }
-                devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
+                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
 
                 /*
@@ -605 +624 @@
                  * the base register than in the limit register.
                  */
-                devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
-                devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
-                devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
-                devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
+                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
+                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
+                devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
+                devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
                 break;
             }
@@ -629 +648 @@
                     /* Calculate size. */
                     u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
-                    devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
+                    devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
                     u32Size = devpciR3GetDWord(pPciDev, u32Address);
                     bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
@@ -665 +684 @@
                                     i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
                             /* Undo the mapping mess caused by the size probing. */
-                            devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
+                            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
                         }
                         else
                         {
                             LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
-                            devpciR3BiosInitSetRegionAddress(pBus, pPciDev, i, uNew);
+                            devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
                             if (fIsPio)
                                 fActiveIORegion = true;
@@ -682 +701 @@
 
                 /* Update the command word appropriately. */
-                devpciR3SetWord(pPciDev, PCI_COMMAND,
+                devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
                                   devpciR3GetWord(pPciDev, PCI_COMMAND)
                                 | (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
@@ -709 +728 @@
             pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
             pic_irq = pci_irqs[pin];
-            devpciR3SetByte(pPciDev, PCI_INTERRUPT_LINE, pic_irq);
+            devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
         }
     }
@@ -750 +769 @@
         elcr[irq >> 3] |= (1 << (irq & 7));
         /* Activate irq remapping in PIIX3. */
-        devpciR3SetByte(pPIIX3, 0x60 + i, irq);
+        devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
     }
 
@@ -770 +789 @@
     {
         PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
-        uint8_t aBridgePositions[256];
-
         if (pPciDev)
         {
-            memset(aBridgePositions, 0, sizeof(aBridgePositions));
-            Log2(("PCI: Initializing device %d (%#x)\n",
-                  uDevFn, 0x80000000 | (uDevFn << 8)));
-            pci_bios_init_device(pGlobals, pBus, pPciDev, 0, aBridgePositions);
+            Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 | (uDevFn << 8)));
+            uint8_t aBridgePositions[256];
+            RT_ZERO(aBridgePositions);
+            pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
         }
     }
@@ -842 +859 @@
     {
         PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
-        rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
+        rc = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
         PCI_UNLOCK(pDevIns);
     }
@@ -984 +1001 @@
  *
  * @returns VBox status code.
+ * @param   pDevIns             The device instance.
  * @param   pBus                The bus which data is being loaded.
  * @param   pSSM                The saved state handle.
@@ -989 +1007 @@
  * @param   uPass               The pass.
  */
-static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
+static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
 {
     uint32_t    u32;
@@ -1010 +1028 @@
         {
             uint16_t u16 = PCIDevGetCommand(pDev);
-            pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
+            devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /*u32Value*/, 2 /*cb*/);
             PCIDevSetCommand(pDev, u16);
             Assert(PCIDevGetCommand(pDev) == u16);
@@ -1102 +1120 @@
         if (RT_FAILURE(rc))
             break;
-        devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
+        devpciR3CommonRestoreConfig(pDevIns, pDev, &DevTmp.abConfig[0]);
 
         pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
@@ -1157 +1175 @@
      * The devices.
      */
-    return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
+    return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
 }
 
@@ -1204 +1222 @@
 
 /* -=-=-=-=-=- PDMDEVREG  -=-=-=-=-=- */
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnReset}
+ */
+static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
+{
+    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUS  pBus     = &pGlobals->PciBus;
+
+    /* PCI-specific reset for each device. */
+    for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
+    {
+        if (pBus->apDevices[uDevFn])
+            devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
+    }
+
+    pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnDestruct}
+ */
+static DECLCALLBACK(int)   pciR3Destruct(PPDMDEVINS pDevIns)
+{
+    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    if (pGlobals->PciBus.papBridgesR3)
+    {
+        PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
+        pGlobals->PciBus.papBridgesR3 = NULL;
+    }
+    return VINF_SUCCESS;
+}
 
 
@@ -1243 +1294 @@
     Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
 
+    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+
     /*
      * Init data and register the PCI bus.
      */
-    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     pGlobals->uPciBiosIo   = 0xc000;
     pGlobals->uPciBiosMmio = 0xf0000000;
@@ -1253 +1306 @@
     memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
 
-    pGlobals->pDevInsR3 = pDevIns;
-    pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-
     pGlobals->PciBus.fTypePiix3  = true;
     pGlobals->PciBus.fTypeIch9   = false;
     pGlobals->PciBus.fPureBridge = false;
-    pGlobals->PciBus.pDevInsR3 = pDevIns;
-    pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
                                                                         sizeof(PPDMPCIDEV)
@@ -1268 +1314 @@
     AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
 
-
-    PDMPCIBUSREG PciBusReg;
-    PDEVPCIBUS   pBus = &pGlobals->PciBus;
-    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
-    PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
-    PciBusReg.pfnRegisterMsiR3        = NULL;
-    PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
-    PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
-    PciBusReg.pfnSetIrqR3             = pciSetIrq;
-    PciBusReg.pszSetIrqRC             = fGCEnabled ? "pciSetIrq" : NULL;
-    PciBusReg.pszSetIrqR0             = fR0Enabled ? "pciSetIrq" : NULL;
-    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
+    PDEVPCIBUS pBus = &pGlobals->PciBus;
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.pfnRegisterR3              = pciR3MergedRegister;
+    PciBusReg.pfnRegisterMsiR3           = NULL;
+    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
+    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
+    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
+    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
+    PciBusReg.pfnSetIrqR3                = pciSetIrq;
+    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
+    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
     if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Failed to register ourselves as a PCI Bus"));
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
     Assert(pBus->iBus == 0);
-    if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
+    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
         return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
                                    N_("PCI helper version mismatch; got %#x expected %#x"),
-                                   pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
-
-    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
-    pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
+                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
 
     /* Disable default device locking. */
@@ -1351 +1393 @@
     }
 
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
-;
+    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)");
     if (RT_FAILURE(rc))
         return rc;
@@ -1374 +1415 @@
 }
 
-
-/**
- * @interface_method_impl{PDMDEVREG,pfnDestruct}
- */
-static DECLCALLBACK(int)   pciR3Destruct(PPDMDEVINS pDevIns)
-{
-    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    if (pGlobals->PciBus.papBridgesR3)
-    {
-        PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
-        pGlobals->PciBus.papBridgesR3 = NULL;
-    }
-    return VINF_SUCCESS;
-}
-
-
-/**
- * @interface_method_impl{PDMDEVREG,pfnReset}
- */
-static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
-{
-    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS  pBus     = &pGlobals->PciBus;
-
-    /* PCI-specific reset for each device. */
-    for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
-    {
-        if (pBus->apDevices[uDevFn])
-            devpciR3ResetDevice(pBus->apDevices[uDevFn]);
-    }
-
-    pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
-}
-
-#endif /* IN_RING3 */
+#else  /* !IN_RING3 */
+
+/**
+ * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
+ */
+static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
+{
+    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.iBus          = pGlobals->PciBus.iBus;
+    PciBusReg.pfnSetIrq     = pciSetIrq;
+    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
+    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
+    AssertRC(rc);
+
+    return rc;
+}
+
+#endif /* !IN_RING3 */
 
 /**
@@ -1423 +1452 @@
     /* .uSharedVersion = */         42,
     /* .cbInstanceShared = */       sizeof(DEVPCIROOT),
-    /* .cbInstanceCC = */           0,
-    /* .cbInstanceRC = */           0,
+    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
+    /* .cbInstanceRC = */           sizeof(DEVPCIBUSRC),
     /* .cMaxPciDevices = */         2,
     /* .cMaxMsixVectors = */        0,
@@ -1455 +1484 @@
 #elif defined(IN_RING0)
     /* .pfnEarlyConstruct = */      NULL,
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           pciRZRootConstruct,
     /* .pfnDestruct = */            NULL,
     /* .pfnFinalDestruct = */       NULL,
@@ -1468 +1497 @@
     /* .pfnReserved7 = */           NULL,
 #elif defined(IN_RC)
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           pciRZRootConstruct,
     /* .pfnReserved0 = */           NULL,
     /* .pfnReserved1 = */           NULL,
@@ -1491 +1520 @@
  * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
  */
-PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
-{
+static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
+{
+    LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
+
     /*
      * The PCI-to-PCI bridge specification defines how the interrupt pins
@@ -1500 +1531 @@
      * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
      */
-    PDEVPCIBUS pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    PPDMPCIDEV pPciDevBus    = pPciDev;
-    int        iIrqPinBridge = iIrq;
-    uint8_t    uDevFnBridge  = 0;
+    PDEVPCIBUS   pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC        = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    PPDMPCIDEV   pPciDevBus    = pPciDev;
+    int          iIrqPinBridge = iIrq;
+    uint8_t      uDevFnBridge  = 0;
 
     /* Walk the chain until we reach the host bus. */
@@ -1517 +1549 @@
 
     AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
-    pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
+    pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), pBusCC, uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
 }
 
@@ -1525 +1557 @@
  * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
  */
-static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-
-    LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
+static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
+                                                         uint32_t u32Address, unsigned cb, uint32_t u32Value)
+{
+    LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
+    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -1538 +1571 @@
         {
             AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
-            pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
+            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
+                                                                 u32Address, cb, u32Value);
         }
     }
@@ -1548 +1582 @@
         {
             LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
-            /** @todo return rc   */
-            pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
-        }
-    }
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigWrite)
+                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                                                           pPciDev, u32Address, cb, u32Value);
+        }
+    }
+    return rcStrict;
 }
 
@@ -1558 +1597 @@
  * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
  */
-static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
-
+static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
+                                                        uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
+{
     LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
+    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -1571 +1610 @@
         if (pBridgeDevice)
         {
-            AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
-            u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
-        }
+            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
+            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
+                                                                iBus, iDevice, u32Address, cb, pu32Value);
+        }
+        else
+            *pu32Value = UINT32_MAX;
     }
     else
@@ -1581 +1623 @@
         if (pPciDev)
         {
-            u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
-            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
-        }
-    }
-
-    return u32Value;
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigRead)
+                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
+
+            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
+        }
+        else
+            *pu32Value = UINT32_MAX;
+    }
+
+    return rcStrict;
 }
 
@@ -1608 +1657 @@
     if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
         return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
-    return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
+    return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
 }
 
@@ -1623 +1672 @@
     pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
     pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnDestruct}
+ */
+static DECLCALLBACK(int)   pcibridgeR3Destruct(PPDMDEVINS pDevIns)
+{
+    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    if (pBus->papBridgesR3)
+    {
+        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
+        pBus->papBridgesR3 = NULL;
+    }
+    return VINF_SUCCESS;
 }
 
@@ -1655 +1719 @@
     Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
 
+    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
     /*
      * Init data and register the PCI bus.
      */
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     pBus->fTypePiix3  = true;
     pBus->fTypeIch9   = false;
     pBus->fPureBridge = true;
-    pBus->pDevInsR3 = pDevIns;
-    pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
     AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
 
-    PDMPCIBUSREG PciBusReg;
-    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
-    PciBusReg.pfnRegisterR3           = pcibridgeR3MergedRegisterDevice;
-    PciBusReg.pfnRegisterMsiR3        = NULL;
-    PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
-    PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
-    PciBusReg.pfnSetIrqR3             = pcibridgeSetIrq;
-    PciBusReg.pszSetIrqRC             = fGCEnabled ? "pcibridgeSetIrq" : NULL;
-    PciBusReg.pszSetIrqR0             = fR0Enabled ? "pcibridgeSetIrq" : NULL;
-    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.pfnRegisterR3              = pcibridgeR3MergedRegisterDevice;
+    PciBusReg.pfnRegisterMsiR3           = NULL;
+    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
+    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
+    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
+    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
+    PciBusReg.pfnSetIrqR3                = pcibridgeSetIrq;
+    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
+    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
     if (RT_FAILURE(rc))
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("Failed to register ourselves as a PCI Bus"));
     Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
-    if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
+    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
         return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
                                    N_("PCI helper version mismatch; got %#x expected %#x"),
-                                   pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
-
-    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
-    pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
+                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
 
     /*
@@ -1736 +1797 @@
 }
 
-
-/**
- * @interface_method_impl{PDMDEVREG,pfnDestruct}
- */
-static DECLCALLBACK(int)   pcibridgeR3Destruct(PPDMDEVINS pDevIns)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    if (pBus->papBridgesR3)
-    {
-        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
-        pBus->papBridgesR3 = NULL;
-    }
-    return VINF_SUCCESS;
-}
-
-#endif /* IN_RING3 */
+#else  /* !IN_RING3 */
+
+/**
+ * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
+ */
+static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
+{
+    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.iBus          = pBus->iBus;
+    PciBusReg.pfnSetIrq     = pcibridgeSetIrq;
+    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
+    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
+    AssertRC(rc);
+
+    return rc;
+}
+
+#endif /* !IN_RING3 */
 
 /**
@@ -1767 +1835 @@
     /* .uSharedVersion = */         42,
     /* .cbInstanceShared = */       sizeof(DEVPCIBUS),
-    /* .cbInstanceCC = */           0,
+    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
     /* .cbInstanceRC = */           0,
     /* .cMaxPciDevices = */         1,
@@ -1799 +1867 @@
 #elif defined(IN_RING0)
     /* .pfnEarlyConstruct = */      NULL,
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           pcibridgeRZConstruct,
     /* .pfnDestruct = */            NULL,
     /* .pfnFinalDestruct = */       NULL,
@@ -1812 +1880 @@
     /* .pfnReserved7 = */           NULL,
 #elif defined(IN_RC)
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           pcibridgeRZConstruct,
     /* .pfnReserved0 = */           NULL,
     /* .pfnReserved1 = */           NULL,

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -93 +93 @@
 *********************************************************************************************************************************/
 /* Prototypes */
-static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
-                                  int iIrq, int iLevel, uint32_t uTagSrc);
+static void ich9pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
+                                  uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc);
 #ifdef IN_RING3
 static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns);
 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
-static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus);
-static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun);
+static void ich9pciBiosInitAllDevicesOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus);
+static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun);
 #endif
 
@@ -125 +125 @@
 {
     LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
-    ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
+    ich9pciSetIrqInternal(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                          pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
 }
 
@@ -163 +164 @@
         || MsixIsEnabled(pPciDev))
         iIrqPinVector = iIrq;
-    ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
+    ich9pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                          uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
 }
 
@@ -292 +294 @@
  * Perform configuration space write.
  */
-static int ich9pciConfigWrite(PDEVPCIROOT pPciRoot, PciAddress* pAddr,
-                              uint32_t val, int cb, int rcReschedule)
-{
-    int rc = VINF_SUCCESS;
-#ifdef IN_RING3
-    NOREF(rcReschedule);
-#else
-    RT_NOREF2(val, cb);
-#endif
-
-    if (pAddr->iBus != 0)       /* forward to subordinate bus */
+static VBOXSTRICTRC ich9pciConfigWrite(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PciAddress const *pPciAddr,
+                                       uint32_t u32Value, int cb, int rcReschedule)
+{
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
+
+    if (pPciAddr->iBus != 0)       /* forward to subordinate bus */
     {
         if (pPciRoot->PciBus.cBridges)
         {
 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
-            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pAddr->iBus);
+            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pPciAddr->iBus);
             if (pBridgeDevice)
             {
                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
-                pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
-                                                          pAddr->iRegister, val, cb);
+                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
+                                                                     pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb, u32Value);
             }
 #else
-            rc = rcReschedule;
+            rcStrict = rcReschedule;
 #endif
         }
@@ -321 +318 @@
     else                    /* forward to directly connected device */
     {
-        R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pAddr->iDeviceFunc];
+        R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pPciAddr->iDeviceFunc];
         if (pPciDev)
         {
 #ifdef IN_RING3
-            rc = VBOXSTRICTRC_TODO(pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
-                                                                 pAddr->iRegister, val, cb));
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigWrite)
+                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
+                                                         pPciAddr->iRegister, cb, u32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                                                           pPciDev, pPciAddr->iRegister, cb, u32Value);
+            RT_NOREF(rcReschedule);
 #else
-            rc = rcReschedule;
+            rcStrict = rcReschedule;
+            RT_NOREF(pDevIns, u32Value, cb);
 #endif
         }
     }
 
-    Log2Func(("%02x:%02x.%d reg %x(%d) %x %Rrc\n",
-              pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister, cb, val, rc));
-    return rc;
+    Log2Func(("%02x:%02x.%u reg %x(%u) %x %Rrc\n", pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7,
+              pPciAddr->iRegister, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
+    return rcStrict;
 }
 
@@ -374 +378 @@
 
             /* Perform configuration space write */
-            rc = ich9pciConfigWrite(pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
+            rc = ich9pciConfigWrite(pDevIns, pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
         } while (0);
 
@@ -388 +392 @@
  * Perform configuration space read.
  */
-static int ich9pciConfigRead(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb,
-                             uint32_t *pu32, int rcReschedule)
-{
-    int rc = VINF_SUCCESS;
+static VBOXSTRICTRC ich9pciConfigRead(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb, uint32_t *pu32Value, int rcReschedule)
+{
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
 #ifdef IN_RING3
     NOREF(rcReschedule);
@@ -407 +410 @@
             {
                 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
-                *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
-                                                                 pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
+                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
+                                                                    pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb, pu32Value);
             }
             else
-                *pu32 = 0xffffffff;
+                *pu32Value = UINT32_MAX;
 #else
-            rc = rcReschedule;
+            rcStrict = rcReschedule;
 #endif
         }
         else
-            *pu32 = 0xffffffff;
+            *pu32Value = 0xffffffff;
     }
     else                    /* forward to directly connected device */
@@ -425 +428 @@
         {
 #ifdef IN_RING3
-            *pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigRead)
+                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
+                                                        pPciAddr->iRegister, cb, pu32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, pPciAddr->iRegister, cb, pu32Value);
 #else
-            rc = rcReschedule;
+            rcStrict = rcReschedule;
 #endif
         }
         else
-            *pu32 = 0xffffffff;
-    }
-
-    Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
-              pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister, cb, *pu32, rc));
-    return rc;
+            *pu32Value = UINT32_MAX;
+    }
+
+    Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n", pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7,
+              pPciAddr->iRegister, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict) ));
+    return rcStrict;
 }
 
@@ -457 +465 @@
 {
     NOREF(pvUser);
-    int rc = VINF_SUCCESS;
     if (!(uPort % cb))
     {
@@ -465 +472 @@
         PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
 
-        do
-        {
-            /* Configuration space mapping enabled? */
-            if (!(pThis->uConfigReg & (1 << 31)))
-            {
-                rc = VINF_SUCCESS;
-                break;
-            }
-
+        /* Configuration space mapping enabled? */
+        int rc;
+        if (!(pThis->uConfigReg & (1 << 31)))
+            rc = VINF_SUCCESS;
+        else
+        {
             /* Decode target device and configuration space register */
             PciAddress aPciAddr;
@@ -479 +483 @@
 
             /* Perform configuration space read */
-            rc =  ich9pciConfigRead(pThis, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
-        } while (0);
+            rc = ich9pciConfigRead(pThis, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
+        }
 
         PCI_UNLOCK(pDevIns);
@@ -528 +532 @@
 }
 
-static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
-                              uint32_t uTagSrc, int iForcedIrq)
+static void ich9pciApicSetIrq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
+                              uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, uint32_t uTagSrc, int iForcedIrq)
 {
     /* This is only allowed to be called with a pointer to the root bus. */
@@ -549 +553 @@
         Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
                   R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
-        pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
+        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
 
         if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
@@ -562 +566 @@
             Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
                       R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
-            pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
+            pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
         }
     } else {
         Log3Func(("(forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
                   R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
-        pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
-    }
-}
-
-static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
-                                  int iIrq, int iLevel, uint32_t uTagSrc)
+        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iForcedIrq, iLevel, uTagSrc);
+    }
+}
+
+static void ich9pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
+                                  uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
 {
     /* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
@@ -583 +587 @@
         Assert(!MsixIsEnabled(pPciDev));    /* Not allowed -- see note above. */
         LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
-        PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
-        MsiNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
+        MsiNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
         return;
     }
@@ -591 +594 @@
     {
         LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
-        PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
-        MsixNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
+        MsixNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
         return;
     }
@@ -618 +620 @@
              */
             /* safe, only needs to go to the config space array */
-            ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
+            ich9pciApicSetIrq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
         else
-            ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
+            ich9pciApicSetIrq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
     }
 }
@@ -670 +672 @@
 
     /* Perform configuration space write */
-    int rc = ich9pciConfigWrite(pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
+    int rc = ich9pciConfigWrite(pDevIns, pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
     PCI_UNLOCK(pDevIns);
 
@@ -770 +772 @@
 uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
 {
-    return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
+    uint32_t     u32Value = UINT32_MAX;
+    VBOXSTRICTRC rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+    if (pPciDev->Int.s.pfnConfigRead)
+        rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb, &u32Value);
+    if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+        rcStrict = devpciR3CommonConfigReadWorker(pPciDev, iRegister, cb, &u32Value);
+    AssertRCSuccess(rcStrict);
+    return u32Value;
 }
 
@@ -779 +788 @@
 }
 
-void devpciR3SetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb)
-{
-    pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, u32, cb);
+/**
+ * Worker for devpciR3SetByte(), devpciR3SetWord() and devpciR3SetDWord(), also
+ * used during state restore.
+ */
+void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32Value, int cb)
+{
+    Assert(cb <= 4 && cb != 3);
+    VBOXSTRICTRC rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+    if (pPciDev->Int.s.pfnConfigWrite)
+        rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb, u32Value);
+    if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+        rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                                                   pPciDev, iRegister, cb, u32Value);
+    AssertRCSuccess(rcStrict);
 }
 
@@ -790 +810 @@
 static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
 {
-    NOREF(pDevIns);
-    int rc;
-
-    rc = MsiR3Init(pPciDev, pMsiReg);
-    if (RT_FAILURE(rc))
-        return rc;
-
-    rc = MsixR3Init(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
-    if (RT_FAILURE(rc))
-        return rc;
-
-    return VINF_SUCCESS;
+    //PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
+    int rc = MsiR3Init(pPciDev, pMsiReg);
+    if (RT_SUCCESS(rc))
+        rc = MsixR3Init(pBusCC->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
+
+    return rc;
 }
 
@@ -871 +887 @@
 
 /**
- * @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
- */
-DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
-                                                    PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
-                                                    PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
+ * @interface_method_impl{PDMPCIBUSREG,pfnInterceptConfigAccesses}
+ */
+DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                         PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
 {
     NOREF(pDevIns);
 
-    if (ppfnReadOld)
-        *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
     pPciDev->Int.s.pfnConfigRead  = pfnRead;
-
-    if (ppfnWriteOld)
-        *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
     pPciDev->Int.s.pfnConfigWrite = pfnWrite;
 }
@@ -979 +989 @@
 
 
-static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-
-    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
+/**
+ * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice,
+                                                           uint32_t u32Address, unsigned cb, uint32_t u32Value)
+{
+    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
+    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%#x cb=%d u32Value=%#x\n", pDevIns, uBus, uDevice, u32Address, cb, u32Value));
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -994 +1008 @@
             AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
             pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
-                                                      u32Address, u32Value, cb);
+                                                      u32Address, cb, u32Value);
         }
     }
@@ -1004 +1018 @@
         {
             LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
-            /** @todo return rc */
-            pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
-        }
-    }
-}
-
-static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, unsigned cb)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    uint32_t u32Value;
-
-    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigWrite)
+                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
+                                                           pPciDev, u32Address, cb, u32Value);
+        }
+    }
+    return rcStrict;
+}
+
+/**
+ * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice,
+                                                          uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
+{
+    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
+    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%#x cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -1024 +1046 @@
         if (pBridgeDevice)
         {
-            AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
-            u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
-                                                                u32Address, cb);
+            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
+            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
+                                                                u32Address, cb, pu32Value);
         }
         else
-            u32Value = 0xffffffff;
+            *pu32Value = UINT32_MAX;
     }
     else
@@ -1037 +1059 @@
         if (pPciDev)
         {
-            u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
-            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
+            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
+            if (pPciDev->Int.s.pfnConfigRead)
+                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
+            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
+                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
+            LogFunc(("%s: u32Address=%02x *pu32Value=%#010x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
         }
         else
-            u32Value = 0xffffffff;
-    }
-
-    return u32Value;
+            *pu32Value = UINT32_MAX;
+    }
+
+    return rcStrict;
 }
 
@@ -1055 +1081 @@
  * Common routine for restoring the config registers of a PCI device.
  *
+ * @param   pDevIns             The device instance of the PC bus.
  * @param   pDev                The PCI device.
  * @param   pbSrcConfig         The configuration register values to be loaded.
  */
-void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
+void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
 {
     /*
@@ -1199 +1226 @@
                     /* safe, only needs to go to the config space array */
                     PDMPciDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec/ich9pciR3CommonLoadExec. */
-                pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
+                devpciR3SetCfg(pDevIns, pDev, off, u32Src, cb);
             }
         }
@@ -1312 +1339 @@
  *
  * @returns VBox status code.
+ * @param   pDevIns             The device instance of the bus.
  * @param   pBus                The bus which data is being loaded.
  * @param   pSSM                The saved state handle.
@@ -1317 +1345 @@
  * @param   uPass               The pass.
  */
-static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
-{
-    uint32_t    u32;
-    int         rc;
+static int ich9pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
+{
+    uint32_t     u32;
+    int          rc;
 
     Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
@@ -1342 +1370 @@
             /* safe, only needs to go to the config space array */
             uint16_t u16 = PDMPciDevGetCommand(pDev);
-            pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
+            devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /*u32Value*/, 2 /*cb*/);
             /* safe, only needs to go to the config space array */
             PDMPciDevSetCommand(pDev, u16);
@@ -1463 +1491 @@
             break;
         Assert(!pciDevIsPassthrough(pDev));
-        devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
+        devpciR3CommonRestoreConfig(pDevIns, pDev, &DevTmp.abConfig[0]);
 
         pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
@@ -1514 +1542 @@
         AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
 
-    return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
+    return ich9pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
 }
 
@@ -1520 +1548 @@
 {
     PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
+    return ich9pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
 }
 
@@ -1528 +1556 @@
 
 
-void devpciR3BiosInitSetRegionAddress(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr)
+void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr)
 {
     NOREF(pBus);
@@ -1542 +1570 @@
 
     /* Write address of the device. */
-    devpciR3SetDWord(pPciDev, uReg, (uint32_t)addr);
+    devpciR3SetDWord(pDevIns, pPciDev, uReg, (uint32_t)addr);
     if (f64Bit)
-        devpciR3SetDWord(pPciDev, uReg + 4, (uint32_t)(addr >> 32));
-}
-
-
-static void ich9pciBiosInitBridge(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
+        devpciR3SetDWord(pDevIns, pPciDev, uReg + 4, (uint32_t)(addr >> 32));
+}
+
+
+static void ich9pciBiosInitBridge(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
 {
     PPDMPCIDEV pBridge = &pBus->PciDev;
@@ -1563 +1591 @@
         LogFunc(("Aligned I/O start address. New address %#x\n", pPciRoot->uPciBiosIo));
     }
-    devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0);
+    devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0);
 
     /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
@@ -1571 +1599 @@
         LogFunc(("Aligned MMIO start address. New address %#x\n", pPciRoot->uPciBiosMmio));
     }
-    devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
+    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
 
     /* Save values to compare later to. */
@@ -1578 +1606 @@
 
     /* Init all devices behind the bridge (recursing to further buses). */
-    ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
+    ich9pciBiosInitAllDevicesOnBus(pDevIns, pPciRoot, pBus);
 
     /*
@@ -1588 +1616 @@
         /* Need again alignment to a 4KB boundary. */
         pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K);
-        devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0);
+        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0);
     }
     else
     {
-        devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, 0xf0);
-        devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, 0x00);
+        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_BASE, 0xf0);
+        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_LIMIT, 0x00);
     }
 
@@ -1600 +1628 @@
     {
         pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
-        devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0));
+        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0));
     }
     else
     {
-        devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, 0xfff0);
-        devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, 0x0000);
+        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_BASE, 0xfff0);
+        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_LIMIT, 0x0000);
     }
 
@@ -1613 +1641 @@
      * the base register than in the limit register.
      */
-    devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
-    devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0000);
-    devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, 0x00000000);
-    devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00000000);
+    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
+    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0000);
+    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_BASE_UPPER32, 0x00000000);
+    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00000000);
 }
 
@@ -1635 +1663 @@
 }
 
-static void ich9pciBiosInitDeviceBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev)
+static void ich9pciBiosInitDeviceBARs(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev)
 {
     int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
@@ -1669 +1697 @@
         if (f64Bit)
         {
-            devpciR3SetDWord(pPciDev, u32Address,   UINT32_C(0xffffffff));
-            devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address,   UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address+4, UINT32_C(0xffffffff));
             cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
                                       devpciR3GetDWord(pPciDev, u32Address+4));
@@ -1684 +1712 @@
         {
             uint32_t cbRegSize32;
-            devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
             cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
 
@@ -1731 +1759 @@
                     uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
                     LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
                     fActiveMemRegion = true;
                     pPciRoot->uPciBiosMmio64 = uNew + cbRegSize64;
@@ -1743 +1771 @@
                             iRegion, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
                     /* Undo the mapping mess caused by the size probing. */
-                    devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
+                    devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
                 }
             }
@@ -1749 +1777 @@
             {
                 LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
-                devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
+                devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
                 if (fIsPio)
                     fActiveIORegion = true;
@@ -1769 +1797 @@
     if (fActiveIORegion)
         uCmd |= VBOX_PCI_COMMAND_IO; /* Enable I/O space access. */
-    devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
-}
-
-static bool ich9pciBiosInitDevicePrefetchableBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, bool fUse64Bit, bool fDryrun)
+    devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd);
+}
+
+static bool ich9pciBiosInitDevicePrefetchableBARs(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, bool fUse64Bit, bool fDryrun)
 {
     int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
@@ -1792 +1820 @@
         if (f64Bit)
         {
-            devpciR3SetDWord(pPciDev, u32Address,   UINT32_C(0xffffffff));
-            devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address,   UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address+4, UINT32_C(0xffffffff));
             cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
                                       devpciR3GetDWord(pPciDev, u32Address+4));
@@ -1802 +1830 @@
         {
             uint32_t cbRegSize32;
-            devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
+            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
             cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
             cbRegSize32 &= ~UINT32_C(0x0f);
@@ -1831 +1859 @@
                 {
                     LogFunc(("Start address of MMIO region %u is %#x\n", iRegion, uNew));
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
                     fActiveMemRegion = true;
                 }
@@ -1851 +1879 @@
                 {
                     LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
-                    devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
+                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
                     fActiveMemRegion = true;
                 }
@@ -1867 +1895 @@
         if (fActiveMemRegion)
             uCmd |= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */
-        devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
+        devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd);
     }
     else
@@ -1875 +1903 @@
 }
 
-static bool ich9pciBiosInitBridgePrefetchable(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
+static bool ich9pciBiosInitBridgePrefetchable(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
 {
     PPDMPCIDEV pBridge = &pBus->PciDev;
@@ -1888 +1916 @@
 
     /* Init all devices behind the bridge (recursing to further buses). */
-    bool fRes = ich9pciBiosInitAllDevicesPrefetchableOnBus(pPciRoot, pBus, fUse64Bit, fDryrun);
+    bool fRes = ich9pciBiosInitAllDevicesPrefetchableOnBus(pDevIns, pPciRoot, pBus, fUse64Bit, fDryrun);
     if (fDryrun)
         return fRes;
@@ -1909 +1937 @@
         uLimit = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M) - 1;
     }
-    devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32);
-    devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, (uint32_t)(uBase >> 16) & UINT32_C(0xfff0));
-    devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, uLimit >> 32);
-    devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, (uint32_t)(uLimit >> 16) & UINT32_C(0xfff0));
+    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32);
+    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_BASE, (uint32_t)(uBase >> 16) & UINT32_C(0xfff0));
+    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, uLimit >> 32);
+    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, (uint32_t)(uLimit >> 16) & UINT32_C(0xfff0));
 
     return false;
 }
 
-static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
+static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus,
+                                                       bool fUse64Bit, bool fDryrun)
 {
     /* First pass: assign resources to all devices. */
@@ -1931 +1960 @@
 
         /* prefetchable memory mappings */
-        bool fRes = ich9pciBiosInitDevicePrefetchableBARs(pPciRoot, pBus, pPciDev, fUse64Bit, fDryrun);
+        bool fRes = ich9pciBiosInitDevicePrefetchableBARs(pDevIns, pPciRoot, pBus, pPciDev, fUse64Bit, fDryrun);
         if (fRes)
         {
@@ -1947 +1976 @@
         PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
 
-        bool fRes = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, fUse64Bit, fDryrun);
+        bool fRes = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, fUse64Bit, fDryrun);
         if (fRes)
         {
@@ -1957 +1986 @@
 }
 
-static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
+static void ich9pciBiosInitAllDevicesOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
 {
     /* First pass: assign resources to all devices and map the interrupt. */
@@ -1971 +2000 @@
 
         /* default memory mappings */
-        ich9pciBiosInitDeviceBARs(pPciRoot, pBus, pPciDev);
+        ich9pciBiosInitDeviceBARs(pDevIns, pPciRoot, pBus, pPciDev);
         uint16_t uDevClass = devpciR3GetWord(pPciDev, VBOX_PCI_CLASS_DEVICE);
         switch (uDevClass)
@@ -1977 +2006 @@
             case 0x0101:
                 /* IDE controller */
-                devpciR3SetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
-                devpciR3SetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
+                devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8000); /* enable IDE0 */
+                devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8000); /* enable IDE1 */
                 break;
             case 0x0300:
@@ -1994 +2023 @@
                  */
                 uint16_t uCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
-                devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd | VBOX_PCI_COMMAND_IO);
+                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd | VBOX_PCI_COMMAND_IO);
                 break;
             }
@@ -2019 +2048 @@
             Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
                  iPin, iIrq, pBus->iBus, uDevFn>>3, uDevFn&7));
-            devpciR3SetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, iIrq);
+            devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_INTERRUPT_LINE, iIrq);
         }
     }
@@ -2031 +2060 @@
         PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
 
-        ich9pciBiosInitBridge(pPciRoot, pChildBus);
+        ich9pciBiosInitBridge(pDevIns, pPciRoot, pChildBus);
     }
 
@@ -2049 +2078 @@
             uint64_t u64MMIOAddressBase = pPciRoot->uPciBiosMmio64;
 
-            bool fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit */, true /* fDryrun */);
+            bool fProbe = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, false /* fUse64Bit */, true /* fDryrun */);
             pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
             pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
             if (fProbe)
             {
-                fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit */, true /* fDryrun */);
+                fProbe = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, true /* fUse64Bit */, true /* fDryrun */);
                 pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
                 pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
@@ -2060 +2089 @@
                     LogRel(("PCI: unresolvable prefetchable memory behind bridge %02x:%02x.%d\n", pChildBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7));
                 else
-                    ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit */, false /* fDryrun */);
+                    ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, true /* fUse64Bit */, false /* fDryrun */);
             }
             else
-                ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit */, false /* fDryrun */);
+                ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, false /* fUse64Bit */, false /* fDryrun */);
         }
     }
@@ -2082 +2111 @@
  * @param   uBusPrimary      The primary bus number the bus is connected to.
  */
-static uint8_t ich9pciBiosInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, uint32_t *pbmUsed, uint8_t uBusPrimary)
+static uint8_t ich9pciBiosInitBridgeTopology(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus,
+                                             uint32_t *pbmUsed, uint8_t uBusPrimary)
 {
     PPDMPCIDEV pBridgeDev = &pBus->PciDev;
@@ -2095 +2125 @@
     if (pBus->iBus != 0)
     {
-        devpciR3SetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
-        devpciR3SetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
+        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
+        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
         /* Since the subordinate bus value can only be finalized once we
          * finished recursing through everything behind the bridge, the only
@@ -2103 +2133 @@
          * (for our own sloppy emulation it apparently doesn't matter, but
          * this is vital for real PCI bridges/devices in passthrough mode). */
-        devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
+        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
     }
 
@@ -2113 +2143 @@
                   ("Device is not a PCI bridge but on the list of PCI bridges\n"));
         PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
-        uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pPciRoot, pChildBus, pbmUsed, pBus->iBus);
+        uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pDevIns, pPciRoot, pChildBus, pbmUsed, pBus->iBus);
         uMaxSubNum = RT_MAX(uMaxSubNum, uMaxChildSubBus);
     }
 
     if (pBus->iBus != 0)
-        devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
+        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
     for (uint32_t i = pBus->iBus; i <= uMaxSubNum; i++)
         *pbmUsed |= RT_BIT_32(i);
@@ -2126 +2156 @@
      * but on the other hand it can't hurt either. */
     if (pBus->iBus != 0)
-        devpciR3SetWord(pBridgeDev, VBOX_PCI_COMMAND,
+        devpciR3SetWord(pDevIns, pBridgeDev, VBOX_PCI_COMMAND,
                           VBOX_PCI_COMMAND_IO
                         | VBOX_PCI_COMMAND_MEMORY
@@ -2132 +2162 @@
 
     /* safe, only needs to go to the config space array */
-    Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n",
-          pBus,
-          PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
-          PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
-          PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
-          ));
+    Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n", pBus,
+              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
+              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
+              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS) ));
 
     return uMaxSubNum;
@@ -2184 +2212 @@
     AssertLogRel(pBus->iBus == 0);
     uint32_t bmUsed = 0;
-    ich9pciBiosInitBridgeTopology(pPciRoot, pBus, &bmUsed, 0);
+    ich9pciBiosInitBridgeTopology(pDevIns, pPciRoot, pBus, &bmUsed, 0);
 
     /*
      * Init all devices on bus 0 (recursing to further buses).
      */
-    ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
+    ich9pciBiosInitAllDevicesOnBus(pDevIns, pPciRoot, pBus);
 
     return VINF_SUCCESS;
@@ -2199 +2227 @@
 
 /**
- * @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
- */
-DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
-{
-    NOREF(pDevIns);
-
+ * Reads config space for a device, ignoring interceptors.
+ */
+DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
+{
     uint32_t uValue;
     if (uAddress + cb <= 256)
@@ -2246 +2272 @@
         uValue = 0;
     }
-    return uValue;
+
+    *pu32Value = uValue;
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * @interface_method_impl{PDMPCIBUSREGR3,pfnConfigRead}
+ */
+DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                    uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
+{
+    RT_NOREF(pDevIns);
+    return devpciR3CommonConfigReadWorker(pPciDev, uAddress, cb, pu32Value);
 }
 
@@ -2254 +2293 @@
  *
  * @returns VBox status code.
+ * @param   pDevIns             The PCI bus device instance.
  * @param   pDev                The PCI device.
  * @param   iRegion             The region to unmap.
  */
-static int devpciR3UnmapRegion(PPDMPCIDEV pDev, int iRegion)
+static int devpciR3UnmapRegion(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, int iRegion)
 {
     PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
@@ -2275 +2315 @@
         else
         {
-            PDEVPCIBUS pBus       = pDev->Int.s.CTX_SUFF(pBus);
-            RTGCPHYS   GCPhysBase = pRegion->addr;
-            if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
+            PDEVPCIBUSCC pBusCC     = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+            RTGCPHYS     GCPhysBase = pRegion->addr;
+            if (pBusCC->pPciHlpR3->pfnIsMMIOExBase(pDevIns, pDev->Int.s.pDevInsR3, GCPhysBase))
             {
                 /* unmap it. */
@@ -2299 +2339 @@
  *
  * @returns VINF_SUCCESS of DBGFSTOP result.
+ * @param   pDevIns             The PCI bus device instance.
  * @param   pPciDev             The PCI device to update the mappings for.
  * @param   fP2PBridge          Whether this is a PCI to PCI bridge or not.
  */
-static VBOXSTRICTRC devpciR3UpdateMappings(PPDMPCIDEV pPciDev, bool fP2PBridge)
+static VBOXSTRICTRC devpciR3UpdateMappings(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, bool fP2PBridge)
 {
     /* safe, only needs to go to the config space array */
@@ -2406 +2447 @@
                          pPciDev->pszNameR3, iRegion, pRegion->addr, uNew, cbRegion, cbRegion));
 
-                devpciR3UnmapRegion(pPciDev, iRegion);
+                devpciR3UnmapRegion(pDevIns, pPciDev, iRegion);
                 pRegion->addr = uNew;
                 if (uNew != INVALID_PCI_ADDRESS)
                 {
                     int rc = pRegion->map_func(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, uNew, cbRegion,
-                                               (PCIADDRESSSPACE)(pRegion->type));
+                                               (PCIADDRESSSPACE)pRegion->type);
                     AssertRC(rc);
                 }
@@ -2546 +2587 @@
 
 /**
- * @callback_method_impl{PFNPCICONFIGWRITE,
- *      Default config space write callback.}
+ * Writes config space for a device, ignoring interceptors.
  *
  * See paragraph 7.5 of PCI Express specification (p. 349) for
  * definition of registers and their writability policy.
  */
-DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
-                                                            uint32_t uAddress, uint32_t u32Value, unsigned cb)
-{
-    NOREF(pDevIns);
-    Assert(cb <= 4);
-    VBOXSTRICTRC rcRet = VINF_SUCCESS;
+DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
+                                                         PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value)
+{
+    Assert(cb <= 4 && cb != 3);
+    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
 
     if (uAddress + cb <= 256)
@@ -2566 +2605 @@
         if (   pciDevIsMsiCapable(pPciDev)
             && uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
-            MsiR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
-                                pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
-                                pPciDev, uAddress, u32Value, cb);
+            MsiR3PciConfigWrite(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, uAddress, u32Value, cb);
         else if (   pciDevIsMsixCapable(pPciDev)
                  && uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
-            MsixR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
-                                 pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
-                                 pPciDev, uAddress, u32Value, cb);
+            MsixR3PciConfigWrite(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, uAddress, u32Value, cb);
         else
         {
@@ -2684 +2719 @@
              */
             if (fUpdateMappings)
-                rcRet = devpciR3UpdateMappings(pPciDev, fP2PBridge);
+                rcStrict = devpciR3UpdateMappings(pDevIns, pPciDev, fP2PBridge);
         }
     }
@@ -2693 +2728 @@
         AssertMsgFailed(("Write after end of PCI config space\n"));
 
-    return rcRet;
+    return rcStrict;
+}
+
+
+/**
+ * @interface_method_impl{PDMPCIBUSREGR3,pfnConfigWrite}
+ */
+DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                     uint32_t uAddress, unsigned cb, uint32_t u32Value)
+{
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    return devpciR3CommonConfigWriteWorker(pDevIns, pBusCC, pPciDev, uAddress, cb, u32Value);
 }
 
@@ -2976 +3022 @@
  * @interface_method_impl{PDMDEVREG,pfnConstruct}
  */
-static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE  pCfg)
+static DECLCALLBACK(int) ich9pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE  pCfg)
 {
     RT_NOREF1(iInstance);
@@ -3019 +3065 @@
      * Init data.
      */
-    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS  pBus     = &pPciRoot->PciBus;
+    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
+    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
     /* Zero out everything */
-    memset(pPciRoot, 0, sizeof(*pPciRoot));
+    Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot)));
+    memset(pPciRoot, 0, sizeof(*pPciRoot)); /** @todo unnecessary as instance data is always set to zero by the allocator, see assertion above. */
+
     /* And fill values */
     if (!fUseIoApic)
@@ -3036 +3086 @@
                                 N_("Configuration error: Failed to read \"McfgLength\""));
 
-    pPciRoot->fUseIoApic = fUseIoApic;
-    pPciRoot->pDevInsR3 = pDevIns;
-    pPciRoot->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-
-    pPciRoot->PciBus.fTypePiix3  = false;
-    pPciRoot->PciBus.fTypeIch9   = true;
-    pPciRoot->PciBus.fPureBridge = false;
-    pPciRoot->PciBus.pDevInsR3 = pDevIns;
-    pPciRoot->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pPciRoot->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
+    pBusCC->pDevInsR3             = pDevIns;
+    pPciRoot->fUseIoApic          = fUseIoApic;
+    pPciRoot->PciBus.fTypePiix3   = false;
+    pPciRoot->PciBus.fTypeIch9    = true;
+    pPciRoot->PciBus.fPureBridge  = false;
     pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pPciRoot->PciBus.apDevices));
     AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
@@ -3053 +3097 @@
      * Register bus
      */
-    PDMPCIBUSREG PciBusReg;
-    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
-    PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
-    PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
-    PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
-    PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
-    PciBusReg.pfnSetIrqR3             = ich9pciSetIrq;
-    PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pciSetIrq" : NULL;
-    PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pciSetIrq" : NULL;
-    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.pfnRegisterR3              = pciR3MergedRegister;
+    PciBusReg.pfnRegisterMsiR3           = ich9pciRegisterMsi;
+    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
+    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
+    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
+    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
+    PciBusReg.pfnSetIrqR3                = ich9pciSetIrq;
+    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
+    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
     if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Failed to register ourselves as a PCI Bus"));
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
     Assert(pBus->iBus == 0);
-    if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
+    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
         return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
                                    N_("PCI helper version mismatch; got %#x expected %#x"),
-                                   pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
-
-    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
-    pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
+                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
 
     /*
@@ -3177 +3218 @@
  * @interface_method_impl{PDMDEVREG,pfnDestruct}
  */
-static DECLCALLBACK(int) ich9pciDestruct(PPDMDEVINS pDevIns)
+static DECLCALLBACK(int) ich9pciR3Destruct(PPDMDEVINS pDevIns)
 {
     PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
@@ -3189 +3230 @@
 
 
-void devpciR3ResetDevice(PPDMPCIDEV pDev)
+/**
+ * @param   pDevIns             The PCI bus device instance.
+ * @param   pDev                The PCI device to reset.
+ */
+void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev)
 {
     /* Clear regions */
@@ -3200 +3245 @@
                             == PCI_ADDRESS_SPACE_BAR64;
 
-        devpciR3UnmapRegion(pDev, iRegion);
+        devpciR3UnmapRegion(pDevIns, pDev, iRegion);
 
         if (f64Bit)
@@ -3213 +3258 @@
     else
     {
-        devpciR3SetWord(pDev, VBOX_PCI_COMMAND,
+        devpciR3SetWord(pDevIns, pDev, VBOX_PCI_COMMAND,
                           devpciR3GetWord(pDev, VBOX_PCI_COMMAND)
                         & ~(VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY |
@@ -3223 +3268 @@
         if (!pciDevIsPci2PciBridge(pDev))
         {
-            devpciR3SetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
-            devpciR3SetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
+            devpciR3SetByte(pDevIns, pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
+            devpciR3SetByte(pDevIns, pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
         }
 
         /* Reset MSI message control. */
         if (pciDevIsMsiCapable(pDev))
-        {
-            devpciR3SetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
+            devpciR3SetWord(pDevIns, pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
                             devpciR3GetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL) & 0xff8e);
-        }
 
         /* Reset MSI-X message control. */
         if (pciDevIsMsixCapable(pDev))
-        {
-            devpciR3SetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
+            devpciR3SetWord(pDevIns, pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
                             devpciR3GetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL) & 0x3fff);
-        }
     }
 }
@@ -3286 +3327 @@
     {
         if (pBus->apDevices[uDevFn])
-            devpciR3ResetDevice(pBus->apDevices[uDevFn]);
+            devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
     }
 
@@ -3299 +3340 @@
     if (pBus->iBus != 0)
     {
-        devpciR3SetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
-        devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
-        devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
+        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
+        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
+        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
         /* Not resetting the address decoders of the bridge to 0, since the
          * PCI-to-PCI Bridge spec says that there is no default value. */
@@ -3324 +3365 @@
 {
     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-
-    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
 
     /* Relocate RC pointers for the attached pci devices. */
@@ -3347 +3385 @@
 DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
 {
-    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-
     AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
     devpciR3BusRelocate(pDevIns, offDelta);
@@ -3368 +3403 @@
 }
 
+/**
+ * @interface_method_impl{PDMDEVREG,pfnDestruct}
+ */
+static DECLCALLBACK(int) ich9pcibridgeR3Destruct(PPDMDEVINS pDevIns)
+{
+    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    if (pBus->papBridgesR3)
+    {
+        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
+        pBus->papBridgesR3 = NULL;
+    }
+    return VINF_SUCCESS;
+}
+
 
 /**
  * @interface_method_impl{PDMDEVREG,pfnConstruct}
  */
-static DECLCALLBACK(int)   ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
-                                                  int        iInstance,
-                                                  PCFGMNODE  pCfg)
+static DECLCALLBACK(int) ich9pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
 {
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
@@ -3421 +3468 @@
      * Init data and register the PCI bus.
      */
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     pBus->fTypePiix3  = false;
     pBus->fTypeIch9   = true;
     pBus->fPureBridge = true;
-    pBus->pDevInsR3 = pDevIns;
-    pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
+    pBusCC->pDevInsR3 = pDevIns;
     /** @todo r=klaus figure out how to extend this to allow PCIe config space
      * extension, which increases the config space from 256 bytes to 4K. */
@@ -3433 +3479 @@
     AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
 
-    PDMPCIBUSREG PciBusReg;
-    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
-    PciBusReg.pfnRegisterR3           = pcibridgeR3MergedRegisterDevice;
-    PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
-    PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
-    PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
-    PciBusReg.pfnSetIrqR3             = ich9pcibridgeSetIrq;
-    PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
-    PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
-    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.pfnRegisterR3              = pcibridgeR3MergedRegisterDevice;
+    PciBusReg.pfnRegisterMsiR3           = ich9pciRegisterMsi;
+    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
+    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
+    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
+    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
+    PciBusReg.pfnSetIrqR3                = ich9pcibridgeSetIrq;
+    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
+    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
     if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Failed to register ourselves as a PCI Bus"));
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
     Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
-    if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
+    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
         return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
                                    N_("PCI helper version mismatch; got %#x expected %#x"),
-                                   pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
-
-    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
-    pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
+                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
+
     LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
 
@@ -3574 +3618 @@
 }
 
-/**
- * @interface_method_impl{PDMDEVREG,pfnDestruct}
- */
-static DECLCALLBACK(int) ich9pcibridgeDestruct(PPDMDEVINS pDevIns)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    if (pBus->papBridgesR3)
-    {
-        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
-        pBus->papBridgesR3 = NULL;
-    }
-    return VINF_SUCCESS;
-}
-
-#endif /* IN_RING3 */
+#else  /* !IN_RING3 */
+
+/**
+ * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
+ */
+DECLCALLBACK(int) ich9pciRZConstruct(PPDMDEVINS pDevIns)
+{
+    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.iBus          = pGlobals->PciBus.iBus;
+    PciBusReg.pfnSetIrq     = ich9pciSetIrq;
+    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
+    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
+    AssertRC(rc);
+
+    /* Disable default device locking. */
+    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
+
+    return rc;
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
+ */
+DECLCALLBACK(int) ich9pcibridgeRZConstruct(PPDMDEVINS pDevIns)
+{
+    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
+    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+
+    PDMPCIBUSREGCC PciBusReg;
+    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
+    PciBusReg.iBus          = pBus->iBus;
+    PciBusReg.pfnSetIrq     = ich9pcibridgeSetIrq;
+    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
+    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
+    AssertRC(rc);
+
+    /* Disable default device locking. */
+    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
+
+    return rc;
+}
+
+#endif /* !IN_RING3 */
 
 /**
@@ -3603 +3684 @@
     /* .uSharedVersion = */         42,
     /* .cbInstanceShared = */       sizeof(DEVPCIROOT),
-    /* .cbInstanceCC = */           0,
-    /* .cbInstanceRC = */           0,
+    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
+    /* .cbInstanceRC = */           sizeof(DEVPCIBUSRC),
     /* .cMaxPciDevices = */         1,
     /* .cMaxMsixVectors = */        0,
@@ -3611 +3692 @@
     /* .pszRCMod = */               "VBoxDDRC.rc",
     /* .pszR0Mod = */               "VBoxDDR0.r0",
-    /* .pfnConstruct = */           ich9pciConstruct,
-    /* .pfnDestruct = */            ich9pciDestruct,
+    /* .pfnConstruct = */           ich9pciR3Construct,
+    /* .pfnDestruct = */            ich9pciR3Destruct,
     /* .pfnRelocate = */            devpciR3RootRelocate,
     /* .pfnMemSetup = */            NULL,
@@ -3635 +3716 @@
 #elif defined(IN_RING0)
     /* .pfnEarlyConstruct = */      NULL,
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           ich9pciRZConstruct,
     /* .pfnDestruct = */            NULL,
     /* .pfnFinalDestruct = */       NULL,
@@ -3648 +3729 @@
     /* .pfnReserved7 = */           NULL,
 #elif defined(IN_RC)
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           ich9pciRZConstruct,
     /* .pfnReserved0 = */           NULL,
     /* .pfnReserved1 = */           NULL,
@@ -3677 +3758 @@
     /* .uSharedVersion = */         42,
     /* .cbInstanceShared = */       sizeof(DEVPCIBUS),
-    /* .cbInstanceCC = */           0,
+    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
     /* .cbInstanceRC = */           0,
     /* .cMaxPciDevices = */         1,
@@ -3685 +3766 @@
     /* .pszRCMod = */               "VBoxDDRC.rc",
     /* .pszR0Mod = */               "VBoxDDR0.r0",
-    /* .pfnConstruct = */           ich9pcibridgeConstruct,
-    /* .pfnDestruct = */            ich9pcibridgeDestruct,
+    /* .pfnConstruct = */           ich9pcibridgeR3Construct,
+    /* .pfnDestruct = */            ich9pcibridgeR3Destruct,
     /* .pfnRelocate = */            devpciR3BusRelocate,
     /* .pfnMemSetup = */            NULL,
@@ -3709 +3790 @@
 #elif defined(IN_RING0)
     /* .pfnEarlyConstruct = */      NULL,
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           ich9pcibridgeRZConstruct,
     /* .pfnDestruct = */            NULL,
     /* .pfnFinalDestruct = */       NULL,
@@ -3722 +3803 @@
     /* .pfnReserved7 = */           NULL,
 #elif defined(IN_RC)
-    /* .pfnConstruct = */           NULL,
+    /* .pfnConstruct = */           ich9pcibridgeRZConstruct,
     /* .pfnReserved0 = */           NULL,
     /* .pfnReserved1 = */           NULL,

trunk/src/VBox/Devices/Bus/DevPciInternal.h

@@ -29 +29 @@
 
 /**
- * PCI bus instance (common to both).
+ * PCI bus shared instance data (common to both PCI buses).
  */
 typedef struct DEVPCIBUS
@@ -42 +42 @@
     uint32_t                fTypePiix3 : 1;
     /** Set if ICH9 type. */
-    uint32_t                fTypeIch9: 1;
+    uint32_t                fTypeIch9 : 1;
     /** Set if this is a pure bridge, i.e. not part of DEVPCIGLOBALS struct. */
     uint32_t                fPureBridge : 1;
@@ -48 +48 @@
     uint32_t                uReservedConfigFlags : 29;
 
+    /** Array of bridges attached to the bus. */
+    R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
+    /** Cache line align apDevices. */
+    uint32_t                au32Alignment1[HC_ARCH_BITS == 32 ? 3+8 : 2+8];
+    /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
+    R3PTRTYPE(PPDMPCIDEV)   apDevices[256];
+
+    /** The PCI device for the PCI bridge. */
+    PDMPCIDEV               PciDev;
+} DEVPCIBUS;
+/** Pointer to PCI bus shared instance data. */
+typedef DEVPCIBUS *PDEVPCIBUS;
+
+/**
+ * PCI bus ring-3 instance data (common to both PCI buses).
+ */
+typedef struct DEVPCIBUSR3
+{
     /** R3 pointer to the device instance. */
     PPDMDEVINSR3            pDevInsR3;
     /** Pointer to the PCI R3  helpers. */
     PCPDMPCIHLPR3           pPciHlpR3;
-
+} DEVPCIBUSR3;
+/** Pointer to PCI bus ring-3 instance data. */
+typedef DEVPCIBUSR3 *PDEVPCIBUSR3;
+
+/**
+ * PCI bus ring-0 instance data (common to both PCI buses).
+ */
+typedef struct DEVPCIBUSR0
+{
     /** R0 pointer to the device instance. */
     PPDMDEVINSR0            pDevInsR0;
     /** Pointer to the PCI R0 helpers. */
     PCPDMPCIHLPR0           pPciHlpR0;
-
-    /** RC pointer to the device instance. */
+} DEVPCIBUSR0;
+/** Pointer to PCI bus ring-0 instance data. */
+typedef DEVPCIBUSR0 *PDEVPCIBUSR0;
+
+/**
+ * PCI bus raw-mode instance data (common to both PCI buses).
+ */
+typedef struct DEVPCIBUSRC
+{
+    /** R0 pointer to the device instance. */
     PPDMDEVINSRC            pDevInsRC;
-    /** Pointer to the PCI RC helpers. */
+    /** Pointer to the PCI raw-mode helpers. */
     PCPDMPCIHLPRC           pPciHlpRC;
-
-    /** Array of bridges attached to the bus. */
-    R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
-#if HC_ARCH_BITS == 32
-    uint32_t                au32Alignment1[5]; /**< Cache line align apDevices. */
-#endif
-    /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
-    R3PTRTYPE(PPDMPCIDEV)   apDevices[256];
-
-    /** The PCI device for the PCI bridge. */
-    PDMPCIDEV               PciDev;
-} DEVPCIBUS;
-/** Pointer to a PCI bus instance.   */
-typedef DEVPCIBUS *PDEVPCIBUS;
+} DEVPCIBUSRC;
+/** Pointer to PCI bus raw-mode instance data. */
+typedef DEVPCIBUSRC *PDEVPCIBUSRC;
+
+/** DEVPCIBUSR3, DEVPCIBUSR0 or DEVPCIBUSRC depending on context.  */
+typedef CTX_SUFF(DEVPCIBUS)  DEVPCIBUSCC;
+/** PDEVPCIBUSR3, PDEVPCIBUSR0 or PDEVPCIBUSRC depending on context.  */
+typedef CTX_SUFF(PDEVPCIBUS) PDEVPCIBUSCC;
 
 
@@ -99 +127 @@
 
 /**
- * PCI Globals - This is the host-to-pci bridge and the root bus.
+ * PCI Globals - This is the host-to-pci bridge and the root bus, shared data.
  *
  * @note Only used by the root bus, not the bridges.
@@ -109 +137 @@
     DEVPCIBUS           PciBus;
 
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-
     /** I/O APIC usage flag (always true of ICH9, see constructor). */
     bool                fUseIoApic;
     /** Reserved for future config flags. */
-    bool                afFutureFlags[3];
+    bool                afFutureFlags[3+4];
     /** Physical address of PCI config space MMIO region. */
     uint64_t            u64PciConfigMMioAddress;
@@ -163 +184 @@
 /** Pointer to PCI device globals. */
 typedef DEVPCIROOT *PDEVPCIROOT;
-
-
 /** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
 #define DEVINS_2_DEVPCIBUS(pDevIns)     (&PDMINS_2_DATA(pDevIns, PDEVPCIROOT)->PciBus)
@@ -176 +195 @@
 #define PCI_LOCK(pDevIns, rc) \
     do { \
-        int rc2 = DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
+        int rc2 = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
         if (rc2 != VINF_SUCCESS) \
             return rc2; \
     } while (0)
 #define PCI_UNLOCK(pDevIns) \
-    DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
+    PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
 
 
@@ -192 +211 @@
 DECLCALLBACK(int)  devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
                                                   PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback);
-DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
-                                                    PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
-                                                    PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld);
-DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb);
-DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
-                                                            uint32_t uAddress, uint32_t u32Value, unsigned cb);
-void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
+DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                         PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite);
+DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                    uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
+DECLHIDDEN(VBOXSTRICTRC)   devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
+DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
+                                                     uint32_t uAddress, unsigned cb, uint32_t u32Value);
+DECLHIDDEN(VBOXSTRICTRC)   devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
+                                                           PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value);
+void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
 int  devpciR3CommonRestoreRegions(PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState);
-void devpciR3ResetDevice(PPDMPCIDEV pDev);
-void devpciR3BiosInitSetRegionAddress(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
+void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev);
+void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
 uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb);
-void devpciR3SetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
+void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
 
 DECLINLINE(uint8_t) devpciR3GetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
@@ -220 +242 @@
 }
 
-DECLINLINE(void) devpciR3SetByte(PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
-{
-    devpciR3SetCfg(pPciDev, iRegister, u8, 1);
-}
-
-DECLINLINE(void) devpciR3SetWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
-{
-    devpciR3SetCfg(pPciDev, iRegister, u16, 2);
-}
-
-DECLINLINE(void) devpciR3SetDWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
-{
-    devpciR3SetCfg(pPciDev, iRegister, u32, 4);
+DECLINLINE(void) devpciR3SetByte(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
+{
+    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u8, 1);
+}
+
+DECLINLINE(void) devpciR3SetWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
+{
+    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u16, 2);
+}
+
+DECLINLINE(void) devpciR3SetDWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
+{
+    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u32, 4);
 }
 

trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h

@@ -60 +60 @@
  *                          function number (0-7).
  * @param   pszName         Device name (static but not unique).
- * @param   pfnConfigRead   The default config read method.
- * @param   pfnConfigWrite  The default config read method.
  *
  * @remarks Caller enters the PDM critical section.
  */
 static int pciR3MergedRegisterDeviceOnBus(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint32_t fFlags,
-                                          uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName,
-                                          PFNPCICONFIGREAD pfnConfigRead, PFNPCICONFIGWRITE pfnConfigWrite)
+                                          uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
 {
     /*
@@ -197 +194 @@
     pPciDev->Int.s.pBusR0           = PDMINS_2_DATA_R0PTR(pDevIns);
     pPciDev->Int.s.pBusRC           = PDMINS_2_DATA_RCPTR(pDevIns);
-    pPciDev->Int.s.pfnConfigRead    = pfnConfigRead;
-    pPciDev->Int.s.pfnConfigWrite   = pfnConfigWrite;
+    pPciDev->Int.s.pfnConfigRead    = NULL;
+    pPciDev->Int.s.pfnConfigWrite   = NULL;
 
     /* Remember and mark bridges. */
@@ -225 +222 @@
     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
-    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
-                                          devpciR3CommonDefaultConfigRead, devpciR3CommonDefaultConfigWrite);
+    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
 }
 
@@ -237 +233 @@
 {
     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
-                                          devpciR3CommonDefaultConfigRead, devpciR3CommonDefaultConfigWrite);
-}
-
+    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
+}
+

trunk/src/VBox/Devices/Bus/MsiCommon.cpp

@@ -33 +33 @@
     uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
 #ifdef IN_RING3
-    if (pciDevIsPassthrough(pDev))
-        return pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2);
+    if (pciDevIsPassthrough(pDev) && pDev->Int.s.pfnConfigRead)
+    {
+        uint32_t u32Value = 0;
+        VBOXSTRICTRC rcStrict = pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2, &u32Value);
+        AssertRCSuccess(rcStrict);
+        return (uint16_t)u32Value;
+    }
 #endif
     return PCIDevGetWord(pDev, idxMessageControl);