VirtualBox

Changeset 80943 in vbox


Ignore:
Timestamp:
Sep 23, 2019 9:36:14 AM (6 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
133523
Message:

Devices/PCI: Device model refactoring, part I. bugref:9218

Location:
trunk
Files:
20 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/err.h

    r80845 r80943  
    14361436 * terminated all VMs and upgraded any extension packs.  If this error
    14371437 * persists, try re-installing VirtualBox. */
    1438 #define VERR_PDM_DEVHLPR3_VERSION_MISMATCH          (-2871)
     1438#define VERR_PDM_DEVHLP_VERSION_MISMATCH            (-2871)
    14391439/** The USB device instance structure version has changed.
    14401440 *
    … …  
    15231523/** The I/O request is in an invalid state for this operation. */
    15241524#define VERR_PDM_MEDIAEX_IOREQ_INVALID_STATE        (-2899)
     1525
     1526/** Returned by PCI config space callbacks to indicate taking default action. */
     1527#define VINF_PDM_PCI_DO_DEFAULT                     (7200)
    15251528/** @} */
    15261529

  • trunk/include/VBox/vmm/gvm.h

    r80641 r80943  
    202202        struct PDMR0PERVM   s;
    203203#endif
    204         uint8_t             padding[1536];
     204        uint8_t             padding[1792];
    205205    } pdmr0;
    206206
    … …  
    215215    /** Padding so aCpus starts on a page boundrary.  */
    216216#ifdef VBOX_WITH_NEM_R0
    217     uint8_t         abPadding2[4096 - 64 - 256 - 512 - 256 - 64 - 1536 - 256 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
    218 #else
    219     uint8_t         abPadding2[4096 - 64 - 256 - 512       - 64 - 1536 - 256 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
     217    uint8_t         abPadding2[4096 - 64 - 256 - 512 - 256 - 64 - 1792 - 256 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
     218#else
     219    uint8_t         abPadding2[4096 - 64 - 256 - 512       - 64 - 1792 - 256 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
    220220#endif
    221221

  • trunk/include/VBox/vmm/pdmdev.h

    r80722 r80943  
    806806 * All the callbacks, except the PCIBIOS hack, are working on PCI devices.
    807807 */
    808 typedef struct PDMPCIBUSREG
    809 {
    810     /** Structure version number. PDM_PCIBUSREG_VERSION defines the current version. */
     808typedef struct PDMPCIBUSREGR3
     809{
     810    /** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
    811811    uint32_t            u32Version;
    812812
    … …  
    868868
    869869    /**
    870      * Register PCI configuration space read/write callbacks.
     870     * Register PCI configuration space read/write intercept callbacks.
    871871     *
    872872     * @param   pDevIns         Device instance of the PCI Bus.
    873873     * @param   pPciDev         The PCI device structure.
    874874     * @param   pfnRead         Pointer to the user defined PCI config read function.
    875      * @param   ppfnReadOld     Pointer to function pointer which will receive the old (default)
    876      *                          PCI config read function. This way, user can decide when (and if)
    877      *                          to call default PCI config read function. Can be NULL.
    878875     * @param   pfnWrite        Pointer to the user defined PCI config write function.
    879      * @param   ppfnWriteOld    Pointer to function pointer which will receive the old (default)
    880      *                          PCI config write function. This way, user can decide when (and if)
    881876     *                          to call default PCI config write function. Can be NULL.
    882877     * @remarks Caller enters the PDM critical section.
    883878     * @thread  EMT
    884879     */
    885     DECLR3CALLBACKMEMBER(void, pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    886                                                         PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    887                                                         PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
     880    DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     881                                                           PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
     882
     883    /**
     884     * Perform a PCI configuration space write, bypassing interception.
     885     *
     886     * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
     887     *
     888     * @returns Strict VBox status code (mainly DBGFSTOP).
     889     * @param   pDevIns         Device instance of the PCI Bus.
     890     * @param   pPciDev         The PCI device which config space is being read.
     891     * @param   uAddress        The config space address.
     892     * @param   cb              The size of the read: 1, 2 or 4 bytes.
     893     * @param   u32Value        The value to write.
     894     * @note    The caller (PDM) does not enter the PDM critsect, but it is possible
     895     *          that the (root) bus will have done that already.
     896     */
     897    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     898                                                       uint32_t uAddress, unsigned cb, uint32_t u32Value));
     899
     900    /**
     901     * Perform a PCI configuration space read, bypassing interception.
     902     *
     903     * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
     904     *
     905     * @returns Strict VBox status code (mainly DBGFSTOP).
     906     * @param   pDevIns         Device instance of the PCI Bus.
     907     * @param   pPciDev         The PCI device which config space is being read.
     908     * @param   uAddress        The config space address.
     909     * @param   cb              The size of the read: 1, 2 or 4 bytes.
     910     * @param   pu32Value       Where to return the value.
     911     * @note    The caller (PDM) does not enter the PDM critsect, but it is possible
     912     *          that the (root) bus will have done that already.
     913     */
     914    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     915                                                      uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
    888916
    889917    /**
    … …  
    899927    DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
    900928
    901     /** The name of the SetIrq RC entry point. */
    902     const char         *pszSetIrqRC;
    903 
    904     /** The name of the SetIrq R0 entry point. */
    905     const char         *pszSetIrqR0;
    906 
    907 } PDMPCIBUSREG;
     929    /** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
     930    uint32_t            u32EndVersion;
     931} PDMPCIBUSREGR3;
    908932/** Pointer to a PCI bus registration structure. */
    909 typedef PDMPCIBUSREG *PPDMPCIBUSREG;
    910 
    911 /** Current PDMPCIBUSREG version number. */
    912 #define PDM_PCIBUSREG_VERSION                   PDM_VERSION_MAKE(0xfffe, 7, 0)
     933typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
     934/** Current PDMPCIBUSREGR3 version number. */
     935#define PDM_PCIBUSREGR3_VERSION                 PDM_VERSION_MAKE(0xff86, 1, 0)
     936
     937/**
     938 * PCI Bus registration structure for ring-0.
     939 */
     940typedef struct PDMPCIBUSREGR0
     941{
     942    /** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
     943    uint32_t            u32Version;
     944    /** The PCI bus number (from ring-3 registration). */
     945    uint32_t            iBus;
     946    /**
     947     * Set the IRQ for a PCI device.
     948     *
     949     * @param   pDevIns         Device instance of the PCI Bus.
     950     * @param   pPciDev         The PCI device structure.
     951     * @param   iIrq            IRQ number to set.
     952     * @param   iLevel          IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
     953     * @param   uTagSrc         The IRQ tag and source (for tracing).
     954     * @remarks Caller enters the PDM critical section.
     955     */
     956    DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     957    /** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
     958    uint32_t            u32EndVersion;
     959} PDMPCIBUSREGR0;
     960/** Pointer to a PCI bus ring-0 registration structure. */
     961typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
     962/** Current PDMPCIBUSREGR0 version number. */
     963#define PDM_PCIBUSREGR0_VERSION                  PDM_VERSION_MAKE(0xff87, 1, 0)
     964
     965/**
     966 * PCI Bus registration structure for raw-mode.
     967 */
     968typedef struct PDMPCIBUSREGRC
     969{
     970    /** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
     971    uint32_t            u32Version;
     972    /** The PCI bus number (from ring-3 registration). */
     973    uint32_t            iBus;
     974    /**
     975     * Set the IRQ for a PCI device.
     976     *
     977     * @param   pDevIns         Device instance of the PCI Bus.
     978     * @param   pPciDev         The PCI device structure.
     979     * @param   iIrq            IRQ number to set.
     980     * @param   iLevel          IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
     981     * @param   uTagSrc         The IRQ tag and source (for tracing).
     982     * @remarks Caller enters the PDM critical section.
     983     */
     984    DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     985    /** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
     986    uint32_t            u32EndVersion;
     987} PDMPCIBUSREGRC;
     988/** Pointer to a PCI bus raw-mode registration structure. */
     989typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
     990/** Current PDMPCIBUSREGRC version number. */
     991#define PDM_PCIBUSREGRC_VERSION                  PDM_VERSION_MAKE(0xff88, 1, 0)
     992
     993/** PCI bus registration structure for the current context. */
     994typedef CTX_SUFF(PDMPCIBUSREG)  PDMPCIBUSREGCC;
     995/** Pointer to a PCI bus registration structure for the current context. */
     996typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
     997/** PCI bus registration structure version for the current context. */
     998#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
     999
    9131000
    9141001/**
    … …  
    33743461     * Register PCI configuration space read/write callbacks.
    33753462     *
     3463     * @returns VBox status code.
    33763464     * @param   pDevIns             The device instance.
    33773465     * @param   pPciDev             The PCI device structure.  If NULL the default
    33783466     *                              PCI device for this device instance is used.
    33793467     * @param   pfnRead             Pointer to the user defined PCI config read function.
    3380      * @param   ppfnReadOld         Pointer to function pointer which will receive the old (default)
    3381      *                              PCI config read function. This way, user can decide when (and if)
    33823468     *                              to call default PCI config read function. Can be NULL.
    33833469     * @param   pfnWrite            Pointer to the user defined PCI config write function.
    3384      * @param   ppfnWriteOld        Pointer to function pointer which will receive
    3385      *                              the old (default) PCI config write function.
    3386      *                              This way, user can decide when (and if) to call
    3387      *                              default PCI config write function. Can be NULL.
    33883470     * @remarks The callbacks will be invoked holding the PDM lock. The device lock
    33893471     *          is NOT take because that is very likely be a lock order violation.
    3390      * @thread  EMT
    3391      */
    3392     DECLR3CALLBACKMEMBER(void, pfnPCISetConfigCallbacks,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    3393                                                          PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    3394                                                          PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
     3472     * @thread  EMT(0)
     3473     * @note    Only callable during VM creation.
     3474     * @sa      PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
     3475     */
     3476    DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     3477                                                             PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
     3478
     3479    /**
     3480     * Perform a PCI configuration space write.
     3481     *
     3482     * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
     3483     *
     3484     * @returns Strict VBox status code (mainly DBGFSTOP).
     3485     * @param   pDevIns             The device instance.
     3486     * @param   pPciDev             The PCI device which config space is being read.
     3487     * @param   uAddress            The config space address.
     3488     * @param   cb                  The size of the read: 1, 2 or 4 bytes.
     3489     * @param   u32Value            The value to write.
     3490     */
     3491    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     3492                                                          uint32_t uAddress, unsigned cb, uint32_t u32Value));
     3493
     3494    /**
     3495     * Perform a PCI configuration space read.
     3496     *
     3497     * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
     3498     *
     3499     * @returns Strict VBox status code (mainly DBGFSTOP).
     3500     * @param   pDevIns             The device instance.
     3501     * @param   pPciDev             The PCI device which config space is being read.
     3502     * @param   uAddress            The config space address.
     3503     * @param   cb                  The size of the read: 1, 2 or 4 bytes.
     3504     * @param   pu32Value           Where to return the value.
     3505     */
     3506    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     3507                                                         uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
    33953508
    33963509    /**
    … …  
    36713784     * @param   piBus               Where to return the PDM bus number. Optional.
    36723785     */
    3673     DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg,
    3674                                                  PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus));
     3786    DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
     3787                                                 PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus));
    36753788
    36763789    /**
    … …  
    45784691     */
    45794692    DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
     4693
     4694    /**
     4695     * Sets up the PCI bus for the raw-mode context.
     4696     *
     4697     * This must be called after ring-3 has registered the PCI bus using
     4698     * PDMDevHlpPCIBusRegister().
     4699     *
     4700     * @returns VBox status code.
     4701     * @param   pDevIns     The device instance.
     4702     * @param   pPciBusReg  The PCI bus registration information for raw-mode,
     4703     *                      considered volatile.
     4704     * @param   ppPciHlp    Where to return the raw-mode PCI bus helpers.
     4705     */
     4706    DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
    45804707
    45814708    /** Space reserved for future members.
    … …  
    49515078    DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
    49525079
     5080    /**
     5081     * Sets up the PCI bus for the ring-0 context.
     5082     *
     5083     * This must be called after ring-3 has registered the PCI bus using
     5084     * PDMDevHlpPCIBusRegister().
     5085     *
     5086     * @returns VBox status code.
     5087     * @param   pDevIns     The device instance.
     5088     * @param   pPciBusReg  The PCI bus registration information for ring-0,
     5089     *                      considered volatile.
     5090     * @param   ppPciHlp    Where to return the ring-0 PCI bus helpers.
     5091     */
     5092    DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
     5093
    49535094    /** Space reserved for future members.
    49545095     * @{ */
    … …  
    52245365                              ("DevIns=%#x  mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
    52255366                              VERR_PDM_DEVINS_VERSION_MISMATCH); \
    5226         AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->pHlpR3->u32Version, PDM_DEVHLPR3_VERSION), \
    5227                               ("DevHlp=%#x  mine=%#x\n", (pDevIns)->pHlpR3->u32Version, PDM_DEVHLPR3_VERSION), \
    5228                               VERR_PDM_DEVHLPR3_VERSION_MISMATCH); \
     5367        AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
     5368                              ("DevHlp=%#x  mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
     5369                              VERR_PDM_DEVHLP_VERSION_MISMATCH); \
    52295370    } while (0)
    52305371
    … …  
    52435384        if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
    52445385        { /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
    5245         if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->pHlpR3->u32Version, PDM_DEVHLPR3_VERSION) )) \
    5246         { /* likely */ } else return VERR_PDM_DEVHLPR3_VERSION_MISMATCH; \
     5386        if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
     5387        { /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
    52475388    } while (0)
    52485389
    … …  
    63106451
    63116452/**
    6312  * @copydoc PDMDEVHLPR3::pfnPCISetConfigCallbacks
    6313  */
    6314 DECLINLINE(void) PDMDevHlpPCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    6315                                                 PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    6316                                                 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
    6317 {
    6318     pDevIns->pHlpR3->pfnPCISetConfigCallbacks(pDevIns, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
     6453 * @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
     6454 */
     6455DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     6456                                                    PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
     6457{
     6458    return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
     6459}
     6460
     6461/**
     6462 * @copydoc PDMDEVHLPR3::pfnPCIConfigRead
     6463 */
     6464DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
     6465                                                unsigned cb, uint32_t *pu32Value)
     6466{
     6467    return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
     6468}
     6469
     6470/**
     6471 * @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
     6472 */
     6473DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
     6474                                                 unsigned cb, uint32_t u32Value)
     6475{
     6476    return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
    63196477}
    63206478
    … …  
    66646822 * @copydoc PDMDEVHLPR3::pfnPCIBusRegister
    66656823 */
    6666 DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus)
    6667 {
    6668     return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlpR3, piBus);
     6824DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
     6825{
     6826    return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
    66696827}
    66706828
    … …  
    68136971}
    68146972
    6815 #endif /* IN_RING3 */
     6973#else  /* !IN_RING3 */
     6974
     6975/**
     6976 * @copydoc PDMDEVHLPR0::pfnPCIBusSetUp
     6977 */
     6978DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
     6979{
     6980    return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
     6981}
     6982
     6983#endif /* !IN_RING3 */
    68166984
    68176985/**

  • trunk/include/VBox/vmm/pdmpcidev.h

    r77299 r80943  
    4040
    4141/**
    42  * Callback function for reading from the PCI configuration space.
    43  *
    44  * @returns The register value.
     42 * Callback function for intercept reading from the PCI configuration space.
     43 *
     44 * @returns VINF_SUCCESS or PDMDevHlpDBGFStop status (maybe others later).
     45 * @retval  VINF_PDM_PCI_DO_DEFAULT to do default read (same as calling
     46 *          PDMDevHlpPCIConfigRead()).
     47 *
    4548 * @param   pDevIns         Pointer to the device instance the PCI device
    4649 *                          belongs to.
    … …  
    4851 * @param   uAddress        The configuration space register address. [0..4096]
    4952 * @param   cb              The register size. [1,2,4]
     53 * @param   pu32Value       Where to return the register value.
    5054 *
    5155 * @remarks Called with the PDM lock held.  The device lock is NOT take because
    5256 *          that is very likely be a lock order violation.
    5357 */
    54 typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb);
     58typedef DECLCALLBACK(VBOXSTRICTRC) FNPCICONFIGREAD(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     59                                                   uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
    5560/** Pointer to a FNPCICONFIGREAD() function. */
    5661typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
    … …  
    6166 * Callback function for writing to the PCI configuration space.
    6267 *
    63  * @returns VINF_SUCCESS or PDMDevHlpDBGFStop status.
     68 * @returns VINF_SUCCESS or PDMDevHlpDBGFStop status (maybe others later).
     69 * @retval  VINF_PDM_PCI_DO_DEFAULT to do default read (same as calling
     70 *          PDMDevHlpPCIConfigWrite()).
    6471 *
    6572 * @param   pDevIns         Pointer to the device instance the PCI device
    … …  
    6774 * @param   pPciDev         Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
    6875 * @param   uAddress        The configuration space register address. [0..4096]
     76 * @param   cb              The register size. [1,2,4]
    6977 * @param   u32Value        The value that's being written. The number of bits actually used from
    7078 *                          this value is determined by the cb parameter.
    71  * @param   cb              The register size. [1,2,4]
    7279 *
    7380 * @remarks Called with the PDM lock held.  The device lock is NOT take because
    … …  
    7582 */
    7683typedef DECLCALLBACK(VBOXSTRICTRC) FNPCICONFIGWRITE(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    77                                                     uint32_t uAddress, uint32_t u32Value, unsigned cb);
     84                                                    uint32_t uAddress, unsigned cb, uint32_t u32Value);
    7885/** Pointer to a FNPCICONFIGWRITE() function. */
    7986typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;

  • trunk/include/VBox/vmm/pdmpcidevint.h

    r80722 r80943  
    6363 * Callback function for reading from the PCI configuration space.
    6464 *
    65  * @returns The register value.
     65 * @returns Strict VBox status code.
    6666 * @param   pDevIns         Pointer to the device instance of the PCI bus.
    6767 * @param   iBus            The bus number this device is on.
    … …  
    6969 * @param   u32Address      The configuration space register address. [0..255]
    7070 * @param   cb              The register size. [1,2,4]
    71  */
    72 typedef DECLCALLBACK(uint32_t) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb);
     71 * @param   pu32Value       Where to return the register value.
     72 */
     73typedef DECLCALLBACK(VBOXSTRICTRC) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
     74                                                         uint32_t u32Address, unsigned cb, uint32_t *pu32Value);
    7375/** Pointer to a FNPCICONFIGREAD() function. */
    7476typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
    … …  
    7981 * Callback function for writing to the PCI configuration space.
    8082 *
     83 * @returns Strict VBox status code.
    8184 * @param   pDevIns         Pointer to the device instance of the PCI bus.
    8285 * @param   iBus            The bus number this device is on.
    8386 * @param   iDevice         The number of the device on the bus.
    8487 * @param   u32Address      The configuration space register address. [0..255]
     88 * @param   cb              The register size. [1,2,4]
    8589 * @param   u32Value        The value that's being written. The number of bits actually used from
    8690 *                          this value is determined by the cb parameter.
    87  * @param   cb              The register size. [1,2,4]
    88  */
    89 typedef DECLCALLBACK(void) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb);
     91 */
     92typedef DECLCALLBACK(VBOXSTRICTRC) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
     93                                                          uint32_t u32Address, unsigned cb, uint32_t u32Value);
    9094/** Pointer to a FNPCICONFIGWRITE() function. */
    9195typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r80854 r80943  
    8484RT_C_DECLS_BEGIN
    8585
    86 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
    87 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
     86static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
    8887PDMBOTHCBDECL(int)  pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    8988PDMBOTHCBDECL(int)  pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
    … …  
    111110
    112111
    113 static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
    114 {
    115     uint8_t iBus, iDevice;
    116     uint32_t config_addr;
    117 
    118     LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
    119 
    120     if (!(pGlobals->uConfigReg & (1 << 31))) {
     112static int pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
     113{
     114    LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
     115
     116    if (!(pGlobals->uConfigReg & (1 << 31)))
    121117        return VINF_SUCCESS;
    122     }
    123     if ((pGlobals->uConfigReg & 0x3) != 0) {
     118    if ((pGlobals->uConfigReg & 0x3) != 0)
    124119        return VINF_SUCCESS;
    125     }
    126     iBus = (pGlobals->uConfigReg >> 16) & 0xff;
    127     iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
    128     config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
     120
     121    uint8_t  const iBus        = (pGlobals->uConfigReg >> 16) & 0xff;
     122    uint8_t  const iDevice     = (pGlobals->uConfigReg >>  8) & 0xff;
     123#ifdef IN_RING3
     124    uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
     125#endif
    129126    RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
     127
     128    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    130129    if (iBus != 0)
    131130    {
    … …  
    137136            {
    138137                AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
    139                 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
     138                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
     139                                                                     iDevice, config_addr, cb, u32Value);
    140140            }
    141141#else
    142             RT_NOREF2(val, len);
    143             return VINF_IOM_R3_IOPORT_WRITE;
     142            RT_NOREF(pDevIns, addr, u32Value, cb);
     143            rcStrict = VINF_IOM_R3_IOPORT_WRITE;
    144144#endif
    145145        }
    … …  
    147147    else
    148148    {
    149         R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
    150         if (pci_dev)
     149        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
     150        if (pPciDev)
    151151        {
    152152#ifdef IN_RING3
    153             LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
    154             return VBOXSTRICTRC_TODO(pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len));
     153            LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
     154            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     155            if (pPciDev->Int.s.pfnConfigWrite)
     156                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
     157            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     158                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     159                                                           pPciDev, config_addr, cb, u32Value);
    155160#else
    156             return VINF_IOM_R3_IOPORT_WRITE;
     161            rcStrict = VINF_IOM_R3_IOPORT_WRITE;
    157162#endif
    158163        }
    159164    }
    160     return VINF_SUCCESS;
    161 }
    162 
    163 static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
    164 {
    165     uint8_t iBus, iDevice;
    166     uint32_t config_addr;
    167 
    168     *pu32 = 0xffffffff;
     165    return rcStrict;
     166}
     167
     168static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
     169{
     170    *pu32Value = UINT32_MAX;
    169171
    170172    if (!(pGlobals->uConfigReg & (1 << 31)))
    … …  
    172174    if ((pGlobals->uConfigReg & 0x3) != 0)
    173175        return VINF_SUCCESS;
    174     iBus = (pGlobals->uConfigReg >> 16) & 0xff;
    175     iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
    176     config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
     176    uint8_t const  iBus        = (pGlobals->uConfigReg >> 16) & 0xff;
     177    uint8_t const  iDevice     = (pGlobals->uConfigReg >>  8) & 0xff;
     178#ifdef IN_RING3
     179    uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
     180#endif
    177181    RT_UNTRUSTED_VALIDATED_FENCE();
     182
     183    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    178184    if (iBus != 0)
    179185    {
    … …  
    185191            {
    186192                AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
    187                 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
     193                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
     194                                                                    iBus, iDevice, config_addr, cb, pu32Value);
    188195            }
    189196#else
    190             NOREF(len);
    191             return VINF_IOM_R3_IOPORT_READ;
     197            RT_NOREF(addr, cb);
     198            rcStrict = VINF_IOM_R3_IOPORT_READ;
    192199#endif
    193200        }
    … …  
    195202    else
    196203    {
    197         R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
    198         if (pci_dev)
     204        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
     205        if (pPciDev)
    199206        {
    200207#ifdef IN_RING3
    201             *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
    202             LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
     208            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     209            if (pPciDev->Int.s.pfnConfigRead)
     210                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
     211            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     212                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
     213            LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
    203214#else
    204             NOREF(len);
    205             return VINF_IOM_R3_IOPORT_READ;
     215            NOREF(cb);
     216            rcStrict = VINF_IOM_R3_IOPORT_READ;
    206217#endif
    207218        }
    208219    }
    209220
    210     return VINF_SUCCESS;
     221    return rcStrict;
    211222}
    212223
    … …  
    234245}
    235246
    236 static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
     247static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
     248                         uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
    237249{
    238250    /* This is only allowed to be called with a pointer to the host bus. */
    … …  
    253265        Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
    254266              R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
    255         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
     267        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
    256268
    257269        if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
    … …  
    261273            Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
    262274                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
    263             pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
     275            pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
    264276        }
    265277    } else {
    266278        Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
    267279              R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
    268         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
     280        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iAcpiIrq, iLevel, uTagSrc);
    269281    }
    270282}
    … …  
    278290 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
    279291 *
    280  * @param   pGlobals        Device instance of the host PCI Bus.
     292 * @param   pPdmDev         The PDM device instance for the PCI bus.
     293 * @param   pGlobals        Device instance of the host PCI bus.
     294 * @param   pBusCC          Context specific data for the PCI bus.
    281295 * @param   uDevFn          The device number on the host bus which will raise the IRQ
    282296 * @param   pPciDev         The PCI device structure which raised the interrupt.
    … …  
    288302 *          is needed to calculate the PIRQ value.
    289303 */
    290 static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     304static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
     305                              uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    291306{
    292307    PDEVPCIBUS  pBus = &pGlobals->PciBus;
    … …  
    316331                 * PCI device configuration space).
    317332                 */
    318                 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
     333                apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
    319334            else
    320                 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
     335                apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
    321336            return;
    322337        }
    … …  
    368383        Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
    369384              R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
    370         pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
     385        pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
    371386
    372387        /** @todo optimize pci irq flip-flop some rainy day. */
    373388        if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
    374             pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
     389            pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
    375390    }
    376391}
    … …  
    380395 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
    381396 */
    382 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    383 {
    384     pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
     397static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     398{
     399    PDEVPCIROOT  pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     400    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     401    LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
     402    pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
    385403}
    386404
    … …  
    454472static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 };   /* bird: added const */
    455473
    456 static void pci_bios_init_device(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
     474static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
     475                                 PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
    457476{
    458477    uint32_t *paddr;
    … …  
    474493                {
    475494                    /* PIIX3, PIIX4 or ICH6 IDE */
    476                     devpciR3SetWord(pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
    477                     devpciR3SetWord(pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing  */
     495                    devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
     496                    devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing  */
    478497                    goto default_map;
    479498                }
    … …  
    481500                {
    482501                    /* IDE: we map it as in ISA mode */
    483                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x1f0);
    484                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 1, 0x3f4);
    485                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 2, 0x170);
    486                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 3, 0x374);
    487                     devpciR3SetWord(pPciDev, PCI_COMMAND,
     502                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
     503                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
     504                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
     505                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
     506                    devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
    488507                                      devpciR3GetWord(pPciDev, PCI_COMMAND)
    489508                                    | PCI_COMMAND_IOACCESS);
    … …  
    495514                    goto default_map;
    496515                /* VGA: map frame buffer to default Bochs VBE address */
    497                 devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0xe0000000);
     516                devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0xe0000000);
    498517                /*
    499518                 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
    … …  
    501520                 * devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
    502521                 */
    503                 devpciR3SetWord(pPciDev, PCI_COMMAND,
     522                devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
    504523                                  devpciR3GetWord(pPciDev, PCI_COMMAND)
    505524                                | PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS);
    … …  
    516535                    {
    517536                        /* MPIC & MPIC2 */
    518                         devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000 + 0x00040000);
    519                         devpciR3SetWord(pPciDev, PCI_COMMAND,
     537                        devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
     538                        devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
    520539                                          devpciR3GetWord(pPciDev, PCI_COMMAND)
    521540                                        | PCI_COMMAND_MEMACCESS);
    … …  
    528547                {
    529548                    /* macio bridge */
    530                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000);
    531                     devpciR3SetWord(pPciDev, PCI_COMMAND,
     549                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
     550                    devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
    532551                                      devpciR3GetWord(pPciDev, PCI_COMMAND)
    533552                                    | PCI_COMMAND_MEMACCESS);
    … …  
    537556            {
    538557                /* Init PCI-to-PCI bridge. */
    539                 devpciR3SetByte(pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
     558                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
    540559
    541560                AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
    542561                pGlobals->uPciBiosBus++;
    543                 devpciR3SetByte(pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
    544                 devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
     562                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
     563                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
    545564
    546565                /* Add position of this bridge into the array. */
    … …  
    555574                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
    556575                LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
    557                 devpciR3SetByte(pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
     576                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
    558577
    559578                /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
    … …  
    561580                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
    562581                LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
    563                 devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
     582                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
    564583
    565584                /* Save values to compare later to. */
    … …  
    573592                    PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
    574593                    if (pChildPciDev)
    575                         pci_bios_init_device(pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
     594                        pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
    576595                }
    577596
    578597                /* The number of bridges behind the this one is now available. */
    579                 devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
     598                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
    580599
    581600                /*
    … …  
    590609                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
    591610                }
    592                 devpciR3SetByte(pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
     611                devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
    593612
    594613                /* Same with the MMIO limit register but with 1MB boundary here. */
    … …  
    598617                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
    599618                }
    600                 devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
     619                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
    601620
    602621                /*
    … …  
    605624                 * the base register than in the limit register.
    606625                 */
    607                 devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
    608                 devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
    609                 devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
    610                 devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
     626                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
     627                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
     628                devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
     629                devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
    611630                break;
    612631            }
    … …  
    629648                    /* Calculate size. */
    630649                    u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
    631                     devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
     650                    devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
    632651                    u32Size = devpciR3GetDWord(pPciDev, u32Address);
    633652                    bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
    … …  
    665684                                    i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
    666685                            /* Undo the mapping mess caused by the size probing. */
    667                             devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
     686                            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
    668687                        }
    669688                        else
    670689                        {
    671690                            LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
    672                             devpciR3BiosInitSetRegionAddress(pBus, pPciDev, i, uNew);
     691                            devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
    673692                            if (fIsPio)
    674693                                fActiveIORegion = true;
    … …  
    682701
    683702                /* Update the command word appropriately. */
    684                 devpciR3SetWord(pPciDev, PCI_COMMAND,
     703                devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
    685704                                  devpciR3GetWord(pPciDev, PCI_COMMAND)
    686705                                | (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
    … …  
    709728            pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
    710729            pic_irq = pci_irqs[pin];
    711             devpciR3SetByte(pPciDev, PCI_INTERRUPT_LINE, pic_irq);
     730            devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
    712731        }
    713732    }
    … …  
    750769        elcr[irq >> 3] |= (1 << (irq & 7));
    751770        /* Activate irq remapping in PIIX3. */
    752         devpciR3SetByte(pPIIX3, 0x60 + i, irq);
     771        devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
    753772    }
    754773
    … …  
    770789    {
    771790        PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
    772         uint8_t aBridgePositions[256];
    773 
    774791        if (pPciDev)
    775792        {
    776             memset(aBridgePositions, 0, sizeof(aBridgePositions));
    777             Log2(("PCI: Initializing device %d (%#x)\n",
    778                   uDevFn, 0x80000000 | (uDevFn << 8)));
    779             pci_bios_init_device(pGlobals, pBus, pPciDev, 0, aBridgePositions);
     793            Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 | (uDevFn << 8)));
     794            uint8_t aBridgePositions[256];
     795            RT_ZERO(aBridgePositions);
     796            pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
    780797        }
    781798    }
    … …  
    842859    {
    843860        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
    844         rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
     861        rc = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
    845862        PCI_UNLOCK(pDevIns);
    846863    }
    … …  
    9841001 *
    9851002 * @returns VBox status code.
     1003 * @param   pDevIns             The device instance.
    9861004 * @param   pBus                The bus which data is being loaded.
    9871005 * @param   pSSM                The saved state handle.
    … …  
    9891007 * @param   uPass               The pass.
    9901008 */
    991 static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     1009static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    9921010{
    9931011    uint32_t    u32;
    … …  
    10101028        {
    10111029            uint16_t u16 = PCIDevGetCommand(pDev);
    1012             pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
     1030            devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /*u32Value*/, 2 /*cb*/);
    10131031            PCIDevSetCommand(pDev, u16);
    10141032            Assert(PCIDevGetCommand(pDev) == u16);
    … …  
    11021120        if (RT_FAILURE(rc))
    11031121            break;
    1104         devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
     1122        devpciR3CommonRestoreConfig(pDevIns, pDev, &DevTmp.abConfig[0]);
    11051123
    11061124        pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
    … …  
    11571175     * The devices.
    11581176     */
    1159     return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
     1177    return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
    11601178}
    11611179
    … …  
    12041222
    12051223/* -=-=-=-=-=- PDMDEVREG  -=-=-=-=-=- */
     1224
     1225/**
     1226 * @interface_method_impl{PDMDEVREG,pfnReset}
     1227 */
     1228static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
     1229{
     1230    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1231    PDEVPCIBUS  pBus     = &pGlobals->PciBus;
     1232
     1233    /* PCI-specific reset for each device. */
     1234    for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
     1235    {
     1236        if (pBus->apDevices[uDevFn])
     1237            devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
     1238    }
     1239
     1240    pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
     1241}
     1242
     1243
     1244/**
     1245 * @interface_method_impl{PDMDEVREG,pfnDestruct}
     1246 */
     1247static DECLCALLBACK(int)   pciR3Destruct(PPDMDEVINS pDevIns)
     1248{
     1249    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1250    if (pGlobals->PciBus.papBridgesR3)
     1251    {
     1252        PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
     1253        pGlobals->PciBus.papBridgesR3 = NULL;
     1254    }
     1255    return VINF_SUCCESS;
     1256}
    12061257
    12071258
    … …  
    12431294    Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
    12441295
     1296    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1297    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1298
    12451299    /*
    12461300     * Init data and register the PCI bus.
    12471301     */
    1248     PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    12491302    pGlobals->uPciBiosIo   = 0xc000;
    12501303    pGlobals->uPciBiosMmio = 0xf0000000;
    … …  
    12531306    memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
    12541307
    1255     pGlobals->pDevInsR3 = pDevIns;
    1256     pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    1257     pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    1258 
    12591308    pGlobals->PciBus.fTypePiix3  = true;
    12601309    pGlobals->PciBus.fTypeIch9   = false;
    12611310    pGlobals->PciBus.fPureBridge = false;
    1262     pGlobals->PciBus.pDevInsR3 = pDevIns;
    1263     pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    1264     pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    12651311    pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
    12661312                                                                        sizeof(PPDMPCIDEV)
    … …  
    12681314    AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
    12691315
    1270 
    1271     PDMPCIBUSREG PciBusReg;
    1272     PDEVPCIBUS   pBus = &pGlobals->PciBus;
    1273     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
    1274     PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
    1275     PciBusReg.pfnRegisterMsiR3        = NULL;
    1276     PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
    1277     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
    1278     PciBusReg.pfnSetIrqR3             = pciSetIrq;
    1279     PciBusReg.pszSetIrqRC             = fGCEnabled ? "pciSetIrq" : NULL;
    1280     PciBusReg.pszSetIrqR0             = fR0Enabled ? "pciSetIrq" : NULL;
    1281     rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
     1316    PDEVPCIBUS pBus = &pGlobals->PciBus;
     1317    PDMPCIBUSREGCC PciBusReg;
     1318    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
     1319    PciBusReg.pfnRegisterR3              = pciR3MergedRegister;
     1320    PciBusReg.pfnRegisterMsiR3           = NULL;
     1321    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
     1322    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
     1323    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
     1324    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
     1325    PciBusReg.pfnSetIrqR3                = pciSetIrq;
     1326    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
     1327    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
    12821328    if (RT_FAILURE(rc))
    1283         return PDMDEV_SET_ERROR(pDevIns, rc,
    1284                                 N_("Failed to register ourselves as a PCI Bus"));
     1329        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
    12851330    Assert(pBus->iBus == 0);
    1286     if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
     1331    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
    12871332        return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
    12881333                                   N_("PCI helper version mismatch; got %#x expected %#x"),
    1289                                    pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    1290 
    1291     pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
    1292     pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
     1334                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    12931335
    12941336    /* Disable default device locking. */
    … …  
    13511393    }
    13521394
    1353     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
    1354 ;
     1395    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)");
    13551396    if (RT_FAILURE(rc))
    13561397        return rc;
    … …  
    13741415}
    13751416
    1376 
    1377 /**
    1378  * @interface_method_impl{PDMDEVREG,pfnDestruct}
    1379  */
    1380 static DECLCALLBACK(int)   pciR3Destruct(PPDMDEVINS pDevIns)
    1381 {
    1382     PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    1383     if (pGlobals->PciBus.papBridgesR3)
    1384     {
    1385         PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
    1386         pGlobals->PciBus.papBridgesR3 = NULL;
    1387     }
    1388     return VINF_SUCCESS;
    1389 }
    1390 
    1391 
    1392 /**
    1393  * @interface_method_impl{PDMDEVREG,pfnReset}
    1394  */
    1395 static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
    1396 {
    1397     PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    1398     PDEVPCIBUS  pBus     = &pGlobals->PciBus;
    1399 
    1400     /* PCI-specific reset for each device. */
    1401     for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
    1402     {
    1403         if (pBus->apDevices[uDevFn])
    1404             devpciR3ResetDevice(pBus->apDevices[uDevFn]);
    1405     }
    1406 
    1407     pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
    1408 }
    1409 
    1410 #endif /* IN_RING3 */
     1417#else  /* !IN_RING3 */
     1418
     1419/**
     1420 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
     1421 */
     1422static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
     1423{
     1424    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     1425    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1426    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1427
     1428    PDMPCIBUSREGCC PciBusReg;
     1429    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
     1430    PciBusReg.iBus          = pGlobals->PciBus.iBus;
     1431    PciBusReg.pfnSetIrq     = pciSetIrq;
     1432    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
     1433    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     1434    AssertRC(rc);
     1435
     1436    return rc;
     1437}
     1438
     1439#endif /* !IN_RING3 */
    14111440
    14121441/**
    … …  
    14231452    /* .uSharedVersion = */         42,
    14241453    /* .cbInstanceShared = */       sizeof(DEVPCIROOT),
    1425     /* .cbInstanceCC = */           0,
    1426     /* .cbInstanceRC = */           0,
     1454    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
     1455    /* .cbInstanceRC = */           sizeof(DEVPCIBUSRC),
    14271456    /* .cMaxPciDevices = */         2,
    14281457    /* .cMaxMsixVectors = */        0,
    … …  
    14551484#elif defined(IN_RING0)
    14561485    /* .pfnEarlyConstruct = */      NULL,
    1457     /* .pfnConstruct = */           NULL,
     1486    /* .pfnConstruct = */           pciRZRootConstruct,
    14581487    /* .pfnDestruct = */            NULL,
    14591488    /* .pfnFinalDestruct = */       NULL,
    … …  
    14681497    /* .pfnReserved7 = */           NULL,
    14691498#elif defined(IN_RC)
    1470     /* .pfnConstruct = */           NULL,
     1499    /* .pfnConstruct = */           pciRZRootConstruct,
    14711500    /* .pfnReserved0 = */           NULL,
    14721501    /* .pfnReserved1 = */           NULL,
    … …  
    14911520 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
    14921521 */
    1493 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    1494 {
     1522static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     1523{
     1524    LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
     1525
    14951526    /*
    14961527     * The PCI-to-PCI bridge specification defines how the interrupt pins
    … …  
    15001531     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    15011532     */
    1502     PDEVPCIBUS pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1503     PPDMPCIDEV pPciDevBus    = pPciDev;
    1504     int        iIrqPinBridge = iIrq;
    1505     uint8_t    uDevFnBridge  = 0;
     1533    PDEVPCIBUS   pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1534    PDEVPCIBUSCC pBusCC        = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1535    PPDMPCIDEV   pPciDevBus    = pPciDev;
     1536    int          iIrqPinBridge = iIrq;
     1537    uint8_t      uDevFnBridge  = 0;
    15061538
    15071539    /* Walk the chain until we reach the host bus. */
    … …  
    15171549
    15181550    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
    1519     pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
     1551    pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), pBusCC, uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
    15201552}
    15211553
    … …  
    15251557 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
    15261558 */
    1527 static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
    1528 {
    1529     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1530 
    1531     LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
     1559static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
     1560                                                         uint32_t u32Address, unsigned cb, uint32_t u32Value)
     1561{
     1562    LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
     1563    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1564    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    15321565
    15331566    /* If the current bus is not the target bus search for the bus which contains the device. */
    … …  
    15381571        {
    15391572            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
    1540             pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
     1573            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
     1574                                                                 u32Address, cb, u32Value);
    15411575        }
    15421576    }
    … …  
    15481582        {
    15491583            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
    1550             /** @todo return rc   */
    1551             pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
    1552         }
    1553     }
     1584            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     1585            if (pPciDev->Int.s.pfnConfigWrite)
     1586                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
     1587            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     1588                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     1589                                                           pPciDev, u32Address, cb, u32Value);
     1590        }
     1591    }
     1592    return rcStrict;
    15541593}
    15551594
    … …  
    15581597 * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
    15591598 */
    1560 static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
    1561 {
    1562     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1563     uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
    1564 
     1599static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
     1600                                                        uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
     1601{
    15651602    LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
     1603    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1604    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    15661605
    15671606    /* If the current bus is not the target bus search for the bus which contains the device. */
    … …  
    15711610        if (pBridgeDevice)
    15721611        {
    1573             AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
    1574             u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
    1575         }
     1612            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
     1613            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
     1614                                                                iBus, iDevice, u32Address, cb, pu32Value);
     1615        }
     1616        else
     1617            *pu32Value = UINT32_MAX;
    15761618    }
    15771619    else
    … …  
    15811623        if (pPciDev)
    15821624        {
    1583             u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
    1584             LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
    1585         }
    1586     }
    1587 
    1588     return u32Value;
     1625            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     1626            if (pPciDev->Int.s.pfnConfigRead)
     1627                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
     1628            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     1629                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
     1630
     1631            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
     1632        }
     1633        else
     1634            *pu32Value = UINT32_MAX;
     1635    }
     1636
     1637    return rcStrict;
    15891638}
    15901639
    … …  
    16081657    if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
    16091658        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    1610     return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
     1659    return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
    16111660}
    16121661
    … …  
    16231672    pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
    16241673    pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
     1674}
     1675
     1676
     1677/**
     1678 * @interface_method_impl{PDMDEVREG,pfnDestruct}
     1679 */
     1680static DECLCALLBACK(int)   pcibridgeR3Destruct(PPDMDEVINS pDevIns)
     1681{
     1682    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1683    if (pBus->papBridgesR3)
     1684    {
     1685        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
     1686        pBus->papBridgesR3 = NULL;
     1687    }
     1688    return VINF_SUCCESS;
    16251689}
    16261690
    … …  
    16551719    Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
    16561720
     1721    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1722    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1723
    16571724    /*
    16581725     * Init data and register the PCI bus.
    16591726     */
    1660     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    16611727    pBus->fTypePiix3  = true;
    16621728    pBus->fTypeIch9   = false;
    16631729    pBus->fPureBridge = true;
    1664     pBus->pDevInsR3 = pDevIns;
    1665     pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    1666     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    16671730    pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
    16681731    AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
    16691732
    1670     PDMPCIBUSREG PciBusReg;
    1671     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
    1672     PciBusReg.pfnRegisterR3           = pcibridgeR3MergedRegisterDevice;
    1673     PciBusReg.pfnRegisterMsiR3        = NULL;
    1674     PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
    1675     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
    1676     PciBusReg.pfnSetIrqR3             = pcibridgeSetIrq;
    1677     PciBusReg.pszSetIrqRC             = fGCEnabled ? "pcibridgeSetIrq" : NULL;
    1678     PciBusReg.pszSetIrqR0             = fR0Enabled ? "pcibridgeSetIrq" : NULL;
    1679     rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
     1733    PDMPCIBUSREGCC PciBusReg;
     1734    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
     1735    PciBusReg.pfnRegisterR3              = pcibridgeR3MergedRegisterDevice;
     1736    PciBusReg.pfnRegisterMsiR3           = NULL;
     1737    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
     1738    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
     1739    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
     1740    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
     1741    PciBusReg.pfnSetIrqR3                = pcibridgeSetIrq;
     1742    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
     1743    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
    16801744    if (RT_FAILURE(rc))
    16811745        return PDMDEV_SET_ERROR(pDevIns, rc,
    16821746                                N_("Failed to register ourselves as a PCI Bus"));
    16831747    Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
    1684     if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
     1748    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
    16851749        return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
    16861750                                   N_("PCI helper version mismatch; got %#x expected %#x"),
    1687                                    pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    1688 
    1689     pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
    1690     pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
     1751                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    16911752
    16921753    /*
    … …  
    17361797}
    17371798
    1738 
    1739 /**
    1740  * @interface_method_impl{PDMDEVREG,pfnDestruct}
    1741  */
    1742 static DECLCALLBACK(int)   pcibridgeR3Destruct(PPDMDEVINS pDevIns)
    1743 {
    1744     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1745     if (pBus->papBridgesR3)
    1746     {
    1747         PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
    1748         pBus->papBridgesR3 = NULL;
    1749     }
    1750     return VINF_SUCCESS;
    1751 }
    1752 
    1753 #endif /* IN_RING3 */
     1799#else  /* !IN_RING3 */
     1800
     1801/**
     1802 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
     1803 */
     1804static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
     1805{
     1806    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     1807    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1808    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1809
     1810    PDMPCIBUSREGCC PciBusReg;
     1811    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
     1812    PciBusReg.iBus          = pBus->iBus;
     1813    PciBusReg.pfnSetIrq     = pcibridgeSetIrq;
     1814    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
     1815    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     1816    AssertRC(rc);
     1817
     1818    return rc;
     1819}
     1820
     1821#endif /* !IN_RING3 */
    17541822
    17551823/**
    … …  
    17671835    /* .uSharedVersion = */         42,
    17681836    /* .cbInstanceShared = */       sizeof(DEVPCIBUS),
    1769     /* .cbInstanceCC = */           0,
     1837    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
    17701838    /* .cbInstanceRC = */           0,
    17711839    /* .cMaxPciDevices = */         1,
    … …  
    17991867#elif defined(IN_RING0)
    18001868    /* .pfnEarlyConstruct = */      NULL,
    1801     /* .pfnConstruct = */           NULL,
     1869    /* .pfnConstruct = */           pcibridgeRZConstruct,
    18021870    /* .pfnDestruct = */            NULL,
    18031871    /* .pfnFinalDestruct = */       NULL,
    … …  
    18121880    /* .pfnReserved7 = */           NULL,
    18131881#elif defined(IN_RC)
    1814     /* .pfnConstruct = */           NULL,
     1882    /* .pfnConstruct = */           pcibridgeRZConstruct,
    18151883    /* .pfnReserved0 = */           NULL,
    18161884    /* .pfnReserved1 = */           NULL,

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r80704 r80943  
    9393*********************************************************************************************************************************/
    9494/* Prototypes */
    95 static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
    96                                   int iIrq, int iLevel, uint32_t uTagSrc);
     95static void ich9pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
     96                                  uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc);
    9797#ifdef IN_RING3
    9898static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns);
    9999DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
    100 static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus);
    101 static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun);
     100static void ich9pciBiosInitAllDevicesOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus);
     101static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun);
    102102#endif
    103103
    … …  
    125125{
    126126    LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
    127     ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
     127    ich9pciSetIrqInternal(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     128                          pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
    128129}
    129130
    … …  
    163164        || MsixIsEnabled(pPciDev))
    164165        iIrqPinVector = iIrq;
    165     ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
     166    ich9pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     167                          uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
    166168}
    167169
    … …  
    292294 * Perform configuration space write.
    293295 */
    294 static int ich9pciConfigWrite(PDEVPCIROOT pPciRoot, PciAddress* pAddr,
    295                               uint32_t val, int cb, int rcReschedule)
    296 {
    297     int rc = VINF_SUCCESS;
    298 #ifdef IN_RING3
    299     NOREF(rcReschedule);
    300 #else
    301     RT_NOREF2(val, cb);
    302 #endif
    303 
    304     if (pAddr->iBus != 0)       /* forward to subordinate bus */
     296static VBOXSTRICTRC ich9pciConfigWrite(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PciAddress const *pPciAddr,
     297                                       uint32_t u32Value, int cb, int rcReschedule)
     298{
     299    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     300
     301    if (pPciAddr->iBus != 0)       /* forward to subordinate bus */
    305302    {
    306303        if (pPciRoot->PciBus.cBridges)
    307304        {
    308305#ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
    309             PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pAddr->iBus);
     306            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pPciAddr->iBus);
    310307            if (pBridgeDevice)
    311308            {
    312309                AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
    313                 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
    314                                                           pAddr->iRegister, val, cb);
     310                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
     311                                                                     pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb, u32Value);
    315312            }
    316313#else
    317             rc = rcReschedule;
     314            rcStrict = rcReschedule;
    318315#endif
    319316        }
    … …  
    321318    else                    /* forward to directly connected device */
    322319    {
    323         R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pAddr->iDeviceFunc];
     320        R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pPciAddr->iDeviceFunc];
    324321        if (pPciDev)
    325322        {
    326323#ifdef IN_RING3
    327             rc = VBOXSTRICTRC_TODO(pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
    328                                                                  pAddr->iRegister, val, cb));
     324            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     325            if (pPciDev->Int.s.pfnConfigWrite)
     326                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
     327                                                         pPciAddr->iRegister, cb, u32Value);
     328            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     329                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     330                                                           pPciDev, pPciAddr->iRegister, cb, u32Value);
     331            RT_NOREF(rcReschedule);
    329332#else
    330             rc = rcReschedule;
     333            rcStrict = rcReschedule;
     334            RT_NOREF(pDevIns, u32Value, cb);
    331335#endif
    332336        }
    333337    }
    334338
    335     Log2Func(("%02x:%02x.%d reg %x(%d) %x %Rrc\n",
    336               pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister, cb, val, rc));
    337     return rc;
     339    Log2Func(("%02x:%02x.%u reg %x(%u) %x %Rrc\n", pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7,
     340              pPciAddr->iRegister, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
     341    return rcStrict;
    338342}
    339343
    … …  
    374378
    375379            /* Perform configuration space write */
    376             rc = ich9pciConfigWrite(pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
     380            rc = ich9pciConfigWrite(pDevIns, pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
    377381        } while (0);
    378382
    … …  
    388392 * Perform configuration space read.
    389393 */
    390 static int ich9pciConfigRead(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb,
    391                              uint32_t *pu32, int rcReschedule)
    392 {
    393     int rc = VINF_SUCCESS;
     394static VBOXSTRICTRC ich9pciConfigRead(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb, uint32_t *pu32Value, int rcReschedule)
     395{
     396    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    394397#ifdef IN_RING3
    395398    NOREF(rcReschedule);
    … …  
    407410            {
    408411                AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
    409                 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
    410                                                                  pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
     412                rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
     413                                                                    pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb, pu32Value);
    411414            }
    412415            else
    413                 *pu32 = 0xffffffff;
     416                *pu32Value = UINT32_MAX;
    414417#else
    415             rc = rcReschedule;
     418            rcStrict = rcReschedule;
    416419#endif
    417420        }
    418421        else
    419             *pu32 = 0xffffffff;
     422            *pu32Value = 0xffffffff;
    420423    }
    421424    else                    /* forward to directly connected device */
    … …  
    425428        {
    426429#ifdef IN_RING3
    427             *pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
     430            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     431            if (pPciDev->Int.s.pfnConfigRead)
     432                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev,
     433                                                        pPciAddr->iRegister, cb, pu32Value);
     434            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     435                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, pPciAddr->iRegister, cb, pu32Value);
    428436#else
    429             rc = rcReschedule;
     437            rcStrict = rcReschedule;
    430438#endif
    431439        }
    432440        else
    433             *pu32 = 0xffffffff;
    434     }
    435 
    436     Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
    437               pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister, cb, *pu32, rc));
    438     return rc;
     441            *pu32Value = UINT32_MAX;
     442    }
     443
     444    Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n", pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7,
     445              pPciAddr->iRegister, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict) ));
     446    return rcStrict;
    439447}
    440448
    … …  
    457465{
    458466    NOREF(pvUser);
    459     int rc = VINF_SUCCESS;
    460467    if (!(uPort % cb))
    461468    {
    … …  
    465472        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
    466473
    467         do
    468         {
    469             /* Configuration space mapping enabled? */
    470             if (!(pThis->uConfigReg & (1 << 31)))
    471             {
    472                 rc = VINF_SUCCESS;
    473                 break;
    474             }
    475 
     474        /* Configuration space mapping enabled? */
     475        int rc;
     476        if (!(pThis->uConfigReg & (1 << 31)))
     477            rc = VINF_SUCCESS;
     478        else
     479        {
    476480            /* Decode target device and configuration space register */
    477481            PciAddress aPciAddr;
    … …  
    479483
    480484            /* Perform configuration space read */
    481             rc =  ich9pciConfigRead(pThis, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
    482         } while (0);
     485            rc = ich9pciConfigRead(pThis, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
     486        }
    483487
    484488        PCI_UNLOCK(pDevIns);
    … …  
    528532}
    529533
    530 static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
    531                               uint32_t uTagSrc, int iForcedIrq)
     534static void ich9pciApicSetIrq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
     535                              uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, uint32_t uTagSrc, int iForcedIrq)
    532536{
    533537    /* This is only allowed to be called with a pointer to the root bus. */
    … …  
    549553        Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
    550554                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
    551         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
     555        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
    552556
    553557        if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
    … …  
    562566            Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
    563567                      R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
    564             pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
     568            pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
    565569        }
    566570    } else {
    567571        Log3Func(("(forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
    568572                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
    569         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
    570     }
    571 }
    572 
    573 static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
    574                                   int iIrq, int iLevel, uint32_t uTagSrc)
     573        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iForcedIrq, iLevel, uTagSrc);
     574    }
     575}
     576
     577static void ich9pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
     578                                  uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    575579{
    576580    /* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
    … …  
    583587        Assert(!MsixIsEnabled(pPciDev));    /* Not allowed -- see note above. */
    584588        LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
    585         PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
    586         MsiNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
     589        MsiNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
    587590        return;
    588591    }
    … …  
    591594    {
    592595        LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
    593         PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
    594         MsixNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
     596        MsixNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
    595597        return;
    596598    }
    … …  
    618620             */
    619621            /* safe, only needs to go to the config space array */
    620             ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
     622            ich9pciApicSetIrq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
    621623        else
    622             ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
     624            ich9pciApicSetIrq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
    623625    }
    624626}
    … …  
    670672
    671673    /* Perform configuration space write */
    672     int rc = ich9pciConfigWrite(pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
     674    int rc = ich9pciConfigWrite(pDevIns, pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
    673675    PCI_UNLOCK(pDevIns);
    674676
    … …  
    770772uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
    771773{
    772     return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
     774    uint32_t     u32Value = UINT32_MAX;
     775    VBOXSTRICTRC rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     776    if (pPciDev->Int.s.pfnConfigRead)
     777        rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb, &u32Value);
     778    if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     779        rcStrict = devpciR3CommonConfigReadWorker(pPciDev, iRegister, cb, &u32Value);
     780    AssertRCSuccess(rcStrict);
     781    return u32Value;
    773782}
    774783
    … …  
    779788}
    780789
    781 void devpciR3SetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb)
    782 {
    783     pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, u32, cb);
     790/**
     791 * Worker for devpciR3SetByte(), devpciR3SetWord() and devpciR3SetDWord(), also
     792 * used during state restore.
     793 */
     794void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32Value, int cb)
     795{
     796    Assert(cb <= 4 && cb != 3);
     797    VBOXSTRICTRC rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     798    if (pPciDev->Int.s.pfnConfigWrite)
     799        rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb, u32Value);
     800    if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     801        rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     802                                                   pPciDev, iRegister, cb, u32Value);
     803    AssertRCSuccess(rcStrict);
    784804}
    785805
    … …  
    790810static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
    791811{
    792     NOREF(pDevIns);
    793     int rc;
    794 
    795     rc = MsiR3Init(pPciDev, pMsiReg);
    796     if (RT_FAILURE(rc))
    797         return rc;
    798 
    799     rc = MsixR3Init(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
    800     if (RT_FAILURE(rc))
    801         return rc;
    802 
    803     return VINF_SUCCESS;
     812    //PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     813    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     814
     815    int rc = MsiR3Init(pPciDev, pMsiReg);
     816    if (RT_SUCCESS(rc))
     817        rc = MsixR3Init(pBusCC->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
     818
     819    return rc;
    804820}
    805821
    … …  
    871887
    872888/**
    873  * @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
    874  */
    875 DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    876                                                     PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    877                                                     PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
     889 * @interface_method_impl{PDMPCIBUSREG,pfnInterceptConfigAccesses}
     890 */
     891DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     892                                                         PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
    878893{
    879894    NOREF(pDevIns);
    880895
    881     if (ppfnReadOld)
    882         *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
    883896    pPciDev->Int.s.pfnConfigRead  = pfnRead;
    884 
    885     if (ppfnWriteOld)
    886         *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
    887897    pPciDev->Int.s.pfnConfigWrite = pfnWrite;
    888898}
    … …  
    979989
    980990
    981 static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
    982 {
    983     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    984 
    985     LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
     991/**
     992 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
     993 */
     994static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice,
     995                                                           uint32_t u32Address, unsigned cb, uint32_t u32Value)
     996{
     997    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     998    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     999    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%#x cb=%d u32Value=%#x\n", pDevIns, uBus, uDevice, u32Address, cb, u32Value));
    9861000
    9871001    /* If the current bus is not the target bus search for the bus which contains the device. */
    … …  
    9941008            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
    9951009            pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
    996                                                       u32Address, u32Value, cb);
     1010                                                      u32Address, cb, u32Value);
    9971011        }
    9981012    }
    … …  
    10041018        {
    10051019            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
    1006             /** @todo return rc */
    1007             pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
    1008         }
    1009     }
    1010 }
    1011 
    1012 static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, unsigned cb)
    1013 {
    1014     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1015     uint32_t u32Value;
    1016 
    1017     LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
     1020            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     1021            if (pPciDev->Int.s.pfnConfigWrite)
     1022                rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
     1023            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     1024                rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
     1025                                                           pPciDev, u32Address, cb, u32Value);
     1026        }
     1027    }
     1028    return rcStrict;
     1029}
     1030
     1031/**
     1032 * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
     1033 */
     1034static DECLCALLBACK(VBOXSTRICTRC) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice,
     1035                                                          uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
     1036{
     1037    PDEVPCIBUS   pBus     = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1038    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     1039    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%#x cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
    10181040
    10191041    /* If the current bus is not the target bus search for the bus which contains the device. */
    … …  
    10241046        if (pBridgeDevice)
    10251047        {
    1026             AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
    1027             u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
    1028                                                                 u32Address, cb);
     1048            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
     1049            rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
     1050                                                                u32Address, cb, pu32Value);
    10291051        }
    10301052        else
    1031             u32Value = 0xffffffff;
     1053            *pu32Value = UINT32_MAX;
    10321054    }
    10331055    else
    … …  
    10371059        if (pPciDev)
    10381060        {
    1039             u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
    1040             LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
     1061            rcStrict = VINF_PDM_PCI_DO_DEFAULT;
     1062            if (pPciDev->Int.s.pfnConfigRead)
     1063                rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
     1064            if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
     1065                rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
     1066            LogFunc(("%s: u32Address=%02x *pu32Value=%#010x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
    10411067        }
    10421068        else
    1043             u32Value = 0xffffffff;
    1044     }
    1045 
    1046     return u32Value;
     1069            *pu32Value = UINT32_MAX;
     1070    }
     1071
     1072    return rcStrict;
    10471073}
    10481074
    … …  
    10551081 * Common routine for restoring the config registers of a PCI device.
    10561082 *
     1083 * @param   pDevIns             The device instance of the PC bus.
    10571084 * @param   pDev                The PCI device.
    10581085 * @param   pbSrcConfig         The configuration register values to be loaded.
    10591086 */
    1060 void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
     1087void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
    10611088{
    10621089    /*
    … …  
    11991226                    /* safe, only needs to go to the config space array */
    12001227                    PDMPciDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec/ich9pciR3CommonLoadExec. */
    1201                 pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
     1228                devpciR3SetCfg(pDevIns, pDev, off, u32Src, cb);
    12021229            }
    12031230        }
    … …  
    13121339 *
    13131340 * @returns VBox status code.
     1341 * @param   pDevIns             The device instance of the bus.
    13141342 * @param   pBus                The bus which data is being loaded.
    13151343 * @param   pSSM                The saved state handle.
    … …  
    13171345 * @param   uPass               The pass.
    13181346 */
    1319 static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    1320 {
    1321     uint32_t    u32;
    1322     int         rc;
     1347static int ich9pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     1348{
     1349    uint32_t     u32;
     1350    int          rc;
    13231351
    13241352    Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
    … …  
    13421370            /* safe, only needs to go to the config space array */
    13431371            uint16_t u16 = PDMPciDevGetCommand(pDev);
    1344             pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
     1372            devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /*u32Value*/, 2 /*cb*/);
    13451373            /* safe, only needs to go to the config space array */
    13461374            PDMPciDevSetCommand(pDev, u16);
    … …  
    14631491            break;
    14641492        Assert(!pciDevIsPassthrough(pDev));
    1465         devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
     1493        devpciR3CommonRestoreConfig(pDevIns, pDev, &DevTmp.abConfig[0]);
    14661494
    14671495        pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
    … …  
    15141542        AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
    15151543
    1516     return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
     1544    return ich9pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
    15171545}
    15181546
    … …  
    15201548{
    15211549    PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1522     return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
     1550    return ich9pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
    15231551}
    15241552
    … …  
    15281556
    15291557
    1530 void devpciR3BiosInitSetRegionAddress(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr)
     1558void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr)
    15311559{
    15321560    NOREF(pBus);
    … …  
    15421570
    15431571    /* Write address of the device. */
    1544     devpciR3SetDWord(pPciDev, uReg, (uint32_t)addr);
     1572    devpciR3SetDWord(pDevIns, pPciDev, uReg, (uint32_t)addr);
    15451573    if (f64Bit)
    1546         devpciR3SetDWord(pPciDev, uReg + 4, (uint32_t)(addr >> 32));
    1547 }
    1548 
    1549 
    1550 static void ich9pciBiosInitBridge(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
     1574        devpciR3SetDWord(pDevIns, pPciDev, uReg + 4, (uint32_t)(addr >> 32));
     1575}
     1576
     1577
     1578static void ich9pciBiosInitBridge(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
    15511579{
    15521580    PPDMPCIDEV pBridge = &pBus->PciDev;
    … …  
    15631591        LogFunc(("Aligned I/O start address. New address %#x\n", pPciRoot->uPciBiosIo));
    15641592    }
    1565     devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0);
     1593    devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0);
    15661594
    15671595    /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
    … …  
    15711599        LogFunc(("Aligned MMIO start address. New address %#x\n", pPciRoot->uPciBiosMmio));
    15721600    }
    1573     devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
     1601    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
    15741602
    15751603    /* Save values to compare later to. */
    … …  
    15781606
    15791607    /* Init all devices behind the bridge (recursing to further buses). */
    1580     ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
     1608    ich9pciBiosInitAllDevicesOnBus(pDevIns, pPciRoot, pBus);
    15811609
    15821610    /*
    … …  
    15881616        /* Need again alignment to a 4KB boundary. */
    15891617        pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K);
    1590         devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0);
     1618        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0);
    15911619    }
    15921620    else
    15931621    {
    1594         devpciR3SetByte(pBridge, VBOX_PCI_IO_BASE, 0xf0);
    1595         devpciR3SetByte(pBridge, VBOX_PCI_IO_LIMIT, 0x00);
     1622        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_BASE, 0xf0);
     1623        devpciR3SetByte(pDevIns, pBridge, VBOX_PCI_IO_LIMIT, 0x00);
    15961624    }
    15971625
    … …  
    16001628    {
    16011629        pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
    1602         devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0));
     1630        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0));
    16031631    }
    16041632    else
    16051633    {
    1606         devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_BASE, 0xfff0);
    1607         devpciR3SetWord(pBridge, VBOX_PCI_MEMORY_LIMIT, 0x0000);
     1634        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_BASE, 0xfff0);
     1635        devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_MEMORY_LIMIT, 0x0000);
    16081636    }
    16091637
    … …  
    16131641     * the base register than in the limit register.
    16141642     */
    1615     devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
    1616     devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0000);
    1617     devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, 0x00000000);
    1618     devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00000000);
     1643    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
     1644    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0000);
     1645    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_BASE_UPPER32, 0x00000000);
     1646    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00000000);
    16191647}
    16201648
    … …  
    16351663}
    16361664
    1637 static void ich9pciBiosInitDeviceBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev)
     1665static void ich9pciBiosInitDeviceBARs(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev)
    16381666{
    16391667    int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
    … …  
    16691697        if (f64Bit)
    16701698        {
    1671             devpciR3SetDWord(pPciDev, u32Address,   UINT32_C(0xffffffff));
    1672             devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
     1699            devpciR3SetDWord(pDevIns, pPciDev, u32Address,   UINT32_C(0xffffffff));
     1700            devpciR3SetDWord(pDevIns, pPciDev, u32Address+4, UINT32_C(0xffffffff));
    16731701            cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
    16741702                                      devpciR3GetDWord(pPciDev, u32Address+4));
    … …  
    16841712        {
    16851713            uint32_t cbRegSize32;
    1686             devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
     1714            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
    16871715            cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
    16881716
    … …  
    17311759                    uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
    17321760                    LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
    1733                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
     1761                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
    17341762                    fActiveMemRegion = true;
    17351763                    pPciRoot->uPciBiosMmio64 = uNew + cbRegSize64;
    … …  
    17431771                            iRegion, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
    17441772                    /* Undo the mapping mess caused by the size probing. */
    1745                     devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
     1773                    devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
    17461774                }
    17471775            }
    … …  
    17491777            {
    17501778                LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
    1751                 devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
     1779                devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
    17521780                if (fIsPio)
    17531781                    fActiveIORegion = true;
    … …  
    17691797    if (fActiveIORegion)
    17701798        uCmd |= VBOX_PCI_COMMAND_IO; /* Enable I/O space access. */
    1771     devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
    1772 }
    1773 
    1774 static bool ich9pciBiosInitDevicePrefetchableBARs(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, bool fUse64Bit, bool fDryrun)
     1799    devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd);
     1800}
     1801
     1802static bool ich9pciBiosInitDevicePrefetchableBARs(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, bool fUse64Bit, bool fDryrun)
    17751803{
    17761804    int cRegions = ich9pciBiosInitDeviceGetRegions(pPciDev);
    … …  
    17921820        if (f64Bit)
    17931821        {
    1794             devpciR3SetDWord(pPciDev, u32Address,   UINT32_C(0xffffffff));
    1795             devpciR3SetDWord(pPciDev, u32Address+4, UINT32_C(0xffffffff));
     1822            devpciR3SetDWord(pDevIns, pPciDev, u32Address,   UINT32_C(0xffffffff));
     1823            devpciR3SetDWord(pDevIns, pPciDev, u32Address+4, UINT32_C(0xffffffff));
    17961824            cbRegSize64 = RT_MAKE_U64(devpciR3GetDWord(pPciDev, u32Address),
    17971825                                      devpciR3GetDWord(pPciDev, u32Address+4));
    … …  
    18021830        {
    18031831            uint32_t cbRegSize32;
    1804             devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
     1832            devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
    18051833            cbRegSize32 = devpciR3GetDWord(pPciDev, u32Address);
    18061834            cbRegSize32 &= ~UINT32_C(0x0f);
    … …  
    18311859                {
    18321860                    LogFunc(("Start address of MMIO region %u is %#x\n", iRegion, uNew));
    1833                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
     1861                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
    18341862                    fActiveMemRegion = true;
    18351863                }
    … …  
    18511879                {
    18521880                    LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
    1853                     devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, uNew);
     1881                    devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, iRegion, uNew);
    18541882                    fActiveMemRegion = true;
    18551883                }
    … …  
    18671895        if (fActiveMemRegion)
    18681896            uCmd |= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */
    1869         devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd);
     1897        devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd);
    18701898    }
    18711899    else
    … …  
    18751903}
    18761904
    1877 static bool ich9pciBiosInitBridgePrefetchable(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
     1905static bool ich9pciBiosInitBridgePrefetchable(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
    18781906{
    18791907    PPDMPCIDEV pBridge = &pBus->PciDev;
    … …  
    18881916
    18891917    /* Init all devices behind the bridge (recursing to further buses). */
    1890     bool fRes = ich9pciBiosInitAllDevicesPrefetchableOnBus(pPciRoot, pBus, fUse64Bit, fDryrun);
     1918    bool fRes = ich9pciBiosInitAllDevicesPrefetchableOnBus(pDevIns, pPciRoot, pBus, fUse64Bit, fDryrun);
    18911919    if (fDryrun)
    18921920        return fRes;
    … …  
    19091937        uLimit = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M) - 1;
    19101938    }
    1911     devpciR3SetDWord(pBridge, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32);
    1912     devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_BASE, (uint32_t)(uBase >> 16) & UINT32_C(0xfff0));
    1913     devpciR3SetDWord(pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, uLimit >> 32);
    1914     devpciR3SetWord(pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, (uint32_t)(uLimit >> 16) & UINT32_C(0xfff0));
     1939    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32);
     1940    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_BASE, (uint32_t)(uBase >> 16) & UINT32_C(0xfff0));
     1941    devpciR3SetDWord(pDevIns, pBridge, VBOX_PCI_PREF_LIMIT_UPPER32, uLimit >> 32);
     1942    devpciR3SetWord(pDevIns, pBridge, VBOX_PCI_PREF_MEMORY_LIMIT, (uint32_t)(uLimit >> 16) & UINT32_C(0xfff0));
    19151943
    19161944    return false;
    19171945}
    19181946
    1919 static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, bool fUse64Bit, bool fDryrun)
     1947static bool ich9pciBiosInitAllDevicesPrefetchableOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus,
     1948                                                       bool fUse64Bit, bool fDryrun)
    19201949{
    19211950    /* First pass: assign resources to all devices. */
    … …  
    19311960
    19321961        /* prefetchable memory mappings */
    1933         bool fRes = ich9pciBiosInitDevicePrefetchableBARs(pPciRoot, pBus, pPciDev, fUse64Bit, fDryrun);
     1962        bool fRes = ich9pciBiosInitDevicePrefetchableBARs(pDevIns, pPciRoot, pBus, pPciDev, fUse64Bit, fDryrun);
    19341963        if (fRes)
    19351964        {
    … …  
    19471976        PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    19481977
    1949         bool fRes = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, fUse64Bit, fDryrun);
     1978        bool fRes = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, fUse64Bit, fDryrun);
    19501979        if (fRes)
    19511980        {
    … …  
    19571986}
    19581987
    1959 static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
     1988static void ich9pciBiosInitAllDevicesOnBus(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus)
    19601989{
    19611990    /* First pass: assign resources to all devices and map the interrupt. */
    … …  
    19712000
    19722001        /* default memory mappings */
    1973         ich9pciBiosInitDeviceBARs(pPciRoot, pBus, pPciDev);
     2002        ich9pciBiosInitDeviceBARs(pDevIns, pPciRoot, pBus, pPciDev);
    19742003        uint16_t uDevClass = devpciR3GetWord(pPciDev, VBOX_PCI_CLASS_DEVICE);
    19752004        switch (uDevClass)
    … …  
    19772006            case 0x0101:
    19782007                /* IDE controller */
    1979                 devpciR3SetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
    1980                 devpciR3SetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
     2008                devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8000); /* enable IDE0 */
     2009                devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8000); /* enable IDE1 */
    19812010                break;
    19822011            case 0x0300:
    … …  
    19942023                 */
    19952024                uint16_t uCmd = devpciR3GetWord(pPciDev, VBOX_PCI_COMMAND);
    1996                 devpciR3SetWord(pPciDev, VBOX_PCI_COMMAND, uCmd | VBOX_PCI_COMMAND_IO);
     2025                devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_COMMAND, uCmd | VBOX_PCI_COMMAND_IO);
    19972026                break;
    19982027            }
    … …  
    20192048            Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
    20202049                 iPin, iIrq, pBus->iBus, uDevFn>>3, uDevFn&7));
    2021             devpciR3SetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, iIrq);
     2050            devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_INTERRUPT_LINE, iIrq);
    20222051        }
    20232052    }
    … …  
    20312060        PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    20322061
    2033         ich9pciBiosInitBridge(pPciRoot, pChildBus);
     2062        ich9pciBiosInitBridge(pDevIns, pPciRoot, pChildBus);
    20342063    }
    20352064
    … …  
    20492078            uint64_t u64MMIOAddressBase = pPciRoot->uPciBiosMmio64;
    20502079
    2051             bool fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit */, true /* fDryrun */);
     2080            bool fProbe = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, false /* fUse64Bit */, true /* fDryrun */);
    20522081            pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
    20532082            pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
    20542083            if (fProbe)
    20552084            {
    2056                 fProbe = ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit */, true /* fDryrun */);
     2085                fProbe = ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, true /* fUse64Bit */, true /* fDryrun */);
    20572086                pPciRoot->uPciBiosMmio = u32MMIOAddressBase;
    20582087                pPciRoot->uPciBiosMmio64 = u64MMIOAddressBase;
    … …  
    20602089                    LogRel(("PCI: unresolvable prefetchable memory behind bridge %02x:%02x.%d\n", pChildBus->iBus, pBridge->uDevFn >> 3, pBridge->uDevFn & 7));
    20612090                else
    2062                     ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, true /* fUse64Bit */, false /* fDryrun */);
     2091                    ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, true /* fUse64Bit */, false /* fDryrun */);
    20632092            }
    20642093            else
    2065                 ich9pciBiosInitBridgePrefetchable(pPciRoot, pChildBus, false /* fUse64Bit */, false /* fDryrun */);
     2094                ich9pciBiosInitBridgePrefetchable(pDevIns, pPciRoot, pChildBus, false /* fUse64Bit */, false /* fDryrun */);
    20662095        }
    20672096    }
    … …  
    20822111 * @param   uBusPrimary      The primary bus number the bus is connected to.
    20832112 */
    2084 static uint8_t ich9pciBiosInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, uint32_t *pbmUsed, uint8_t uBusPrimary)
     2113static uint8_t ich9pciBiosInitBridgeTopology(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus,
     2114                                             uint32_t *pbmUsed, uint8_t uBusPrimary)
    20852115{
    20862116    PPDMPCIDEV pBridgeDev = &pBus->PciDev;
    … …  
    20952125    if (pBus->iBus != 0)
    20962126    {
    2097         devpciR3SetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
    2098         devpciR3SetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
     2127        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
     2128        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
    20992129        /* Since the subordinate bus value can only be finalized once we
    21002130         * finished recursing through everything behind the bridge, the only
    … …  
    21032133         * (for our own sloppy emulation it apparently doesn't matter, but
    21042134         * this is vital for real PCI bridges/devices in passthrough mode). */
    2105         devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
     2135        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
    21062136    }
    21072137
    … …  
    21132143                  ("Device is not a PCI bridge but on the list of PCI bridges\n"));
    21142144        PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    2115         uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pPciRoot, pChildBus, pbmUsed, pBus->iBus);
     2145        uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pDevIns, pPciRoot, pChildBus, pbmUsed, pBus->iBus);
    21162146        uMaxSubNum = RT_MAX(uMaxSubNum, uMaxChildSubBus);
    21172147    }
    21182148
    21192149    if (pBus->iBus != 0)
    2120         devpciR3SetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
     2150        devpciR3SetByte(pDevIns, pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
    21212151    for (uint32_t i = pBus->iBus; i <= uMaxSubNum; i++)
    21222152        *pbmUsed |= RT_BIT_32(i);
    … …  
    21262156     * but on the other hand it can't hurt either. */
    21272157    if (pBus->iBus != 0)
    2128         devpciR3SetWord(pBridgeDev, VBOX_PCI_COMMAND,
     2158        devpciR3SetWord(pDevIns, pBridgeDev, VBOX_PCI_COMMAND,
    21292159                          VBOX_PCI_COMMAND_IO
    21302160                        | VBOX_PCI_COMMAND_MEMORY
    … …  
    21322162
    21332163    /* safe, only needs to go to the config space array */
    2134     Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n",
    2135           pBus,
    2136           PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
    2137           PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
    2138           PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
    2139           ));
     2164    Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n", pBus,
     2165              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
     2166              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
     2167              PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS) ));
    21402168
    21412169    return uMaxSubNum;
    … …  
    21842212    AssertLogRel(pBus->iBus == 0);
    21852213    uint32_t bmUsed = 0;
    2186     ich9pciBiosInitBridgeTopology(pPciRoot, pBus, &bmUsed, 0);
     2214    ich9pciBiosInitBridgeTopology(pDevIns, pPciRoot, pBus, &bmUsed, 0);
    21872215
    21882216    /*
    21892217     * Init all devices on bus 0 (recursing to further buses).
    21902218     */
    2191     ich9pciBiosInitAllDevicesOnBus(pPciRoot, pBus);
     2219    ich9pciBiosInitAllDevicesOnBus(pDevIns, pPciRoot, pBus);
    21922220
    21932221    return VINF_SUCCESS;
    … …  
    21992227
    22002228/**
    2201  * @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
    2202  */
    2203 DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
    2204 {
    2205     NOREF(pDevIns);
    2206 
     2229 * Reads config space for a device, ignoring interceptors.
     2230 */
     2231DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
     2232{
    22072233    uint32_t uValue;
    22082234    if (uAddress + cb <= 256)
    … …  
    22462272        uValue = 0;
    22472273    }
    2248     return uValue;
     2274
     2275    *pu32Value = uValue;
     2276    return VINF_SUCCESS;
     2277}
     2278
     2279
     2280/**
     2281 * @interface_method_impl{PDMPCIBUSREGR3,pfnConfigRead}
     2282 */
     2283DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     2284                                                    uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
     2285{
     2286    RT_NOREF(pDevIns);
     2287    return devpciR3CommonConfigReadWorker(pPciDev, uAddress, cb, pu32Value);
    22492288}
    22502289
    … …  
    22542293 *
    22552294 * @returns VBox status code.
     2295 * @param   pDevIns             The PCI bus device instance.
    22562296 * @param   pDev                The PCI device.
    22572297 * @param   iRegion             The region to unmap.
    22582298 */
    2259 static int devpciR3UnmapRegion(PPDMPCIDEV pDev, int iRegion)
     2299static int devpciR3UnmapRegion(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, int iRegion)
    22602300{
    22612301    PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
    … …  
    22752315        else
    22762316        {
    2277             PDEVPCIBUS pBus       = pDev->Int.s.CTX_SUFF(pBus);
    2278             RTGCPHYS   GCPhysBase = pRegion->addr;
    2279             if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
     2317            PDEVPCIBUSCC pBusCC     = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     2318            RTGCPHYS     GCPhysBase = pRegion->addr;
     2319            if (pBusCC->pPciHlpR3->pfnIsMMIOExBase(pDevIns, pDev->Int.s.pDevInsR3, GCPhysBase))
    22802320            {
    22812321                /* unmap it. */
    … …  
    22992339 *
    23002340 * @returns VINF_SUCCESS of DBGFSTOP result.
     2341 * @param   pDevIns             The PCI bus device instance.
    23012342 * @param   pPciDev             The PCI device to update the mappings for.
    23022343 * @param   fP2PBridge          Whether this is a PCI to PCI bridge or not.
    23032344 */
    2304 static VBOXSTRICTRC devpciR3UpdateMappings(PPDMPCIDEV pPciDev, bool fP2PBridge)
     2345static VBOXSTRICTRC devpciR3UpdateMappings(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, bool fP2PBridge)
    23052346{
    23062347    /* safe, only needs to go to the config space array */
    … …  
    24062447                         pPciDev->pszNameR3, iRegion, pRegion->addr, uNew, cbRegion, cbRegion));
    24072448
    2408                 devpciR3UnmapRegion(pPciDev, iRegion);
     2449                devpciR3UnmapRegion(pDevIns, pPciDev, iRegion);
    24092450                pRegion->addr = uNew;
    24102451                if (uNew != INVALID_PCI_ADDRESS)
    24112452                {
    24122453                    int rc = pRegion->map_func(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, uNew, cbRegion,
    2413                                                (PCIADDRESSSPACE)(pRegion->type));
     2454                                               (PCIADDRESSSPACE)pRegion->type);
    24142455                    AssertRC(rc);
    24152456                }
    … …  
    25462587
    25472588/**
    2548  * @callback_method_impl{PFNPCICONFIGWRITE,
    2549  *      Default config space write callback.}
     2589 * Writes config space for a device, ignoring interceptors.
    25502590 *
    25512591 * See paragraph 7.5 of PCI Express specification (p. 349) for
    25522592 * definition of registers and their writability policy.
    25532593 */
    2554 DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    2555                                                             uint32_t uAddress, uint32_t u32Value, unsigned cb)
    2556 {
    2557     NOREF(pDevIns);
    2558     Assert(cb <= 4);
    2559     VBOXSTRICTRC rcRet = VINF_SUCCESS;
     2594DECLHIDDEN(VBOXSTRICTRC) devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
     2595                                                         PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value)
     2596{
     2597    Assert(cb <= 4 && cb != 3);
     2598    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    25602599
    25612600    if (uAddress + cb <= 256)
    … …  
    25662605        if (   pciDevIsMsiCapable(pPciDev)
    25672606            && uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
    2568             MsiR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
    2569                                 pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
    2570                                 pPciDev, uAddress, u32Value, cb);
     2607            MsiR3PciConfigWrite(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, uAddress, u32Value, cb);
    25712608        else if (   pciDevIsMsixCapable(pPciDev)
    25722609                 && uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
    2573             MsixR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
    2574                                  pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
    2575                                  pPciDev, uAddress, u32Value, cb);
     2610            MsixR3PciConfigWrite(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, uAddress, u32Value, cb);
    25762611        else
    25772612        {
    … …  
    26842719             */
    26852720            if (fUpdateMappings)
    2686                 rcRet = devpciR3UpdateMappings(pPciDev, fP2PBridge);
     2721                rcStrict = devpciR3UpdateMappings(pDevIns, pPciDev, fP2PBridge);
    26872722        }
    26882723    }
    … …  
    26932728        AssertMsgFailed(("Write after end of PCI config space\n"));
    26942729
    2695     return rcRet;
     2730    return rcStrict;
     2731}
     2732
     2733
     2734/**
     2735 * @interface_method_impl{PDMPCIBUSREGR3,pfnConfigWrite}
     2736 */
     2737DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     2738                                                     uint32_t uAddress, unsigned cb, uint32_t u32Value)
     2739{
     2740    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     2741    return devpciR3CommonConfigWriteWorker(pDevIns, pBusCC, pPciDev, uAddress, cb, u32Value);
    26962742}
    26972743
    … …  
    29763022 * @interface_method_impl{PDMDEVREG,pfnConstruct}
    29773023 */
    2978 static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE  pCfg)
     3024static DECLCALLBACK(int) ich9pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE  pCfg)
    29793025{
    29803026    RT_NOREF1(iInstance);
    … …  
    30193065     * Init data.
    30203066     */
    3021     PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    3022     PDEVPCIBUS  pBus     = &pPciRoot->PciBus;
     3067    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     3068    PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
     3069    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     3070
    30233071    /* Zero out everything */
    3024     memset(pPciRoot, 0, sizeof(*pPciRoot));
     3072    Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot)));
     3073    memset(pPciRoot, 0, sizeof(*pPciRoot)); /** @todo unnecessary as instance data is always set to zero by the allocator, see assertion above. */
     3074
    30253075    /* And fill values */
    30263076    if (!fUseIoApic)
    … …  
    30363086                                N_("Configuration error: Failed to read \"McfgLength\""));
    30373087
    3038     pPciRoot->fUseIoApic = fUseIoApic;
    3039     pPciRoot->pDevInsR3 = pDevIns;
    3040     pPciRoot->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3041     pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3042 
    3043     pPciRoot->PciBus.fTypePiix3  = false;
    3044     pPciRoot->PciBus.fTypeIch9   = true;
    3045     pPciRoot->PciBus.fPureBridge = false;
    3046     pPciRoot->PciBus.pDevInsR3 = pDevIns;
    3047     pPciRoot->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3048     pPciRoot->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     3088    pBusCC->pDevInsR3             = pDevIns;
     3089    pPciRoot->fUseIoApic          = fUseIoApic;
     3090    pPciRoot->PciBus.fTypePiix3   = false;
     3091    pPciRoot->PciBus.fTypeIch9    = true;
     3092    pPciRoot->PciBus.fPureBridge  = false;
    30493093    pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pPciRoot->PciBus.apDevices));
    30503094    AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
    … …  
    30533097     * Register bus
    30543098     */
    3055     PDMPCIBUSREG PciBusReg;
    3056     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
    3057     PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
    3058     PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
    3059     PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
    3060     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
    3061     PciBusReg.pfnSetIrqR3             = ich9pciSetIrq;
    3062     PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pciSetIrq" : NULL;
    3063     PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pciSetIrq" : NULL;
    3064     rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
     3099    PDMPCIBUSREGCC PciBusReg;
     3100    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
     3101    PciBusReg.pfnRegisterR3              = pciR3MergedRegister;
     3102    PciBusReg.pfnRegisterMsiR3           = ich9pciRegisterMsi;
     3103    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
     3104    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
     3105    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
     3106    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
     3107    PciBusReg.pfnSetIrqR3                = ich9pciSetIrq;
     3108    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
     3109    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
    30653110    if (RT_FAILURE(rc))
    3066         return PDMDEV_SET_ERROR(pDevIns, rc,
    3067                                 N_("Failed to register ourselves as a PCI Bus"));
     3111        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
    30683112    Assert(pBus->iBus == 0);
    3069     if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
     3113    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
    30703114        return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
    30713115                                   N_("PCI helper version mismatch; got %#x expected %#x"),
    3072                                    pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    3073 
    3074     pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
    3075     pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
     3116                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    30763117
    30773118    /*
    … …  
    31773218 * @interface_method_impl{PDMDEVREG,pfnDestruct}
    31783219 */
    3179 static DECLCALLBACK(int) ich9pciDestruct(PPDMDEVINS pDevIns)
     3220static DECLCALLBACK(int) ich9pciR3Destruct(PPDMDEVINS pDevIns)
    31803221{
    31813222    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    … …  
    31893230
    31903231
    3191 void devpciR3ResetDevice(PPDMPCIDEV pDev)
     3232/**
     3233 * @param   pDevIns             The PCI bus device instance.
     3234 * @param   pDev                The PCI device to reset.
     3235 */
     3236void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev)
    31923237{
    31933238    /* Clear regions */
    … …  
    32003245                            == PCI_ADDRESS_SPACE_BAR64;
    32013246
    3202         devpciR3UnmapRegion(pDev, iRegion);
     3247        devpciR3UnmapRegion(pDevIns, pDev, iRegion);
    32033248
    32043249        if (f64Bit)
    … …  
    32133258    else
    32143259    {
    3215         devpciR3SetWord(pDev, VBOX_PCI_COMMAND,
     3260        devpciR3SetWord(pDevIns, pDev, VBOX_PCI_COMMAND,
    32163261                          devpciR3GetWord(pDev, VBOX_PCI_COMMAND)
    32173262                        & ~(VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY |
    … …  
    32233268        if (!pciDevIsPci2PciBridge(pDev))
    32243269        {
    3225             devpciR3SetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
    3226             devpciR3SetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
     3270            devpciR3SetByte(pDevIns, pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
     3271            devpciR3SetByte(pDevIns, pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
    32273272        }
    32283273
    32293274        /* Reset MSI message control. */
    32303275        if (pciDevIsMsiCapable(pDev))
    3231         {
    3232             devpciR3SetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
     3276            devpciR3SetWord(pDevIns, pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
    32333277                            devpciR3GetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL) & 0xff8e);
    3234         }
    32353278
    32363279        /* Reset MSI-X message control. */
    32373280        if (pciDevIsMsixCapable(pDev))
    3238         {
    3239             devpciR3SetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
     3281            devpciR3SetWord(pDevIns, pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
    32403282                            devpciR3GetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL) & 0x3fff);
    3241         }
    32423283    }
    32433284}
    … …  
    32863327    {
    32873328        if (pBus->apDevices[uDevFn])
    3288             devpciR3ResetDevice(pBus->apDevices[uDevFn]);
     3329            devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
    32893330    }
    32903331
    … …  
    32993340    if (pBus->iBus != 0)
    33003341    {
    3301         devpciR3SetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
    3302         devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
    3303         devpciR3SetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
     3342        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
     3343        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
     3344        devpciR3SetByte(pDevIns, &pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
    33043345        /* Not resetting the address decoders of the bridge to 0, since the
    33053346         * PCI-to-PCI Bridge spec says that there is no default value. */
    … …  
    33243365{
    33253366    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    3326 
    3327     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3328     pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
    33293367
    33303368    /* Relocate RC pointers for the attached pci devices. */
    … …  
    33473385DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    33483386{
    3349     PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    3350     pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3351 
    33523387    AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
    33533388    devpciR3BusRelocate(pDevIns, offDelta);
    … …  
    33683403}
    33693404
     3405/**
     3406 * @interface_method_impl{PDMDEVREG,pfnDestruct}
     3407 */
     3408static DECLCALLBACK(int) ich9pcibridgeR3Destruct(PPDMDEVINS pDevIns)
     3409{
     3410    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     3411    if (pBus->papBridgesR3)
     3412    {
     3413        PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
     3414        pBus->papBridgesR3 = NULL;
     3415    }
     3416    return VINF_SUCCESS;
     3417}
     3418
    33703419
    33713420/**
    33723421 * @interface_method_impl{PDMDEVREG,pfnConstruct}
    33733422 */
    3374 static DECLCALLBACK(int)   ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
    3375                                                   int        iInstance,
    3376                                                   PCFGMNODE  pCfg)
     3423static DECLCALLBACK(int) ich9pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    33773424{
    33783425    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    … …  
    34213468     * Init data and register the PCI bus.
    34223469     */
    3423     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     3470    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     3471    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    34243472    pBus->fTypePiix3  = false;
    34253473    pBus->fTypeIch9   = true;
    34263474    pBus->fPureBridge = true;
    3427     pBus->pDevInsR3 = pDevIns;
    3428     pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3429     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     3475    pBusCC->pDevInsR3 = pDevIns;
    34303476    /** @todo r=klaus figure out how to extend this to allow PCIe config space
    34313477     * extension, which increases the config space from 256 bytes to 4K. */
    … …  
    34333479    AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
    34343480
    3435     PDMPCIBUSREG PciBusReg;
    3436     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
    3437     PciBusReg.pfnRegisterR3           = pcibridgeR3MergedRegisterDevice;
    3438     PciBusReg.pfnRegisterMsiR3        = ich9pciRegisterMsi;
    3439     PciBusReg.pfnIORegionRegisterR3   = devpciR3CommonIORegionRegister;
    3440     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
    3441     PciBusReg.pfnSetIrqR3             = ich9pcibridgeSetIrq;
    3442     PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
    3443     PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
    3444     rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
     3481    PDMPCIBUSREGCC PciBusReg;
     3482    PciBusReg.u32Version                 = PDM_PCIBUSREGCC_VERSION;
     3483    PciBusReg.pfnRegisterR3              = pcibridgeR3MergedRegisterDevice;
     3484    PciBusReg.pfnRegisterMsiR3           = ich9pciRegisterMsi;
     3485    PciBusReg.pfnIORegionRegisterR3      = devpciR3CommonIORegionRegister;
     3486    PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
     3487    PciBusReg.pfnConfigWrite             = devpciR3CommonConfigWrite;
     3488    PciBusReg.pfnConfigRead              = devpciR3CommonConfigRead;
     3489    PciBusReg.pfnSetIrqR3                = ich9pcibridgeSetIrq;
     3490    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
     3491    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
    34453492    if (RT_FAILURE(rc))
    3446         return PDMDEV_SET_ERROR(pDevIns, rc,
    3447                                 N_("Failed to register ourselves as a PCI Bus"));
     3493        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
    34483494    Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
    3449     if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
     3495    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
    34503496        return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
    34513497                                   N_("PCI helper version mismatch; got %#x expected %#x"),
    3452                                    pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
    3453 
    3454     pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
    3455     pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
     3498                                   pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
     3499
    34563500    LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
    34573501
    … …  
    35743618}
    35753619
    3576 /**
    3577  * @interface_method_impl{PDMDEVREG,pfnDestruct}
    3578  */
    3579 static DECLCALLBACK(int) ich9pcibridgeDestruct(PPDMDEVINS pDevIns)
    3580 {
    3581     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    3582     if (pBus->papBridgesR3)
    3583     {
    3584         PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
    3585         pBus->papBridgesR3 = NULL;
    3586     }
    3587     return VINF_SUCCESS;
    3588 }
    3589 
    3590 #endif /* IN_RING3 */
     3620#else  /* !IN_RING3 */
     3621
     3622/**
     3623 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
     3624 */
     3625DECLCALLBACK(int) ich9pciRZConstruct(PPDMDEVINS pDevIns)
     3626{
     3627    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     3628    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     3629    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     3630
     3631    PDMPCIBUSREGCC PciBusReg;
     3632    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
     3633    PciBusReg.iBus          = pGlobals->PciBus.iBus;
     3634    PciBusReg.pfnSetIrq     = ich9pciSetIrq;
     3635    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
     3636    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     3637    AssertRC(rc);
     3638
     3639    /* Disable default device locking. */
     3640    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3641    AssertRCReturn(rc, rc);
     3642
     3643    return rc;
     3644}
     3645
     3646
     3647/**
     3648 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
     3649 */
     3650DECLCALLBACK(int) ich9pcibridgeRZConstruct(PPDMDEVINS pDevIns)
     3651{
     3652    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     3653    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     3654    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     3655
     3656    PDMPCIBUSREGCC PciBusReg;
     3657    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
     3658    PciBusReg.iBus          = pBus->iBus;
     3659    PciBusReg.pfnSetIrq     = ich9pcibridgeSetIrq;
     3660    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
     3661    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     3662    AssertRC(rc);
     3663
     3664    /* Disable default device locking. */
     3665    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3666    AssertRCReturn(rc, rc);
     3667
     3668    return rc;
     3669}
     3670
     3671#endif /* !IN_RING3 */
    35913672
    35923673/**
    … …  
    36033684    /* .uSharedVersion = */         42,
    36043685    /* .cbInstanceShared = */       sizeof(DEVPCIROOT),
    3605     /* .cbInstanceCC = */           0,
    3606     /* .cbInstanceRC = */           0,
     3686    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
     3687    /* .cbInstanceRC = */           sizeof(DEVPCIBUSRC),
    36073688    /* .cMaxPciDevices = */         1,
    36083689    /* .cMaxMsixVectors = */        0,
    … …  
    36113692    /* .pszRCMod = */               "VBoxDDRC.rc",
    36123693    /* .pszR0Mod = */               "VBoxDDR0.r0",
    3613     /* .pfnConstruct = */           ich9pciConstruct,
    3614     /* .pfnDestruct = */            ich9pciDestruct,
     3694    /* .pfnConstruct = */           ich9pciR3Construct,
     3695    /* .pfnDestruct = */            ich9pciR3Destruct,
    36153696    /* .pfnRelocate = */            devpciR3RootRelocate,
    36163697    /* .pfnMemSetup = */            NULL,
    … …  
    36353716#elif defined(IN_RING0)
    36363717    /* .pfnEarlyConstruct = */      NULL,
    3637     /* .pfnConstruct = */           NULL,
     3718    /* .pfnConstruct = */           ich9pciRZConstruct,
    36383719    /* .pfnDestruct = */            NULL,
    36393720    /* .pfnFinalDestruct = */       NULL,
    … …  
    36483729    /* .pfnReserved7 = */           NULL,
    36493730#elif defined(IN_RC)
    3650     /* .pfnConstruct = */           NULL,
     3731    /* .pfnConstruct = */           ich9pciRZConstruct,
    36513732    /* .pfnReserved0 = */           NULL,
    36523733    /* .pfnReserved1 = */           NULL,
    … …  
    36773758    /* .uSharedVersion = */         42,
    36783759    /* .cbInstanceShared = */       sizeof(DEVPCIBUS),
    3679     /* .cbInstanceCC = */           0,
     3760    /* .cbInstanceCC = */           sizeof(CTX_SUFF(DEVPCIBUS)),
    36803761    /* .cbInstanceRC = */           0,
    36813762    /* .cMaxPciDevices = */         1,
    … …  
    36853766    /* .pszRCMod = */               "VBoxDDRC.rc",
    36863767    /* .pszR0Mod = */               "VBoxDDR0.r0",
    3687     /* .pfnConstruct = */           ich9pcibridgeConstruct,
    3688     /* .pfnDestruct = */            ich9pcibridgeDestruct,
     3768    /* .pfnConstruct = */           ich9pcibridgeR3Construct,
     3769    /* .pfnDestruct = */            ich9pcibridgeR3Destruct,
    36893770    /* .pfnRelocate = */            devpciR3BusRelocate,
    36903771    /* .pfnMemSetup = */            NULL,
    … …  
    37093790#elif defined(IN_RING0)
    37103791    /* .pfnEarlyConstruct = */      NULL,
    3711     /* .pfnConstruct = */           NULL,
     3792    /* .pfnConstruct = */           ich9pcibridgeRZConstruct,
    37123793    /* .pfnDestruct = */            NULL,
    37133794    /* .pfnFinalDestruct = */       NULL,
    … …  
    37223803    /* .pfnReserved7 = */           NULL,
    37233804#elif defined(IN_RC)
    3724     /* .pfnConstruct = */           NULL,
     3805    /* .pfnConstruct = */           ich9pcibridgeRZConstruct,
    37253806    /* .pfnReserved0 = */           NULL,
    37263807    /* .pfnReserved1 = */           NULL,

  • trunk/src/VBox/Devices/Bus/DevPciInternal.h

    r76565 r80943  
    2929
    3030/**
    31  * PCI bus instance (common to both).
     31 * PCI bus shared instance data (common to both PCI buses).
    3232 */
    3333typedef struct DEVPCIBUS
    … …  
    4242    uint32_t                fTypePiix3 : 1;
    4343    /** Set if ICH9 type. */
    44     uint32_t                fTypeIch9: 1;
     44    uint32_t                fTypeIch9 : 1;
    4545    /** Set if this is a pure bridge, i.e. not part of DEVPCIGLOBALS struct. */
    4646    uint32_t                fPureBridge : 1;
    … …  
    4848    uint32_t                uReservedConfigFlags : 29;
    4949
     50    /** Array of bridges attached to the bus. */
     51    R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
     52    /** Cache line align apDevices. */
     53    uint32_t                au32Alignment1[HC_ARCH_BITS == 32 ? 3+8 : 2+8];
     54    /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
     55    R3PTRTYPE(PPDMPCIDEV)   apDevices[256];
     56
     57    /** The PCI device for the PCI bridge. */
     58    PDMPCIDEV               PciDev;
     59} DEVPCIBUS;
     60/** Pointer to PCI bus shared instance data. */
     61typedef DEVPCIBUS *PDEVPCIBUS;
     62
     63/**
     64 * PCI bus ring-3 instance data (common to both PCI buses).
     65 */
     66typedef struct DEVPCIBUSR3
     67{
    5068    /** R3 pointer to the device instance. */
    5169    PPDMDEVINSR3            pDevInsR3;
    5270    /** Pointer to the PCI R3  helpers. */
    5371    PCPDMPCIHLPR3           pPciHlpR3;
    54 
     72} DEVPCIBUSR3;
     73/** Pointer to PCI bus ring-3 instance data. */
     74typedef DEVPCIBUSR3 *PDEVPCIBUSR3;
     75
     76/**
     77 * PCI bus ring-0 instance data (common to both PCI buses).
     78 */
     79typedef struct DEVPCIBUSR0
     80{
    5581    /** R0 pointer to the device instance. */
    5682    PPDMDEVINSR0            pDevInsR0;
    5783    /** Pointer to the PCI R0 helpers. */
    5884    PCPDMPCIHLPR0           pPciHlpR0;
    59 
    60     /** RC pointer to the device instance. */
     85} DEVPCIBUSR0;
     86/** Pointer to PCI bus ring-0 instance data. */
     87typedef DEVPCIBUSR0 *PDEVPCIBUSR0;
     88
     89/**
     90 * PCI bus raw-mode instance data (common to both PCI buses).
     91 */
     92typedef struct DEVPCIBUSRC
     93{
     94    /** R0 pointer to the device instance. */
    6195    PPDMDEVINSRC            pDevInsRC;
    62     /** Pointer to the PCI RC helpers. */
     96    /** Pointer to the PCI raw-mode helpers. */
    6397    PCPDMPCIHLPRC           pPciHlpRC;
    64 
    65     /** Array of bridges attached to the bus. */
    66     R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
    67 #if HC_ARCH_BITS == 32
    68     uint32_t                au32Alignment1[5]; /**< Cache line align apDevices. */
    69 #endif
    70     /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
    71     R3PTRTYPE(PPDMPCIDEV)   apDevices[256];
    72 
    73     /** The PCI device for the PCI bridge. */
    74     PDMPCIDEV               PciDev;
    75 } DEVPCIBUS;
    76 /** Pointer to a PCI bus instance.   */
    77 typedef DEVPCIBUS *PDEVPCIBUS;
     98} DEVPCIBUSRC;
     99/** Pointer to PCI bus raw-mode instance data. */
     100typedef DEVPCIBUSRC *PDEVPCIBUSRC;
     101
     102/** DEVPCIBUSR3, DEVPCIBUSR0 or DEVPCIBUSRC depending on context.  */
     103typedef CTX_SUFF(DEVPCIBUS)  DEVPCIBUSCC;
     104/** PDEVPCIBUSR3, PDEVPCIBUSR0 or PDEVPCIBUSRC depending on context.  */
     105typedef CTX_SUFF(PDEVPCIBUS) PDEVPCIBUSCC;
    78106
    79107
    … …  
    99127
    100128/**
    101  * PCI Globals - This is the host-to-pci bridge and the root bus.
     129 * PCI Globals - This is the host-to-pci bridge and the root bus, shared data.
    102130 *
    103131 * @note Only used by the root bus, not the bridges.
    … …  
    109137    DEVPCIBUS           PciBus;
    110138
    111     /** R3 pointer to the device instance. */
    112     PPDMDEVINSR3        pDevInsR3;
    113     /** R0 pointer to the device instance. */
    114     PPDMDEVINSR0        pDevInsR0;
    115     /** RC pointer to the device instance. */
    116     PPDMDEVINSRC        pDevInsRC;
    117 
    118139    /** I/O APIC usage flag (always true of ICH9, see constructor). */
    119140    bool                fUseIoApic;
    120141    /** Reserved for future config flags. */
    121     bool                afFutureFlags[3];
     142    bool                afFutureFlags[3+4];
    122143    /** Physical address of PCI config space MMIO region. */
    123144    uint64_t            u64PciConfigMMioAddress;
    … …  
    163184/** Pointer to PCI device globals. */
    164185typedef DEVPCIROOT *PDEVPCIROOT;
    165 
    166 
    167186/** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
    168187#define DEVINS_2_DEVPCIBUS(pDevIns)     (&PDMINS_2_DATA(pDevIns, PDEVPCIROOT)->PciBus)
    … …  
    176195#define PCI_LOCK(pDevIns, rc) \
    177196    do { \
    178         int rc2 = DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
     197        int rc2 = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
    179198        if (rc2 != VINF_SUCCESS) \
    180199            return rc2; \
    181200    } while (0)
    182201#define PCI_UNLOCK(pDevIns) \
    183     DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
     202    PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
    184203
    185204
    … …  
    192211DECLCALLBACK(int)  devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
    193212                                                  PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback);
    194 DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    195                                                     PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    196                                                     PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld);
    197 DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb);
    198 DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    199                                                             uint32_t uAddress, uint32_t u32Value, unsigned cb);
    200 void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
     213DECLCALLBACK(void) devpciR3CommonInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     214                                                         PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite);
     215DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     216                                                    uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
     217DECLHIDDEN(VBOXSTRICTRC)   devpciR3CommonConfigReadWorker(PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value);
     218DECLCALLBACK(VBOXSTRICTRC) devpciR3CommonConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     219                                                     uint32_t uAddress, unsigned cb, uint32_t u32Value);
     220DECLHIDDEN(VBOXSTRICTRC)   devpciR3CommonConfigWriteWorker(PPDMDEVINS pDevIns, PDEVPCIBUSCC pBusCC,
     221                                                           PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value);
     222void devpciR3CommonRestoreConfig(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint8_t const *pbSrcConfig);
    201223int  devpciR3CommonRestoreRegions(PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState);
    202 void devpciR3ResetDevice(PPDMPCIDEV pDev);
    203 void devpciR3BiosInitSetRegionAddress(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
     224void devpciR3ResetDevice(PPDMDEVINS pDevIns, PPDMPCIDEV pDev);
     225void devpciR3BiosInitSetRegionAddress(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, int iRegion, uint64_t addr);
    204226uint32_t devpciR3GetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb);
    205 void devpciR3SetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
     227void devpciR3SetCfg(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb);
    206228
    207229DECLINLINE(uint8_t) devpciR3GetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
    … …  
    220242}
    221243
    222 DECLINLINE(void) devpciR3SetByte(PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
    223 {
    224     devpciR3SetCfg(pPciDev, iRegister, u8, 1);
    225 }
    226 
    227 DECLINLINE(void) devpciR3SetWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
    228 {
    229     devpciR3SetCfg(pPciDev, iRegister, u16, 2);
    230 }
    231 
    232 DECLINLINE(void) devpciR3SetDWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
    233 {
    234     devpciR3SetCfg(pPciDev, iRegister, u32, 4);
     244DECLINLINE(void) devpciR3SetByte(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
     245{
     246    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u8, 1);
     247}
     248
     249DECLINLINE(void) devpciR3SetWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
     250{
     251    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u16, 2);
     252}
     253
     254DECLINLINE(void) devpciR3SetDWord(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
     255{
     256    devpciR3SetCfg(pDevIns, pPciDev, iRegister, u32, 4);
    235257}
    236258

  • trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h

    r80531 r80943  
    6060 *                          function number (0-7).
    6161 * @param   pszName         Device name (static but not unique).
    62  * @param   pfnConfigRead   The default config read method.
    63  * @param   pfnConfigWrite  The default config read method.
    6462 *
    6563 * @remarks Caller enters the PDM critical section.
    6664 */
    6765static int pciR3MergedRegisterDeviceOnBus(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint32_t fFlags,
    68                                           uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName,
    69                                           PFNPCICONFIGREAD pfnConfigRead, PFNPCICONFIGWRITE pfnConfigWrite)
     66                                          uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
    7067{
    7168    /*
    … …  
    197194    pPciDev->Int.s.pBusR0           = PDMINS_2_DATA_R0PTR(pDevIns);
    198195    pPciDev->Int.s.pBusRC           = PDMINS_2_DATA_RCPTR(pDevIns);
    199     pPciDev->Int.s.pfnConfigRead    = pfnConfigRead;
    200     pPciDev->Int.s.pfnConfigWrite   = pfnConfigWrite;
     196    pPciDev->Int.s.pfnConfigRead    = NULL;
     197    pPciDev->Int.s.pfnConfigWrite   = NULL;
    201198
    202199    /* Remember and mark bridges. */
    … …  
    225222    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    226223    AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
    227     return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
    228                                           devpciR3CommonDefaultConfigRead, devpciR3CommonDefaultConfigWrite);
     224    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
    229225}
    230226
    … …  
    237233{
    238234    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    239     return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
    240                                           devpciR3CommonDefaultConfigRead, devpciR3CommonDefaultConfigWrite);
    241 }
    242 
     235    return pciR3MergedRegisterDeviceOnBus(pDevIns, pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
     236}
     237

  • trunk/src/VBox/Devices/Bus/MsiCommon.cpp

    r76553 r80943  
    3333    uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
    3434#ifdef IN_RING3
    35     if (pciDevIsPassthrough(pDev))
    36         return pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2);
     35    if (pciDevIsPassthrough(pDev) && pDev->Int.s.pfnConfigRead)
     36    {
     37        uint32_t u32Value = 0;
     38        VBOXSTRICTRC rcStrict = pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2, &u32Value);
     39        AssertRCSuccess(rcStrict);
     40        return (uint16_t)u32Value;
     41    }
    3742#endif
    3843    return PCIDevGetWord(pDev, idxMessageControl);

  • trunk/src/VBox/Devices/Makefile.kmk

    r80732 r80943  
    524524  VBoxDD_DEFS           += VBOX_WITH_VIRTIO_SCSI
    525525  VBoxDD_SOURCES        += \
    526     Virtio/Virtio_1_0.cpp \
     526        Virtio/Virtio_1_0.cpp \
    527527        Storage/DevVirtioSCSI.cpp
    528528 endif

  • trunk/src/VBox/Devices/PC/DevACPI.cpp

    r80704 r80943  
    435435    /** Pointer to the driver connector interface. */
    436436    R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
    437 
    438     /** Pointer to default PCI config read function. */
    439     R3PTRTYPE(PFNPCICONFIGREAD)   pfnAcpiPciConfigRead;
    440     /** Pointer to default PCI config write function. */
    441     R3PTRTYPE(PFNPCICONFIGWRITE)  pfnAcpiPciConfigWrite;
    442437
    443438    /** Number of custom ACPI tables */
    … …  
    33583353 * @callback_method_impl{FNPCICONFIGREAD}
    33593354 */
    3360 static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
    3361 {
    3362     ACPIState *pThis   = PDMINS_2_DATA(pDevIns, ACPIState *);
    3363 
    3364     Log2(("acpi: PCI config read: 0x%x (%d)\n", uAddress, cb));
    3365     return pThis->pfnAcpiPciConfigRead(pDevIns, pPciDev, uAddress, cb);
     3355static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     3356                                                      uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
     3357{
     3358    VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
     3359    Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
     3360    return rcStrict;
    33663361}
    33673362
    … …  
    33693364 * @callback_method_impl{FNPCICONFIGWRITE}
    33703365 */
    3371 static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
    3372                                                        uint32_t u32Value, unsigned cb)
     3366static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     3367                                                       uint32_t uAddress, unsigned cb, uint32_t u32Value)
    33733368{
    33743369    ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
    … …  
    33833378    }
    33843379
    3385     VBOXSTRICTRC rcBase = pThis->pfnAcpiPciConfigWrite(pDevIns, pPciDev, uAddress, u32Value, cb);
     3380    VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
    33863381
    33873382    /* Assume that the base address is only changed when the corresponding
    … …  
    34183413
    34193414    DEVACPI_UNLOCK(pThis);
    3420     return rcBase;
     3415    return rcStrict;
    34213416}
    34223417
    … …  
    41424137        return rc;
    41434138
    4144     PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->dev,
    4145                                    acpiR3PciConfigRead,  &pThis->pfnAcpiPciConfigRead,
    4146                                    acpiR3PciConfigWrite, &pThis->pfnAcpiPciConfigWrite);
     4139    rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, &pThis->dev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
     4140    AssertRCReturn(rc, rc);
    41474141
    41484142    /*

  • trunk/src/VBox/Devices/PC/DevLpc-new.cpp

    r80704 r80943  
    5959    /** Explicit padding. */
    6060    uint8_t         abPadding[HC_ARCH_BITS == 32 ? 2 : 6];
    61 
    62     /** Pointer to generic PCI config reader. */
    63     R3PTRTYPE(PFNPCICONFIGREAD)  pfnPciConfigReadFallback;
    64     /** Pointer to generic PCI config write. */
    65     R3PTRTYPE(PFNPCICONFIGWRITE) pfnPciConfigWriteFallback;
    6661
    6762    /** Number of MMIO reads. */
    … …  
    140135 * @callback_method_impl{FNPCICONFIGREAD}
    141136 */
    142 static DECLCALLBACK(uint32_t) lpcPciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
     137static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     138                                                     uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
    143139{
    144140    PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
    … …  
    146142
    147143    STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
    148     uint32_t uValue = pThis->pfnPciConfigReadFallback(pDevIns, pPciDev, uAddress, cb);
     144    VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
    149145    switch (cb)
    150146    {
    151         case 1: Log(("lpcPciConfigRead: %#04x -> %#04x\n",  uAddress, uValue)); break;
    152         case 2: Log(("lpcPciConfigRead: %#04x -> %#06x\n",  uAddress, uValue)); break;
    153         case 4: Log(("lpcPciConfigRead: %#04x -> %#010x\n", uAddress, uValue)); break;
    154     }
    155     return uValue;
     147        case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n",  uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
     148        case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n",  uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
     149        case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
     150    }
     151    return rcStrict;
    156152}
    157153
    … …  
    160156 * @callback_method_impl{FNPCICONFIGWRITE}
    161157 */
    162 static DECLCALLBACK(VBOXSTRICTRC)
    163 lpcPciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, uint32_t u32Value, unsigned cb)
     158static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     159                                                      uint32_t uAddress, unsigned cb, uint32_t u32Value)
    164160{
    165161    PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
    … …  
    169165    switch (cb)
    170166    {
    171         case 1: Log(("lpcPciConfigWrite: %#04x <- %#04x\n",  uAddress, u32Value)); break;
    172         case 2: Log(("lpcPciConfigWrite: %#04x <- %#06x\n",  uAddress, u32Value)); break;
    173         case 4: Log(("lpcPciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
    174     }
    175 
    176     return pThis->pfnPciConfigWriteFallback(pDevIns, pPciDev, uAddress, u32Value, cb);
     167        case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n",  uAddress, u32Value)); break;
     168        case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n",  uAddress, u32Value)); break;
     169        case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
     170    }
     171
     172    return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
    177173}
    178174
    … …  
    354350                                31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
    355351    AssertRCReturn(rc, rc);
    356     PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->PciDev,
    357                                    lpcPciConfigRead, &pThis->pfnPciConfigReadFallback,
    358                                    lpcPciConfigWrite, &pThis->pfnPciConfigWriteFallback);
     352    rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, &pThis->PciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
     353    AssertRCReturn(rc, rc);
    359354
    360355    /*

  • trunk/src/VBox/Devices/VirtIO/Virtio_1_0.cpp

    r80931 r80943  
    545545 *
    546546 * @param   pVirtio     Virtio instance state
    547  * @param   fWrite      If write access (otherwise read access)
     547 * @param   fWrite      Set if write access, clear if read access.
    548548 * @param   pv          Pointer to location to write to or read from
    549549 * @param   cb          Number of bytes to read or write
    550550 */
    551 static int virtioCommonCfgAccessed(PVIRTIOSTATE pVirtio, int fWrite, off_t uOffset, unsigned cb, void const *pv)
     551static int virtioCommonCfgAccessed(PVIRTIOSTATE pVirtio, bool fWrite, off_t uOffset, unsigned cb, void const *pv)
    552552{
    553553    int rc = VINF_SUCCESS;
    … …  
    765765    {
    766766        uint32_t uOffset = GCPhysAddr - pVirtio->pGcPhysCommonCfg;
    767         virtioCommonCfgAccessed(pVirtio, 0 /* fWrite */, uOffset, cb, (void const *)pv);
     767        virtioCommonCfgAccessed(pVirtio, false /* fWrite */, uOffset, cb, (void const *)pv);
    768768    }
    769769    else
    … …  
    816816    {
    817817        uint32_t uOffset = GCPhysAddr - pVirtio->pGcPhysCommonCfg;
    818         virtioCommonCfgAccessed(pVirtio, 1 /* fWrite */, uOffset, cb, pv);
     818        virtioCommonCfgAccessed(pVirtio, true /* fWrite */, uOffset, cb, pv);
    819819    }
    820820    else
    … …  
    884884
    885885/**
    886   * Callback function for reading from the PCI configuration space.
    887   *
    888   * @returns The register value.
    889   * @param   pDevIns         Pointer to the device instance the PCI device
    890   *                          belongs to.
    891   * @param   pPciDev         Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
    892   * @param   uAddress        The configuration space register address. [0..4096]
    893   * @param   cb              The register size. [1,2,4]
    894   *
    895   * @remarks Called with the PDM lock held.  The device lock is NOT take because
    896   *          that is very likely be a lock order violation.
    897   */
    898 static DECLCALLBACK(uint32_t) virtioPciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    899                                        uint32_t uAddress, unsigned cb)
     886 * @callback_method_impl{FNPCICONFIGRead}
     887 */
     888static DECLCALLBACK(VBOXSTRICTRC) virtioR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     889                                                        uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
    900890{
    901891    PVIRTIOSTATE pVirtio = *PDMINS_2_DATA(pDevIns, PVIRTIOSTATE *);
    902 
     892    RT_NOREF(pPciDev);
     893
     894    /** @todo r=bird: this comparison just cannot be correct.   */
    903895    if (uAddress == (uint64_t)&pVirtio->pPciCfgCap->uPciCfgData)
    904896    {
    … …  
    909901        uint32_t uOffset = pVirtio->pPciCfgCap->pciCap.uOffset;
    910902        uint8_t  uBar    = pVirtio->pPciCfgCap->pciCap.uBar;
    911         uint32_t pv = 0;
     903        *pu32Value = 0;
    912904        if (uBar == VIRTIO_REGION_PCI_CAP)
    913             (void)virtioR3MmioRead(pDevIns, NULL, (RTGCPHYS)((uint32_t)pVirtio->pGcPhysPciCapBase + uOffset),
    914                                     &pv, uLength);
     905        {
     906            virtioR3MmioRead(pDevIns, NULL, (RTGCPHYS)((uint32_t)pVirtio->pGcPhysPciCapBase + uOffset), pu32Value, uLength);
     907            Log2Func(("virtio: Guest read  virtio_pci_cfg_cap.pci_cfg_data, bar=%d, offset=%d, length=%d, result=%d\n",
     908                      uBar, uOffset, uLength, *pu32Value));
     909        }
    915910        else
    916         {
    917911            Log2Func(("Guest read virtio_pci_cfg_cap.pci_cfg_data using unconfigured BAR. Ignoring"));
    918             return 0;
    919         }
    920         Log2Func(("virtio: Guest read  virtio_pci_cfg_cap.pci_cfg_data, bar=%d, offset=%d, length=%d, result=%d\n",
    921                 uBar, uOffset, uLength, pv));
    922         return pv;
    923     }
    924     return pVirtio->pfnPciConfigReadOld(pDevIns, pPciDev, uAddress, cb);
    925 }
    926 
    927 /**
    928  * Callback function for writing to the PCI configuration space.
    929  *
    930  * @returns VINF_SUCCESS or PDMDevHlpDBGFStop status.
    931  *
    932  * @param   pDevIns         Pointer to the device instance the PCI device
    933  *                          belongs to.
    934  * @param   pPciDev         Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
    935  * @param   uAddress        The configuration space register address. [0..4096]
    936  * @param   u32Value        The value that's being written. The number of bits actually used from
    937  *                          this value is determined by the cb parameter.
    938  * @param   cb              The register size. [1,2,4]
    939  *
    940  * @remarks Called with the PDM lock held.  The device lock is NOT take because
    941  *          that is very likely be a lock order violation.
    942  */
    943 static DECLCALLBACK(VBOXSTRICTRC) virtioPciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
    944                                         uint32_t uAddress, uint32_t u32Value, unsigned cb)
     912        return VINF_SUCCESS;
     913    }
     914    return VINF_PDM_PCI_DO_DEFAULT;
     915}
     916
     917/**
     918 * @callback_method_impl{FNPCICONFIGWRITE}
     919 */
     920static DECLCALLBACK(VBOXSTRICTRC) virtioR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     921                                                         uint32_t uAddress, unsigned cb, uint32_t u32Value)
    945922{
    946923    PVIRTIOSTATE pVirtio = *PDMINS_2_DATA(pDevIns, PVIRTIOSTATE *);
     924    RT_NOREF(pPciDev);
    947925
    948926    if (uAddress == pVirtio->uPciCfgDataOff)
    … …  
    955933        uint8_t  uBar    = pVirtio->pPciCfgCap->pciCap.uBar;
    956934        if (uBar == VIRTIO_REGION_PCI_CAP)
    957             (void)virtioR3MmioWrite(pDevIns, NULL, (RTGCPHYS)((uint32_t)pVirtio->pGcPhysPciCapBase + uOffset),
    958                                     (void *)&u32Value, uLength);
     935        {
     936            Assert(uLength <= sizeof(u32Value));
     937            virtioR3MmioWrite(pDevIns, NULL, (RTGCPHYS)((uint32_t)pVirtio->pGcPhysPciCapBase + uOffset), &u32Value, uLength);
     938        }
    959939        else
    960940        {
    … …  
    966946        return VINF_SUCCESS;
    967947    }
    968     return pVirtio->pfnPciConfigWriteOld(pDevIns, pPciDev, uAddress, u32Value, cb);
     948    return VINF_PDM_PCI_DO_DEFAULT;
    969949}
    970950
    … …  
    10971077    {
    10981078        RTMemFree(pVirtio);
    1099         return PDMDEV_SET_ERROR(pDevIns, rc,
    1100             N_("virtio: cannot register PCI Device")); /* can we put params in this error? */
     1079        return PDMDEV_SET_ERROR(pDevIns, rc, N_("virtio: cannot register PCI Device")); /* can we put params in this error? */
    11011080    }
    11021081
    … …  
    11071086    {
    11081087        RTMemFree(pVirtio);
    1109         return PDMDEV_SET_ERROR(pDevIns, rc,
    1110             N_("virtio: cannot register SSM callbacks"));
    1111     }
    1112 
    1113     PDMDevHlpPCISetConfigCallbacks(pDevIns, &pVirtio->dev,
    1114                 virtioPciConfigRead,  &pVirtio->pfnPciConfigReadOld,
    1115                 virtioPciConfigWrite, &pVirtio->pfnPciConfigWriteOld);
     1088        return PDMDEV_SET_ERROR(pDevIns, rc, N_("virtio: cannot register SSM callbacks"));
     1089    }
     1090
     1091    rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, &pVirtio->dev, virtioR3PciConfigRead, virtioR3PciConfigWrite);
     1092    AssertRCReturnStmt(rc, RTMemFree(pVirtio), rc);
    11161093
    11171094
    … …  
    12721249              "  pfnSSMDevLiveExec        = %p\n  pfnSSMDevSaveExec        = %p\n"
    12731250              "  pfnSSMDevLoadExec        = %p\n  pfnSSMDevLoadDone        = %p\n"
    1274               "  pfnPciConfigReadOld      = %p\n  pfnPciConfigWriteOld     = %p\n",
    12751251                    pcszCaller ? pcszCaller : "<unspecified>",
    12761252                    pVirtio->uDeviceFeatures, pVirtio->uDriverFeatures, pVirtio->uDeviceFeaturesSelect,
    … …  
    12831259                    pVirtio->virtioCallbacks.pfnVirtioDevCapWrite, pVirtio->virtioCallbacks.pfnSSMDevLiveExec,
    12841260                    pVirtio->virtioCallbacks.pfnSSMDevSaveExec, pVirtio->virtioCallbacks.pfnSSMDevLoadExec,
    1285                     pVirtio->virtioCallbacks.pfnSSMDevLoadDone, pVirtio->pfnPciConfigReadOld,
    1286                     pVirtio->pfnPciConfigWriteOld
     1261                    pVirtio->virtioCallbacks.pfnSSMDevLoadDone
    12871262    ));
    12881263
    … …  
    13391314    rc = SSMR3PutU64(pSSM,    (uint64_t)pVirtio->virtioCallbacks.pfnSSMDevLoadExec);
    13401315    rc = SSMR3PutU64(pSSM,    (uint64_t)pVirtio->virtioCallbacks.pfnSSMDevLoadDone);
    1341     rc = SSMR3PutU64(pSSM,    (uint64_t)pVirtio->pfnPciConfigReadOld);
    1342     rc = SSMR3PutU64(pSSM,    (uint64_t)pVirtio->pfnPciConfigWriteOld);
    13431316    rc = SSMR3PutGCPhys(pSSM, pVirtio->pGcPhysCommonCfg);
    13441317    rc = SSMR3PutGCPhys(pSSM, pVirtio->pGcPhysNotifyCap);
    … …  
    14011374        rc = SSMR3GetU64(pSSM,   (uint64_t *)&pVirtio->virtioCallbacks.pfnSSMDevLoadExec);
    14021375        rc = SSMR3GetU64(pSSM,   (uint64_t *)&pVirtio->virtioCallbacks.pfnSSMDevLoadDone);
    1403         rc = SSMR3GetU64(pSSM,   (uint64_t *)&pVirtio->pfnPciConfigReadOld);
    1404         rc = SSMR3GetU64(pSSM,   (uint64_t *)&pVirtio->pfnPciConfigWriteOld);
    14051376        rc = SSMR3GetGCPhys(pSSM, &pVirtio->pGcPhysCommonCfg);
    14061377        rc = SSMR3GetGCPhys(pSSM, &pVirtio->pGcPhysNotifyCap);

  • trunk/src/VBox/Devices/VirtIO/Virtio_1_0_impl.h

    r80931 r80943  
    177177    VIRTQSTATE                virtqState[VIRTQ_MAX_CNT];         /**< Local impl-specific queue context         */
    178178    VIRTIOCALLBACKS           virtioCallbacks;                   /**< Callback vectors to client                */
    179 
    180     PFNPCICONFIGREAD          pfnPciConfigReadOld;               /**< Prev rd. cb. intercepting PCI Cfg I/O     */
    181     PFNPCICONFIGWRITE         pfnPciConfigWriteOld;              /**< Prev wr. cb. intercepting PCI Cfg I/O     */
    182179
    183180    PVIRTIO_PCI_CFG_CAP_T     pPciCfgCap;                        /**< Pointer to struct in configuration area   */

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r80396 r80943  
    218218    GEN_CHECK_OFF(DEVPCIBUS, apDevices);
    219219    GEN_CHECK_OFF(DEVPCIBUS, apDevices[1]);
    220     GEN_CHECK_OFF(DEVPCIBUS, pDevInsR3);
    221     GEN_CHECK_OFF(DEVPCIBUS, pPciHlpR3);
    222220    GEN_CHECK_OFF(DEVPCIBUS, papBridgesR3);
    223     GEN_CHECK_OFF(DEVPCIBUS, pDevInsR0);
    224     GEN_CHECK_OFF(DEVPCIBUS, pPciHlpR0);
    225     GEN_CHECK_OFF(DEVPCIBUS, pDevInsRC);
    226     GEN_CHECK_OFF(DEVPCIBUS, pPciHlpRC);
    227221    GEN_CHECK_OFF(DEVPCIBUS, PciDev);
    228222    GEN_CHECK_SIZE(PIIX3ISABRIDGE);
    229223    GEN_CHECK_SIZE(DEVPCIROOT);
    230224    GEN_CHECK_OFF(DEVPCIROOT, PciBus);
    231     GEN_CHECK_OFF(DEVPCIROOT, pDevInsR3);
    232     GEN_CHECK_OFF(DEVPCIROOT, pDevInsR0);
    233     GEN_CHECK_OFF(DEVPCIROOT, pDevInsRC);
    234225    GEN_CHECK_OFF(DEVPCIROOT, fUseIoApic);
    235226    GEN_CHECK_OFF(DEVPCIROOT, u64PciConfigMMioAddress);

  • trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

    r80942 r80943  
    283283    LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
    284284             pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
    285     PGVM         pGVM    = pDevIns->Internal.s.pGVM;
    286     size_t const idxBus  = pPciDev->Int.s.idxPdmBus;
    287     AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses));
    288     PPDMPCIBUS   pPciBus = &pGVM->pdm.s.aPciBuses[idxBus];
     285    PGVM         pGVM      = pDevIns->Internal.s.pGVM;
     286    size_t const idxBus    = pPciDev->Int.s.idxPdmBus;
     287    AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
     288    PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
    289289
    290290    pdmLock(pGVM);
     291
    291292    uint32_t uTagSrc;
    292293    if (iLevel & PDM_IRQ_LEVEL_HIGH)
    … …  
    301302        uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
    302303
    303     if (    pPciBus
    304         &&  pPciBus->pDevInsR0)
    305     {
    306         pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
     304    if (pPciBusR0->pDevInsR0)
     305    {
     306        pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
    307307
    308308        pdmUnlock(pGVM);
    … …  
    793793    LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
    794794    return hTraceBuf;
     795}
     796
     797
     798/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
     799static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
     800{
     801    PDMDEV_ASSERT_DEVINS(pDevIns);
     802    LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
     803             pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
     804             pPciBusReg->u32EndVersion, ppPciHlp));
     805    PGVM pGVM = pDevIns->Internal.s.pGVM;
     806
     807    /*
     808     * Validate input.
     809     */
     810    AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
     811    AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
     812                          ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
     813    AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
     814    AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
     815                          ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
     816
     817    AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
     818
     819    VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
     820    VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
     821
     822    /* Check the shared bus data (registered earlier from ring-3): */
     823    uint32_t iBus = pPciBusReg->iBus;
     824    ASMCompilerBarrier();
     825    AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
     826    PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
     827    AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
     828    AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
     829                          ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
     830
     831    /* Check that the bus isn't already registered in ring-0: */
     832    AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
     833    PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
     834    AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
     835                          ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
     836                          VERR_ALREADY_EXISTS);
     837
     838    /*
     839     * Do the registering.
     840     */
     841    pPciBusR0->iBus        = iBus;
     842    pPciBusR0->uPadding0   = 0xbeefbeef;
     843    pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
     844    pPciBusR0->pDevInsR0   = pDevIns;
     845
     846    *ppPciHlp = &g_pdmR0PciHlp;
     847
     848    LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
     849    return VINF_SUCCESS;
    795850}
    796851
    … …  
    853908    pdmR0DevHlp_CritSectGetRecursion,
    854909    pdmR0DevHlp_DBGFTraceBuf,
     910    pdmR0DevHlp_PCIBusSetUpContext,
    855911    NULL /*pfnReserved1*/,
    856912    NULL /*pfnReserved2*/,

  • trunk/src/VBox/VMM/VMMR3/PDM.cpp

    r80531 r80943  
    542542
    543543    /*
    544      * The register PCI Buses.
    545      */
    546     for (unsigned i = 0; i < RT_ELEMENTS(pVM->pdm.s.aPciBuses); i++)
    547     {
    548         if (pVM->pdm.s.aPciBuses[i].pDevInsRC)
    549         {
    550             pVM->pdm.s.aPciBuses[i].pDevInsRC   += offDelta;
    551             pVM->pdm.s.aPciBuses[i].pfnSetIrqRC += offDelta;
    552         }
    553     }
    554 
    555     /*
    556544     * Devices & Drivers.
    557545     */

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r80722 r80943  
    18451845         */
    18461846        pdmLock(pVM);
    1847         rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
     1847        rc = pBus->pfnRegister(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
    18481848        pdmUnlock(pVM);
    18491849        if (RT_SUCCESS(rc))
    … …  
    19191919    pdmLock(pVM);
    19201920    int rc;
    1921     if (pBus->pfnRegisterMsiR3)
    1922         rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
     1921    if (pBus->pfnRegisterMsi)
     1922        rc = pBus->pfnRegisterMsi(pBus->pDevInsR3, pPciDev, pMsiReg);
    19231923    else
    19241924        rc = VERR_NOT_IMPLEMENTED;
    … …  
    20242024
    20252025    pdmLock(pVM);
    2026     int rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
     2026    int rc = pBus->pfnIORegionRegister(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
    20272027    pdmUnlock(pVM);
    20282028
    … …  
    20322032
    20332033
    2034 /** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
    2035 static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    2036                                                             PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
     2034/** @interface_method_impl{PDMDEVHLPR3,pfnPCIInterceptConfigAccesses} */
     2035static DECLCALLBACK(int) pdmR3DevHlp_PCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     2036                                                                PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
    20372037{
    20382038    PDMDEV_ASSERT_DEVINS(pDevIns);
    … …  
    20412041    if (!pPciDev) /* NULL is an alias for the default PCI device. */
    20422042        pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
    2043     AssertReturnVoid(pPciDev);
    2044     LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
    2045              pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
    2046 
    2047     /*
    2048      * Validate input and resolve defaults.
     2043    AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2044    LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: pPciDev=%p pfnRead=%p pfnWrite=%p\n",
     2045             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, pfnWrite));
     2046
     2047    /*
     2048     * Validate input.
    20492049     */
    20502050    AssertPtr(pfnRead);
    20512051    AssertPtr(pfnWrite);
    2052     AssertPtrNull(ppfnReadOld);
    2053     AssertPtrNull(ppfnWriteOld);
    2054     AssertPtrNull(pPciDev);
     2052    AssertPtr(pPciDev);
    20552053
    20562054    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
    2057     AssertReleaseReturnVoid(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
     2055    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
    20582056    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
    20592057    AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
    … …  
    20632061     */
    20642062    pdmLock(pVM);
    2065     pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
     2063    pBus->pfnInterceptConfigAccesses(pBus->pDevInsR3, pPciDev, pfnRead, pfnWrite);
    20662064    pdmUnlock(pVM);
    20672065
    2068     LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
     2066    LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: returns VINF_SUCCESS\n",
     2067             pDevIns->pReg->szName, pDevIns->iInstance));
     2068    return VINF_SUCCESS;
     2069}
     2070
     2071
     2072/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigWrite} */
     2073static DECLCALLBACK(VBOXSTRICTRC)
     2074pdmR3DevHlp_PCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value)
     2075{
     2076    PDMDEV_ASSERT_DEVINS(pDevIns);
     2077    PVM pVM = pDevIns->Internal.s.pVMR3;
     2078    AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2079    LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d u32Value=%#x\n",
     2080             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, u32Value));
     2081
     2082    /*
     2083     * Resolve the bus.
     2084     */
     2085    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
     2086    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
     2087    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
     2088
     2089    /*
     2090     * Do the job.
     2091     */
     2092    VBOXSTRICTRC rcStrict = pBus->pfnConfigWrite(pBus->pDevInsR3, pPciDev, uAddress, cb, u32Value);
     2093
     2094    LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: returns %Rrc\n",
     2095             pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
     2096    return rcStrict;
     2097}
     2098
     2099
     2100/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigRead} */
     2101static DECLCALLBACK(VBOXSTRICTRC)
     2102pdmR3DevHlp_PCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
     2103{
     2104    PDMDEV_ASSERT_DEVINS(pDevIns);
     2105    PVM pVM = pDevIns->Internal.s.pVMR3;
     2106    AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2107    LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d pu32Value=%p:{%#x}\n",
     2108             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, pu32Value, *pu32Value));
     2109
     2110    /*
     2111     * Resolve the bus.
     2112     */
     2113    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
     2114    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
     2115    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
     2116
     2117    /*
     2118     * Do the job.
     2119     */
     2120    VBOXSTRICTRC rcStrict = pBus->pfnConfigRead(pBus->pDevInsR3, pPciDev, uAddress, cb, pu32Value);
     2121
     2122    LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: returns %Rrc (*pu32Value=%#x)\n",
     2123             pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict), pu32Value, *pu32Value));
     2124    return rcStrict;
    20692125}
    20702126
    … …  
    31323188
    31333189/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
    3134 static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg,
    3135                                                     PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus)
     3190static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
     3191                                                    PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
    31363192{
    31373193    PDMDEV_ASSERT_DEVINS(pDevIns);
    … …  
    31393195    VM_ASSERT_EMT(pVM);
    31403196    LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
    3141              ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
     3197             ".pfnInterceptConfigAccesses=%p, pfnConfigRead=%p, pfnConfigWrite=%p, .pfnSetIrqR3=%p, .u32EndVersion=%#x} ppPciHlpR3=%p piBus=%p\n",
    31423198             pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
    3143              pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
    3144              pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3, piBus));
    3145 
    3146     /*
    3147      * Validate the structure.
    3148      */
    3149     if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
    3150     {
    3151         AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
    3152         LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3153         return VERR_INVALID_PARAMETER;
    3154     }
    3155     if (    !pPciBusReg->pfnRegisterR3
    3156         ||  !pPciBusReg->pfnIORegionRegisterR3
    3157         ||  !pPciBusReg->pfnSetIrqR3)
    3158     {
    3159         Assert(pPciBusReg->pfnRegisterR3);
    3160         Assert(pPciBusReg->pfnIORegionRegisterR3);
    3161         Assert(pPciBusReg->pfnSetIrqR3);
    3162         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3163         return VERR_INVALID_PARAMETER;
    3164     }
    3165     if (    pPciBusReg->pszSetIrqRC
    3166         &&  !VALID_PTR(pPciBusReg->pszSetIrqRC))
    3167     {
    3168         Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
    3169         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3170         return VERR_INVALID_PARAMETER;
    3171     }
    3172     if (    pPciBusReg->pszSetIrqR0
    3173         &&  !VALID_PTR(pPciBusReg->pszSetIrqR0))
    3174     {
    3175         Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
    3176         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3177         return VERR_INVALID_PARAMETER;
    3178     }
    3179     if (!ppPciHlpR3)
    3180     {
    3181         Assert(ppPciHlpR3);
    3182         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3183         return VERR_INVALID_PARAMETER;
    3184     }
    3185     AssertLogRelMsgReturn(RT_VALID_PTR(piBus) || !piBus,
    3186                           ("caller='%s'/%d: piBus=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, piBus),
    3187                           VERR_INVALID_POINTER);
     3199             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnInterceptConfigAccesses, pPciBusReg->pfnConfigRead,
     3200             pPciBusReg->pfnConfigWrite, pPciBusReg->pfnSetIrqR3, pPciBusReg->u32EndVersion, ppPciHlp, piBus));
     3201
     3202    /*
     3203     * Validate the structure and output parameters.
     3204     */
     3205    AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGR3_VERSION,
     3206                          ("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
     3207                          VERR_INVALID_PARAMETER);
     3208    AssertPtrReturn(pPciBusReg->pfnRegisterR3, VERR_INVALID_PARAMETER);
     3209    AssertPtrNullReturn(pPciBusReg->pfnRegisterMsiR3, VERR_INVALID_POINTER);
     3210    AssertPtrReturn(pPciBusReg->pfnIORegionRegisterR3, VERR_INVALID_POINTER);
     3211    AssertPtrReturn(pPciBusReg->pfnInterceptConfigAccesses, VERR_INVALID_POINTER);
     3212    AssertPtrReturn(pPciBusReg->pfnConfigWrite, VERR_INVALID_POINTER);
     3213    AssertPtrReturn(pPciBusReg->pfnConfigRead, VERR_INVALID_POINTER);
     3214    AssertPtrReturn(pPciBusReg->pfnSetIrqR3, VERR_INVALID_POINTER);
     3215    AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGR3_VERSION,
     3216                          ("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
     3217                          VERR_INVALID_PARAMETER);
     3218    AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
     3219    AssertPtrNullReturn(piBus, VERR_INVALID_POINTER);
     3220    VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
    31883221
    31893222    /*
    … …  
    31943227        if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
    31953228            break;
    3196     if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
    3197     {
    3198         AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
    3199         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3200         return VERR_INVALID_PARAMETER;
    3201     }
     3229    AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
     3230                          ("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)),
     3231                          VERR_OUT_OF_RESOURCES);
    32023232    PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
    32033233
    32043234    /*
    3205      * Resolve and init the RC bits.
    3206      */
    3207     if (pPciBusReg->pszSetIrqRC)
    3208     {
    3209         int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
    3210         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->pszRCMod, pPciBusReg->pszSetIrqRC, rc));
    3211         if (RT_FAILURE(rc))
    3212         {
    3213             LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3214             return rc;
    3215         }
    3216         pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3217     }
    3218     else
    3219     {
    3220         pPciBus->pfnSetIrqRC  = 0;
    3221         pPciBus->pDevInsRC    = 0;
    3222     }
    3223 
    3224     /*
    3225      * Resolve and init the R0 bits.
    3226      */
    3227     if (pPciBusReg->pszSetIrqR0)
    3228     {
    3229         int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
    3230         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->pszR0Mod, pPciBusReg->pszSetIrqR0, rc));
    3231         if (RT_FAILURE(rc))
    3232         {
    3233             LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3234             return rc;
    3235         }
    3236         pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3237     }
    3238     else
    3239     {
    3240         pPciBus->pfnSetIrqR0 = 0;
    3241         pPciBus->pDevInsR0   = 0;
    3242     }
    3243 
    3244     /*
    32453235     * Init the R3 bits.
    32463236     */
    3247     pPciBus->iBus                    = iBus;
    3248     pPciBus->pDevInsR3               = pDevIns;
    3249     pPciBus->pfnRegisterR3           = pPciBusReg->pfnRegisterR3;
    3250     pPciBus->pfnRegisterMsiR3        = pPciBusReg->pfnRegisterMsiR3;
    3251     pPciBus->pfnIORegionRegisterR3   = pPciBusReg->pfnIORegionRegisterR3;
    3252     pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
    3253     pPciBus->pfnSetIrqR3             = pPciBusReg->pfnSetIrqR3;
     3237    pPciBus->iBus                       = iBus;
     3238    pPciBus->pDevInsR3                  = pDevIns;
     3239    pPciBus->pfnRegister                = pPciBusReg->pfnRegisterR3;
     3240    pPciBus->pfnRegisterMsi             = pPciBusReg->pfnRegisterMsiR3;
     3241    pPciBus->pfnIORegionRegister        = pPciBusReg->pfnIORegionRegisterR3;
     3242    pPciBus->pfnInterceptConfigAccesses = pPciBusReg->pfnInterceptConfigAccesses;
     3243    pPciBus->pfnConfigRead              = pPciBusReg->pfnConfigRead;
     3244    pPciBus->pfnConfigWrite             = pPciBusReg->pfnConfigWrite;
     3245    pPciBus->pfnSetIrqR3                = pPciBusReg->pfnSetIrqR3;
    32543246
    32553247    Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
    32563248
    32573249    /* set the helper pointer and return. */
    3258     *ppPciHlpR3 = &g_pdmR3DevPciHlp;
     3250    *ppPciHlp = &g_pdmR3DevPciHlp;
    32593251    if (piBus)
    32603252        *piBus = iBus;
    … …  
    43174309    pdmR3DevHlp_PCIRegisterMsi,
    43184310    pdmR3DevHlp_PCIIORegionRegister,
    4319     pdmR3DevHlp_PCISetConfigCallbacks,
     4311    pdmR3DevHlp_PCIInterceptConfigAccesses,
     4312    pdmR3DevHlp_PCIConfigWrite,
     4313    pdmR3DevHlp_PCIConfigRead,
    43204314    pdmR3DevHlp_PCIPhysRead,
    43214315    pdmR3DevHlp_PCIPhysWrite,
    … …  
    47564750    pdmR3DevHlp_PCIRegisterMsi,
    47574751    pdmR3DevHlp_PCIIORegionRegister,
    4758     pdmR3DevHlp_PCISetConfigCallbacks,
     4752    pdmR3DevHlp_PCIInterceptConfigAccesses,
     4753    pdmR3DevHlp_PCIConfigWrite,
     4754    pdmR3DevHlp_PCIConfigRead,
    47594755    pdmR3DevHlp_PCIPhysRead,
    47604756    pdmR3DevHlp_PCIPhysWrite,

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r80531 r80943  
    718718
    719719/**
    720  * PDM PCI Bus instance.
     720 * PDM PCI bus instance.
    721721 */
    722722typedef struct PDMPCIBUS
    723723{
    724724    /** PCI bus number. */
    725     RTUINT          iBus;
    726     RTUINT          uPadding0; /**< Alignment padding.*/
    727 
    728     /** Pointer to PCI Bus device instance. */
    729     PPDMDEVINSR3                    pDevInsR3;
    730     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    731     DECLR3CALLBACKMEMBER(void,      pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
    732     /** @copydoc PDMPCIBUSREG::pfnRegisterR3 */
    733     DECLR3CALLBACKMEMBER(int,       pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
    734                                                    uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
    735     /** @copydoc PDMPCIBUSREG::pfnRegisterMsiR3 */
    736     DECLR3CALLBACKMEMBER(int,       pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
    737     /** @copydoc PDMPCIBUSREG::pfnIORegionRegisterR3 */
    738     DECLR3CALLBACKMEMBER(int,       pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
    739                                                            PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback));
    740     /** @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3 */
    741     DECLR3CALLBACKMEMBER(void,      pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead,
    742                                                              PPFNPCICONFIGREAD ppfnReadOld, PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
    743 
    744     /** Pointer to the PIC device instance - R0. */
    745     R0PTRTYPE(PPDMDEVINS)           pDevInsR0;
    746     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    747     DECLR0CALLBACKMEMBER(void,      pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
    748 
    749     /** Pointer to PCI Bus device instance. */
    750     PPDMDEVINSRC                    pDevInsRC;
    751     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    752     DECLRCCALLBACKMEMBER(void,      pfnSetIrqRC,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     725    uint32_t                   iBus;
     726    uint32_t                   uPadding0; /**< Alignment padding.*/
     727
     728    /** Pointer to PCI bus device instance. */
     729    PPDMDEVINSR3               pDevInsR3;
     730    /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
     731    DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     732
     733    /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
     734    DECLR3CALLBACKMEMBER(int,  pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
     735                                            uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
     736    /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
     737    DECLR3CALLBACKMEMBER(int,  pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
     738    /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
     739    DECLR3CALLBACKMEMBER(int,  pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
     740                                                    PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback));
     741    /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
     742    DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     743                                                           PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
     744    /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
     745    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     746                                                       uint32_t uAddress, unsigned cb, uint32_t u32Value));
     747    /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
     748    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     749                                                      uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
    753750} PDMPCIBUS;
    754751
     752
     753/**
     754 * Ring-0 PDM PCI bus instance data.
     755 */
     756typedef struct PDMPCIBUSR0
     757{
     758    /** PCI bus number. */
     759    uint32_t                   iBus;
     760    uint32_t                   uPadding0; /**< Alignment padding.*/
     761    /** Pointer to PCI bus device instance. */
     762    PPDMDEVINSR0               pDevInsR0;
     763    /** @copydoc PDMPCIBUSREGR0::pfnSetIrqR0 */
     764    DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     765} PDMPCIBUSR0;
     766/** Pointer to the ring-0 PCI bus data. */
     767typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
    755768
    756769#ifdef IN_RING3
    … …  
    12241237typedef struct PDMR0PERVM
    12251238{
     1239    /** PCI Buses, ring-0 data. */
     1240    PDMPCIBUSR0                     aPciBuses[PDM_PCI_BUSSES_MAX];
    12261241    /** Number of valid ring-0 device instances (apDevInstances). */
    12271242    uint32_t                        cDevInstances;
     1243    uint32_t                        u32Padding;
    12281244    /** Pointer to ring-0 device instances. */
    12291245    R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
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