VirtualBox

Changeset 80943 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Sep 23, 2019 9:36:14 AM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
133523
Message:

Devices/PCI: Device model refactoring, part I. bugref:9218

Location:
trunk/src/VBox/VMM
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

    r80942 r80943  
    283283    LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
    284284             pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
    285     PGVM         pGVM    = pDevIns->Internal.s.pGVM;
    286     size_t const idxBus  = pPciDev->Int.s.idxPdmBus;
    287     AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses));
    288     PPDMPCIBUS   pPciBus = &pGVM->pdm.s.aPciBuses[idxBus];
     285    PGVM         pGVM      = pDevIns->Internal.s.pGVM;
     286    size_t const idxBus    = pPciDev->Int.s.idxPdmBus;
     287    AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
     288    PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
    289289
    290290    pdmLock(pGVM);
     291
    291292    uint32_t uTagSrc;
    292293    if (iLevel & PDM_IRQ_LEVEL_HIGH)
    … …  
    301302        uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
    302303
    303     if (    pPciBus
    304         &&  pPciBus->pDevInsR0)
    305     {
    306         pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
     304    if (pPciBusR0->pDevInsR0)
     305    {
     306        pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
    307307
    308308        pdmUnlock(pGVM);
    … …  
    793793    LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
    794794    return hTraceBuf;
     795}
     796
     797
     798/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
     799static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
     800{
     801    PDMDEV_ASSERT_DEVINS(pDevIns);
     802    LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
     803             pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
     804             pPciBusReg->u32EndVersion, ppPciHlp));
     805    PGVM pGVM = pDevIns->Internal.s.pGVM;
     806
     807    /*
     808     * Validate input.
     809     */
     810    AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
     811    AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
     812                          ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
     813    AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
     814    AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
     815                          ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
     816
     817    AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
     818
     819    VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
     820    VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
     821
     822    /* Check the shared bus data (registered earlier from ring-3): */
     823    uint32_t iBus = pPciBusReg->iBus;
     824    ASMCompilerBarrier();
     825    AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
     826    PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
     827    AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
     828    AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
     829                          ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
     830
     831    /* Check that the bus isn't already registered in ring-0: */
     832    AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
     833    PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
     834    AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
     835                          ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
     836                          VERR_ALREADY_EXISTS);
     837
     838    /*
     839     * Do the registering.
     840     */
     841    pPciBusR0->iBus        = iBus;
     842    pPciBusR0->uPadding0   = 0xbeefbeef;
     843    pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
     844    pPciBusR0->pDevInsR0   = pDevIns;
     845
     846    *ppPciHlp = &g_pdmR0PciHlp;
     847
     848    LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
     849    return VINF_SUCCESS;
    795850}
    796851
    … …  
    853908    pdmR0DevHlp_CritSectGetRecursion,
    854909    pdmR0DevHlp_DBGFTraceBuf,
     910    pdmR0DevHlp_PCIBusSetUpContext,
    855911    NULL /*pfnReserved1*/,
    856912    NULL /*pfnReserved2*/,

  • trunk/src/VBox/VMM/VMMR3/PDM.cpp

    r80531 r80943  
    542542
    543543    /*
    544      * The register PCI Buses.
    545      */
    546     for (unsigned i = 0; i < RT_ELEMENTS(pVM->pdm.s.aPciBuses); i++)
    547     {
    548         if (pVM->pdm.s.aPciBuses[i].pDevInsRC)
    549         {
    550             pVM->pdm.s.aPciBuses[i].pDevInsRC   += offDelta;
    551             pVM->pdm.s.aPciBuses[i].pfnSetIrqRC += offDelta;
    552         }
    553     }
    554 
    555     /*
    556544     * Devices & Drivers.
    557545     */

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r80722 r80943  
    18451845         */
    18461846        pdmLock(pVM);
    1847         rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
     1847        rc = pBus->pfnRegister(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
    18481848        pdmUnlock(pVM);
    18491849        if (RT_SUCCESS(rc))
    … …  
    19191919    pdmLock(pVM);
    19201920    int rc;
    1921     if (pBus->pfnRegisterMsiR3)
    1922         rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
     1921    if (pBus->pfnRegisterMsi)
     1922        rc = pBus->pfnRegisterMsi(pBus->pDevInsR3, pPciDev, pMsiReg);
    19231923    else
    19241924        rc = VERR_NOT_IMPLEMENTED;
    … …  
    20242024
    20252025    pdmLock(pVM);
    2026     int rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
     2026    int rc = pBus->pfnIORegionRegister(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
    20272027    pdmUnlock(pVM);
    20282028
    … …  
    20322032
    20332033
    2034 /** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
    2035 static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
    2036                                                             PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
     2034/** @interface_method_impl{PDMDEVHLPR3,pfnPCIInterceptConfigAccesses} */
     2035static DECLCALLBACK(int) pdmR3DevHlp_PCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     2036                                                                PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
    20372037{
    20382038    PDMDEV_ASSERT_DEVINS(pDevIns);
    … …  
    20412041    if (!pPciDev) /* NULL is an alias for the default PCI device. */
    20422042        pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
    2043     AssertReturnVoid(pPciDev);
    2044     LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
    2045              pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
    2046 
    2047     /*
    2048      * Validate input and resolve defaults.
     2043    AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2044    LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: pPciDev=%p pfnRead=%p pfnWrite=%p\n",
     2045             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, pfnWrite));
     2046
     2047    /*
     2048     * Validate input.
    20492049     */
    20502050    AssertPtr(pfnRead);
    20512051    AssertPtr(pfnWrite);
    2052     AssertPtrNull(ppfnReadOld);
    2053     AssertPtrNull(ppfnWriteOld);
    2054     AssertPtrNull(pPciDev);
     2052    AssertPtr(pPciDev);
    20552053
    20562054    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
    2057     AssertReleaseReturnVoid(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
     2055    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
    20582056    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
    20592057    AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
    … …  
    20632061     */
    20642062    pdmLock(pVM);
    2065     pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
     2063    pBus->pfnInterceptConfigAccesses(pBus->pDevInsR3, pPciDev, pfnRead, pfnWrite);
    20662064    pdmUnlock(pVM);
    20672065
    2068     LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
     2066    LogFlow(("pdmR3DevHlp_PCIInterceptConfigAccesses: caller='%s'/%d: returns VINF_SUCCESS\n",
     2067             pDevIns->pReg->szName, pDevIns->iInstance));
     2068    return VINF_SUCCESS;
     2069}
     2070
     2071
     2072/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigWrite} */
     2073static DECLCALLBACK(VBOXSTRICTRC)
     2074pdmR3DevHlp_PCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t u32Value)
     2075{
     2076    PDMDEV_ASSERT_DEVINS(pDevIns);
     2077    PVM pVM = pDevIns->Internal.s.pVMR3;
     2078    AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2079    LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d u32Value=%#x\n",
     2080             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, u32Value));
     2081
     2082    /*
     2083     * Resolve the bus.
     2084     */
     2085    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
     2086    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
     2087    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
     2088
     2089    /*
     2090     * Do the job.
     2091     */
     2092    VBOXSTRICTRC rcStrict = pBus->pfnConfigWrite(pBus->pDevInsR3, pPciDev, uAddress, cb, u32Value);
     2093
     2094    LogFlow(("pdmR3DevHlp_PCIConfigWrite: caller='%s'/%d: returns %Rrc\n",
     2095             pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict)));
     2096    return rcStrict;
     2097}
     2098
     2099
     2100/** @interface_method_impl{PDMDEVHLPR3,pfnPCIConfigRead} */
     2101static DECLCALLBACK(VBOXSTRICTRC)
     2102pdmR3DevHlp_PCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
     2103{
     2104    PDMDEV_ASSERT_DEVINS(pDevIns);
     2105    PVM pVM = pDevIns->Internal.s.pVMR3;
     2106    AssertPtrReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
     2107    LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: pPciDev=%p uAddress=%#x cd=%d pu32Value=%p:{%#x}\n",
     2108             pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, uAddress, cb, pu32Value, *pu32Value));
     2109
     2110    /*
     2111     * Resolve the bus.
     2112     */
     2113    size_t const    idxBus = pPciDev->Int.s.idxPdmBus;
     2114    AssertReturn(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), VERR_INTERNAL_ERROR_2);
     2115    PPDMPCIBUS      pBus   = &pVM->pdm.s.aPciBuses[idxBus];
     2116
     2117    /*
     2118     * Do the job.
     2119     */
     2120    VBOXSTRICTRC rcStrict = pBus->pfnConfigRead(pBus->pDevInsR3, pPciDev, uAddress, cb, pu32Value);
     2121
     2122    LogFlow(("pdmR3DevHlp_PCIConfigRead: caller='%s'/%d: returns %Rrc (*pu32Value=%#x)\n",
     2123             pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict), pu32Value, *pu32Value));
     2124    return rcStrict;
    20692125}
    20702126
    … …  
    31323188
    31333189/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
    3134 static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg,
    3135                                                     PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus)
     3190static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
     3191                                                    PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
    31363192{
    31373193    PDMDEV_ASSERT_DEVINS(pDevIns);
    … …  
    31393195    VM_ASSERT_EMT(pVM);
    31403196    LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
    3141              ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
     3197             ".pfnInterceptConfigAccesses=%p, pfnConfigRead=%p, pfnConfigWrite=%p, .pfnSetIrqR3=%p, .u32EndVersion=%#x} ppPciHlpR3=%p piBus=%p\n",
    31423198             pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
    3143              pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
    3144              pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3, piBus));
    3145 
    3146     /*
    3147      * Validate the structure.
    3148      */
    3149     if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
    3150     {
    3151         AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
    3152         LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3153         return VERR_INVALID_PARAMETER;
    3154     }
    3155     if (    !pPciBusReg->pfnRegisterR3
    3156         ||  !pPciBusReg->pfnIORegionRegisterR3
    3157         ||  !pPciBusReg->pfnSetIrqR3)
    3158     {
    3159         Assert(pPciBusReg->pfnRegisterR3);
    3160         Assert(pPciBusReg->pfnIORegionRegisterR3);
    3161         Assert(pPciBusReg->pfnSetIrqR3);
    3162         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3163         return VERR_INVALID_PARAMETER;
    3164     }
    3165     if (    pPciBusReg->pszSetIrqRC
    3166         &&  !VALID_PTR(pPciBusReg->pszSetIrqRC))
    3167     {
    3168         Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
    3169         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3170         return VERR_INVALID_PARAMETER;
    3171     }
    3172     if (    pPciBusReg->pszSetIrqR0
    3173         &&  !VALID_PTR(pPciBusReg->pszSetIrqR0))
    3174     {
    3175         Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
    3176         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3177         return VERR_INVALID_PARAMETER;
    3178     }
    3179     if (!ppPciHlpR3)
    3180     {
    3181         Assert(ppPciHlpR3);
    3182         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3183         return VERR_INVALID_PARAMETER;
    3184     }
    3185     AssertLogRelMsgReturn(RT_VALID_PTR(piBus) || !piBus,
    3186                           ("caller='%s'/%d: piBus=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, piBus),
    3187                           VERR_INVALID_POINTER);
     3199             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnInterceptConfigAccesses, pPciBusReg->pfnConfigRead,
     3200             pPciBusReg->pfnConfigWrite, pPciBusReg->pfnSetIrqR3, pPciBusReg->u32EndVersion, ppPciHlp, piBus));
     3201
     3202    /*
     3203     * Validate the structure and output parameters.
     3204     */
     3205    AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGR3_VERSION,
     3206                          ("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
     3207                          VERR_INVALID_PARAMETER);
     3208    AssertPtrReturn(pPciBusReg->pfnRegisterR3, VERR_INVALID_PARAMETER);
     3209    AssertPtrNullReturn(pPciBusReg->pfnRegisterMsiR3, VERR_INVALID_POINTER);
     3210    AssertPtrReturn(pPciBusReg->pfnIORegionRegisterR3, VERR_INVALID_POINTER);
     3211    AssertPtrReturn(pPciBusReg->pfnInterceptConfigAccesses, VERR_INVALID_POINTER);
     3212    AssertPtrReturn(pPciBusReg->pfnConfigWrite, VERR_INVALID_POINTER);
     3213    AssertPtrReturn(pPciBusReg->pfnConfigRead, VERR_INVALID_POINTER);
     3214    AssertPtrReturn(pPciBusReg->pfnSetIrqR3, VERR_INVALID_POINTER);
     3215    AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGR3_VERSION,
     3216                          ("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGR3_VERSION),
     3217                          VERR_INVALID_PARAMETER);
     3218    AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
     3219    AssertPtrNullReturn(piBus, VERR_INVALID_POINTER);
     3220    VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
    31883221
    31893222    /*
    … …  
    31943227        if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
    31953228            break;
    3196     if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
    3197     {
    3198         AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
    3199         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    3200         return VERR_INVALID_PARAMETER;
    3201     }
     3229    AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
     3230                          ("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)),
     3231                          VERR_OUT_OF_RESOURCES);
    32023232    PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
    32033233
    32043234    /*
    3205      * Resolve and init the RC bits.
    3206      */
    3207     if (pPciBusReg->pszSetIrqRC)
    3208     {
    3209         int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
    3210         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->pszRCMod, pPciBusReg->pszSetIrqRC, rc));
    3211         if (RT_FAILURE(rc))
    3212         {
    3213             LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3214             return rc;
    3215         }
    3216         pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3217     }
    3218     else
    3219     {
    3220         pPciBus->pfnSetIrqRC  = 0;
    3221         pPciBus->pDevInsRC    = 0;
    3222     }
    3223 
    3224     /*
    3225      * Resolve and init the R0 bits.
    3226      */
    3227     if (pPciBusReg->pszSetIrqR0)
    3228     {
    3229         int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
    3230         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->pszR0Mod, pPciBusReg->pszSetIrqR0, rc));
    3231         if (RT_FAILURE(rc))
    3232         {
    3233             LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3234             return rc;
    3235         }
    3236         pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3237     }
    3238     else
    3239     {
    3240         pPciBus->pfnSetIrqR0 = 0;
    3241         pPciBus->pDevInsR0   = 0;
    3242     }
    3243 
    3244     /*
    32453235     * Init the R3 bits.
    32463236     */
    3247     pPciBus->iBus                    = iBus;
    3248     pPciBus->pDevInsR3               = pDevIns;
    3249     pPciBus->pfnRegisterR3           = pPciBusReg->pfnRegisterR3;
    3250     pPciBus->pfnRegisterMsiR3        = pPciBusReg->pfnRegisterMsiR3;
    3251     pPciBus->pfnIORegionRegisterR3   = pPciBusReg->pfnIORegionRegisterR3;
    3252     pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
    3253     pPciBus->pfnSetIrqR3             = pPciBusReg->pfnSetIrqR3;
     3237    pPciBus->iBus                       = iBus;
     3238    pPciBus->pDevInsR3                  = pDevIns;
     3239    pPciBus->pfnRegister                = pPciBusReg->pfnRegisterR3;
     3240    pPciBus->pfnRegisterMsi             = pPciBusReg->pfnRegisterMsiR3;
     3241    pPciBus->pfnIORegionRegister        = pPciBusReg->pfnIORegionRegisterR3;
     3242    pPciBus->pfnInterceptConfigAccesses = pPciBusReg->pfnInterceptConfigAccesses;
     3243    pPciBus->pfnConfigRead              = pPciBusReg->pfnConfigRead;
     3244    pPciBus->pfnConfigWrite             = pPciBusReg->pfnConfigWrite;
     3245    pPciBus->pfnSetIrqR3                = pPciBusReg->pfnSetIrqR3;
    32543246
    32553247    Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
    32563248
    32573249    /* set the helper pointer and return. */
    3258     *ppPciHlpR3 = &g_pdmR3DevPciHlp;
     3250    *ppPciHlp = &g_pdmR3DevPciHlp;
    32593251    if (piBus)
    32603252        *piBus = iBus;
    … …  
    43174309    pdmR3DevHlp_PCIRegisterMsi,
    43184310    pdmR3DevHlp_PCIIORegionRegister,
    4319     pdmR3DevHlp_PCISetConfigCallbacks,
     4311    pdmR3DevHlp_PCIInterceptConfigAccesses,
     4312    pdmR3DevHlp_PCIConfigWrite,
     4313    pdmR3DevHlp_PCIConfigRead,
    43204314    pdmR3DevHlp_PCIPhysRead,
    43214315    pdmR3DevHlp_PCIPhysWrite,
    … …  
    47564750    pdmR3DevHlp_PCIRegisterMsi,
    47574751    pdmR3DevHlp_PCIIORegionRegister,
    4758     pdmR3DevHlp_PCISetConfigCallbacks,
     4752    pdmR3DevHlp_PCIInterceptConfigAccesses,
     4753    pdmR3DevHlp_PCIConfigWrite,
     4754    pdmR3DevHlp_PCIConfigRead,
    47594755    pdmR3DevHlp_PCIPhysRead,
    47604756    pdmR3DevHlp_PCIPhysWrite,

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r80531 r80943  
    718718
    719719/**
    720  * PDM PCI Bus instance.
     720 * PDM PCI bus instance.
    721721 */
    722722typedef struct PDMPCIBUS
    723723{
    724724    /** PCI bus number. */
    725     RTUINT          iBus;
    726     RTUINT          uPadding0; /**< Alignment padding.*/
    727 
    728     /** Pointer to PCI Bus device instance. */
    729     PPDMDEVINSR3                    pDevInsR3;
    730     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    731     DECLR3CALLBACKMEMBER(void,      pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
    732     /** @copydoc PDMPCIBUSREG::pfnRegisterR3 */
    733     DECLR3CALLBACKMEMBER(int,       pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
    734                                                    uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
    735     /** @copydoc PDMPCIBUSREG::pfnRegisterMsiR3 */
    736     DECLR3CALLBACKMEMBER(int,       pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
    737     /** @copydoc PDMPCIBUSREG::pfnIORegionRegisterR3 */
    738     DECLR3CALLBACKMEMBER(int,       pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
    739                                                            PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback));
    740     /** @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3 */
    741     DECLR3CALLBACKMEMBER(void,      pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead,
    742                                                              PPFNPCICONFIGREAD ppfnReadOld, PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
    743 
    744     /** Pointer to the PIC device instance - R0. */
    745     R0PTRTYPE(PPDMDEVINS)           pDevInsR0;
    746     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    747     DECLR0CALLBACKMEMBER(void,      pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
    748 
    749     /** Pointer to PCI Bus device instance. */
    750     PPDMDEVINSRC                    pDevInsRC;
    751     /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
    752     DECLRCCALLBACKMEMBER(void,      pfnSetIrqRC,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     725    uint32_t                   iBus;
     726    uint32_t                   uPadding0; /**< Alignment padding.*/
     727
     728    /** Pointer to PCI bus device instance. */
     729    PPDMDEVINSR3               pDevInsR3;
     730    /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
     731    DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     732
     733    /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
     734    DECLR3CALLBACKMEMBER(int,  pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
     735                                            uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
     736    /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
     737    DECLR3CALLBACKMEMBER(int,  pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
     738    /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
     739    DECLR3CALLBACKMEMBER(int,  pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
     740                                                    PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback));
     741    /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
     742    DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     743                                                           PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
     744    /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
     745    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     746                                                       uint32_t uAddress, unsigned cb, uint32_t u32Value));
     747    /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
     748    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
     749                                                      uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
    753750} PDMPCIBUS;
    754751
     752
     753/**
     754 * Ring-0 PDM PCI bus instance data.
     755 */
     756typedef struct PDMPCIBUSR0
     757{
     758    /** PCI bus number. */
     759    uint32_t                   iBus;
     760    uint32_t                   uPadding0; /**< Alignment padding.*/
     761    /** Pointer to PCI bus device instance. */
     762    PPDMDEVINSR0               pDevInsR0;
     763    /** @copydoc PDMPCIBUSREGR0::pfnSetIrqR0 */
     764    DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
     765} PDMPCIBUSR0;
     766/** Pointer to the ring-0 PCI bus data. */
     767typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
    755768
    756769#ifdef IN_RING3
    … …  
    12241237typedef struct PDMR0PERVM
    12251238{
     1239    /** PCI Buses, ring-0 data. */
     1240    PDMPCIBUSR0                     aPciBuses[PDM_PCI_BUSSES_MAX];
    12261241    /** Number of valid ring-0 device instances (apDevInstances). */
    12271242    uint32_t                        cDevInstances;
     1243    uint32_t                        u32Padding;
    12281244    /** Pointer to ring-0 device instances. */
    12291245    R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
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