VirtualBox

Changeset 80960 in vbox


Ignore:
Timestamp:
Sep 23, 2019 8:54:03 PM (6 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
133547
Message:

IOM,PDM,DevPCI,DevPciIch9,RTC: Fixes to the I/O port lookup table insertion code. Converted (mostly) the two PCI buses to the new PDM device style. The ICH9 variant wasn't actually dropping the default critsect, it turned out. Changed the new I/O port callbacks to return VBOXSTRICTRC rather than plain int. bugref:9218

Location:
trunk
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/iom.h

    r80679 r80960  
    243243typedef FNIOMIOPORTOUTSTRING *PFNIOMIOPORTOUTSTRING;
    244244
     245
     246/**
     247 * Port I/O Handler for IN operations.
     248 *
     249 * @returns VINF_SUCCESS or VINF_EM_*.
     250 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
     251 *
     252 * @param   pDevIns     The device instance.
     253 * @param   pvUser      User argument.
     254 * @param   uPort       Port number used for the IN operation.
     255 * @param   pu32        Where to store the result.  This is always a 32-bit
     256 *                      variable regardless of what @a cb might say.
     257 * @param   cb          Number of bytes read.
     258 * @remarks Caller enters the device critical section.
     259 */
     260typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWIN(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb);
     261/** Pointer to a FNIOMIOPORTNEWIN(). */
     262typedef FNIOMIOPORTNEWIN *PFNIOMIOPORTNEWIN;
     263
     264/**
     265 * Port I/O Handler for string IN operations.
     266 *
     267 * @returns VINF_SUCCESS or VINF_EM_*.
     268 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
     269 *
     270 * @param   pDevIns     The device instance.
     271 * @param   pvUser      User argument.
     272 * @param   uPort       Port number used for the IN operation.
     273 * @param   pbDst       Pointer to the destination buffer.
     274 * @param   pcTransfers Pointer to the number of transfer units to read, on
     275 *                      return remaining transfer units.
     276 * @param   cb          Size of the transfer unit (1, 2 or 4 bytes).
     277 * @remarks Caller enters the device critical section.
     278 */
     279typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWINSTRING(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint8_t *pbDst,
     280                                                          uint32_t *pcTransfers, unsigned cb);
     281/** Pointer to a FNIOMIOPORTNEWINSTRING(). */
     282typedef FNIOMIOPORTNEWINSTRING *PFNIOMIOPORTNEWINSTRING;
     283
     284/**
     285 * Port I/O Handler for OUT operations.
     286 *
     287 * @returns VINF_SUCCESS or VINF_EM_*.
     288 *
     289 * @param   pDevIns     The device instance.
     290 * @param   pvUser      User argument.
     291 * @param   uPort       Port number used for the OUT operation.
     292 * @param   u32         The value to output.
     293 * @param   cb          The value size in bytes.
     294 * @remarks Caller enters the device critical section.
     295 */
     296typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWOUT(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb);
     297/** Pointer to a FNIOMIOPORTNEWOUT(). */
     298typedef FNIOMIOPORTNEWOUT *PFNIOMIOPORTNEWOUT;
     299
     300/**
     301 * Port I/O Handler for string OUT operations.
     302 *
     303 * @returns VINF_SUCCESS or VINF_EM_*.
     304 *
     305 * @param   pDevIns     The device instance.
     306 * @param   pvUser      User argument.
     307 * @param   uPort       Port number used for the OUT operation.
     308 * @param   pbSrc       Pointer to the source buffer.
     309 * @param   pcTransfers Pointer to the number of transfer units to write, on
     310 *                      return remaining transfer units.
     311 * @param   cb          Size of the transfer unit (1, 2 or 4 bytes).
     312 * @remarks Caller enters the device critical section.
     313 */
     314typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWOUTSTRING(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, const uint8_t *pbSrc,
     315                                                           uint32_t *pcTransfers, unsigned cb);
     316/** Pointer to a FNIOMIOPORTNEWOUTSTRING(). */
     317typedef FNIOMIOPORTNEWOUTSTRING *PFNIOMIOPORTNEWOUTSTRING;
     318
    245319/**
    246320 * I/O port description.
    … …  
    338412
    339413VMMR3_INT_DECL(int)  IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
    340                                        uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    341                                        PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
     414                                       uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     415                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
    342416                                       const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
    343417VMMR3_INT_DECL(int)  IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
    … …  
    409483VMMR0_INT_DECL(void) IOMR0CleanupVM(PGVM pGVM);
    410484VMMR0_INT_DECL(int)  IOMR0IoPortSetUpContext(PGVM pGVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    411                                              PFNIOMIOPORTOUT pfnOut,  PFNIOMIOPORTIN pfnIn,
    412                                              PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser);
     485                                             PFNIOMIOPORTNEWOUT pfnOut,  PFNIOMIOPORTNEWIN pfnIn,
     486                                             PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser);
    413487VMMR0_INT_DECL(int)  IOMR0IoPortGrowRegistrationTables(PGVM pGVM, uint64_t cMinEntries);
    414488VMMR0_INT_DECL(int)  IOMR0IoPortGrowStatisticsTable(PGVM pGVM, uint64_t cMinEntries);

  • trunk/include/VBox/vmm/pdmdev.h

    r80943 r80960  
    10581058    DECLRCCALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
    10591059
     1060    /**
     1061     * Gets a bus by it's PDM ordinal (typically the parent bus).
     1062     *
     1063     * @returns Pointer to the device instance of the bus.
     1064     * @param   pDevIns         The PCI bus device instance.
     1065     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
     1066     */
     1067    DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
     1068
    10601069    /** Just a safety precaution. */
    10611070    uint32_t                    u32TheEnd;
    … …  
    11111120    DECLR0CALLBACKMEMBER(void,  pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
    11121121
    1113 
    11141122    /**
    11151123     * Acquires the PDM lock.
    … …  
    11281136     */
    11291137    DECLR0CALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
     1138
     1139    /**
     1140     * Gets a bus by it's PDM ordinal (typically the parent bus).
     1141     *
     1142     * @returns Pointer to the device instance of the bus.
     1143     * @param   pDevIns         The PCI bus device instance.
     1144     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
     1145     */
     1146    DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
    11301147
    11311148    /** Just a safety precaution. */
    … …  
    11381155
    11391156/** Current PDMPCIHLPR0 version number. */
    1140 #define PDM_PCIHLPR0_VERSION                    PDM_VERSION_MAKE(0xfffc, 3, 0)
     1157#define PDM_PCIHLPR0_VERSION                    PDM_VERSION_MAKE(0xfffc, 4, 0)
    11411158
    11421159/**
    … …  
    11901207
    11911208    /**
    1192      * Gets the address of the RC PCI Bus helpers.
    1193      *
    1194      * This should be called at both construction and relocation time
    1195      * to obtain the correct address of the RC helpers.
    1196      *
    1197      * @returns RC pointer to the PCI Bus helpers.
    1198      * @param   pDevIns         Device instance of the PCI Bus.
    1199      * @thread  EMT only.
    1200      */
    1201     DECLR3CALLBACKMEMBER(PCPDMPCIHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
    1202 
    1203     /**
    1204      * Gets the address of the R0 PCI Bus helpers.
    1205      *
    1206      * This should be called at both construction and relocation time
    1207      * to obtain the correct address of the R0 helpers.
    1208      *
    1209      * @returns R0 pointer to the PCI Bus helpers.
    1210      * @param   pDevIns         Device instance of the PCI Bus.
    1211      * @thread  EMT only.
    1212      */
    1213     DECLR3CALLBACKMEMBER(PCPDMPCIHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
    1214 
    1215     /**
    12161209     * Acquires the PDM lock.
    12171210     *
    … …  
    12291222     */
    12301223    DECLR3CALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
     1224
     1225    /**
     1226     * Gets a bus by it's PDM ordinal (typically the parent bus).
     1227     *
     1228     * @returns Pointer to the device instance of the bus.
     1229     * @param   pDevIns         The PCI bus device instance.
     1230     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
     1231     */
     1232    DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
    12311233
    12321234    /** Just a safety precaution. */
    … …  
    12391241
    12401242/** Current PDMPCIHLPR3 version number. */
    1241 #define PDM_PCIHLPR3_VERSION                    PDM_VERSION_MAKE(0xfffb, 3, 1)
     1243#define PDM_PCIHLPR3_VERSION                    PDM_VERSION_MAKE(0xfffb, 4, 0)
    12421244
    12431245
    … …  
    22972299     */
    22982300    DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
    2299                                                  uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    2300                                                  PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
     2301                                                 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     2302                                                 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
    23012303                                                 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
    23022304
    … …  
    44104412     */
    44114413    DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    4412                                                        PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    4413                                                        PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
     4414                                                       PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     4415                                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
    44144416                                                       void *pvUser));
    44154417
    … …  
    47664768     */
    47674769    DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    4768                                                        PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    4769                                                        PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
     4770                                                       PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     4771                                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
    47704772                                                       void *pvUser));
    47714773
    … …  
    55325534 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
    55335535 */
    5534 DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTOUT pfnOut,
    5535                                             PFNIOMIOPORTIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
     5536DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
     5537                                            PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
    55365538                                            PIOMIOPORTHANDLE phIoPorts)
    55375539{
    … …  
    55475549 */
    55485550DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
    5549                                       PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn, void *pvUser, const char *pszDesc,
     5551                                      PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
    55505552                                      PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
    55515553{
    … …  
    55585560 */
    55595561DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
    5560                                         uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    5561                                         PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser,
     5562                                        uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     5563                                        PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
    55625564                                        const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
    55635565{
    … …  
    55895591 */
    55905592DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    5591                                             PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn, void *pvUser)
     5593                                            PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
    55925594{
    55935595    return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
    … …  
    55985600 */
    55995601DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    5600                                               PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    5601                                               PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser)
     5602                                              PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     5603                                              PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
    56025604{
    56035605    return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);

  • trunk/include/VBox/vmm/pdmpcidevint.h

    r80943 r80960  
    178178    R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
    179179
    180     /** Pointer to the PCI bus of the device. (R0 ptr)
    181      * @note Only used by ich9pcibridgeSetIrq to find the host (root) bus. */
    182     R0PTRTYPE(struct DEVPCIBUS *)   pBusR0;
    183180    /** Page used for MSI-X state.            (R0 ptr) */
    184181    R0PTRTYPE(void *)               pMsixPageR0;
    185 
    186     /** Pointer to the PCI bus of the device. (RC ptr)
    187      * @note Only used by ich9pcibridgeSetIrq to find the host (root) bus. */
    188     RCPTRTYPE(struct DEVPCIBUS *)   pBusRC;
    189182    /** Page used for MSI-X state.            (RC ptr) */
    190183    RCPTRTYPE(void *)               pMsixPageRC;
    … …  
    211204    /** Offset to the PBA for MSI-X.   */
    212205    uint16_t                        offMsixPba;
    213 #if HC_ARCH_BITS == 32
    214     /** Add padding to align aIORegions to an 8 byte boundary. */
    215     uint8_t                         abPadding2[12];
    216 #endif
     206    /** Add padding to align aIORegions to an 16 byte boundary. */
     207    uint8_t                         abPadding2[HC_ARCH_BITS == 32 ? 4+8 : 4+8];
    217208
    218209    /** Pointer to bus specific data. (R3 ptr) */

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r80944 r80960  
    8585
    8686static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
    87 PDMBOTHCBDECL(int)  pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    88 PDMBOTHCBDECL(int)  pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
    89 PDMBOTHCBDECL(int)  pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    90 PDMBOTHCBDECL(int)  pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
    9187
    9288#ifdef IN_RING3
    … …  
    290286 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
    291287 *
    292  * @param   pPdmDev         The PDM device instance for the PCI bus.
     288 * @param   pDevIns         The PDM device instance for the PCI bus.
    293289 * @param   pGlobals        Device instance of the host PCI bus.
    294290 * @param   pBusCC          Context specific data for the PCI bus.
    … …  
    807803
    808804/**
    809  * @callback_method_impl{FNIOMIOPORTOUT, PCI address}
    810  */
    811 PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     805 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
     806 */
     807static DECLCALLBACK(VBOXSTRICTRC) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    812808{
    813809    LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
    … …  
    827823
    828824/**
    829  * @callback_method_impl{FNIOMIOPORTIN, PCI address}
    830  */
    831 PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     825 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
     826 */
     827static DECLCALLBACK(VBOXSTRICTRC) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    832828{
    833829    RT_NOREF2(Port, pvUser);
    … …  
    849845
    850846/**
    851  * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
    852  */
    853 PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     847 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
     848 */
     849static DECLCALLBACK(VBOXSTRICTRC) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    854850{
    855851    LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
    … …  
    864860    else
    865861        AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
    866     return VBOXSTRICTRC_TODO(rcStrict);
    867 }
    868 
    869 
    870 /**
    871  * @callback_method_impl{FNIOMIOPORTIN, PCI data}
    872  */
    873 PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     862    return rcStrict;
     863}
     864
     865
     866/**
     867 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
     868 */
     869static DECLCALLBACK(VBOXSTRICTRC) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    874870{
    875871    NOREF(pvUser);
    … …  
    880876        PCI_UNLOCK(pDevIns);
    881877        LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
    882         return VBOXSTRICTRC_TODO(rcStrict);
     878        return rcStrict;
    883879    }
    884880    AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
    … …  
    889885
    890886/**
    891  * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
    892  */
    893 DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     887 * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
     888 */
     889static DECLCALLBACK(VBOXSTRICTRC)
     890pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    894891{
    895892    RT_NOREF2(pvUser, Port);
    … …  
    908905
    909906/**
    910  * @callback_method_impl{FNIOMIOPORTIN, PCI data}
    911  */
    912 DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     907 * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
     908 */
     909static DECLCALLBACK(VBOXSTRICTRC)
     910pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    913911{
    914912    RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
    … …  
    12691267     * Validate and read configuration.
    12701268     */
    1271     if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
    1272         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
     1269    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
    12731270
    12741271    /* query whether we got an IOAPIC */
    … …  
    12791276                                N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
    12801277
    1281     /* check if RC code is enabled. */
    1282     bool fGCEnabled;
    1283     rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
    1284     if (RT_FAILURE(rc))
    1285         return PDMDEV_SET_ERROR(pDevIns, rc,
    1286                                 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
    1287 
    1288     /* check if R0 code is enabled. */
    1289     bool fR0Enabled;
    1290     rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
    1291     if (RT_FAILURE(rc))
    1292         return PDMDEV_SET_ERROR(pDevIns, rc,
    1293                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
    1294     Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
    1295 
     1278    Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic,  pDevIns->fR0Enabled, pDevIns->fRCEnabled));
     1279
     1280    /*
     1281     * Init data and register the PCI bus.
     1282     */
    12961283    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    12971284    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    12981285
    1299     /*
    1300      * Init data and register the PCI bus.
    1301      */
    13021286    pGlobals->uPciBiosIo   = 0xc000;
    13031287    pGlobals->uPciBiosMmio = 0xf0000000;
    … …  
    13681352     * Register I/O ports and save state.
    13691353     */
    1370     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
    1371     if (RT_FAILURE(rc))
    1372         return rc;
    1373     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
    1374     if (RT_FAILURE(rc))
    1375         return rc;
    1376     if (fGCEnabled)
    1377     {
    1378         rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
    1379         if (RT_FAILURE(rc))
    1380             return rc;
    1381         rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
    1382         if (RT_FAILURE(rc))
    1383             return rc;
    1384     }
    1385     if (fR0Enabled)
    1386     {
    1387         rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
    1388         if (RT_FAILURE(rc))
    1389             return rc;
    1390         rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
    1391         if (RT_FAILURE(rc))
    1392             return rc;
    1393     }
    1394 
    1395     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)");
    1396     if (RT_FAILURE(rc))
    1397         return rc;
     1354    static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
     1355    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
     1356                                     &pGlobals->hIoPortAddress);
     1357    AssertLogRelRCReturn(rc, rc);
     1358
     1359    static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
     1360    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
     1361                                     &pGlobals->hIoPortData);
     1362    AssertLogRelRCReturn(rc, rc);
     1363
     1364    static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
     1365    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
     1366                                     "i440FX (Fake PCI BIOS trigger)", s_aMagicDesc,  &pGlobals->hIoPortMagic);
     1367    AssertLogRelRCReturn(rc, rc);
    13981368
    13991369
    … …  
    14021372                                NULL, pciR3SaveExec, NULL,
    14031373                                NULL, pciR3LoadExec, NULL);
    1404     if (RT_FAILURE(rc))
    1405         return rc;
     1374    AssertLogRelRCReturn(rc, rc);
    14061375
    14071376    PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
    … …  
    14261395    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    14271396
     1397    /* Mirror the ring-3 device lock disabling: */
     1398    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     1399    AssertRCReturn(rc, rc);
     1400
     1401    /* Set up the RZ PCI bus callbacks: */
    14281402    PDMPCIBUSREGCC PciBusReg;
    14291403    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
    … …  
    14311405    PciBusReg.pfnSetIrq     = pciSetIrq;
    14321406    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
    1433     int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
    1434     AssertRC(rc);
     1407    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     1408    AssertRCReturn(rc, rc);
     1409
     1410    /* Set up I/O port callbacks, except for the magic port: */
     1411    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
     1412    AssertLogRelRCReturn(rc, rc);
     1413
     1414    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
     1415    AssertLogRelRCReturn(rc, rc);
    14351416
    14361417    return rc;
    … …  
    14471428    /* .uReserved0 = */             0,
    14481429    /* .szName = */                 "pci",
    1449     /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
     1430    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
    14501431    /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
    14511432    /* .cMaxInstances = */          1,
    … …  
    15311512     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    15321513     */
     1514#if 1
     1515    PDEVPCIBUSCC const  pBridgeBusCC  = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); /* For keep using our own pcihlp.  */
     1516    PPDMDEVINS const    pBridgeDevIns = pDevIns;                                 /* ditto */
     1517
     1518    PDEVPCIBUS          pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     1519    PPDMDEVINS          pDevInsBus;
     1520    PPDMPCIDEV          pPciDevBus    = &pBus->PciDev;
     1521    uint8_t             uDevFnBridge  = pPciDevBus->uDevFn;
     1522    int                 iIrqPinBridge = ((pPciDev->uDevFn >> 3) + iIrq) & 3;
     1523
     1524    /* Walk the chain until we reach the host bus. */
     1525    Assert(pBus->iBus != 0);
     1526    for (;;)
     1527    {
     1528        /* Get the parent. */
     1529        pDevInsBus = pBridgeBusCC->CTX_SUFF(pPciHlp)->pfnGetBusByNo(pBridgeDevIns, pPciDevBus->Int.s.idxPdmBus);
     1530        AssertLogRelReturnVoid(pDevInsBus);
     1531
     1532        pBus       = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
     1533        pPciDevBus = &pBus->PciDev;
     1534        if (pBus->iBus == 0)
     1535            break;
     1536
     1537        uDevFnBridge  = pPciDevBus->uDevFn;
     1538        iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
     1539    }
     1540
     1541    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
     1542    Assert(pDevInsBus->pReg == &g_DevicePCI);
     1543    pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
     1544                      uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
     1545#else  /* (old code for reference) */
    15331546    PDEVPCIBUS   pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    15341547    PDEVPCIBUSCC pBusCC        = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    … …  
    15501563    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
    15511564    pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), pBusCC, uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
     1565#endif
    15521566}
    15531567
    … …  
    18301844    /* .uReserved0 = */             0,
    18311845    /* .szName = */                 "pcibridge",
    1832     /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
     1846    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
    18331847    /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI,
    18341848    /* .cMaxInstances = */          ~0U,

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r80950 r80960  
    122122}
    123123
    124 PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     124static void ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    125125{
    126126    LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
    … …  
    129129}
    130130
    131 PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     131static void ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    132132{
    133133    /*
    … …  
    138138     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    139139     */
     140#if 1
     141    PDEVPCIBUSCC const  pBridgeBusCC  = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); /* For keep using our own pcihlp.  */
     142    PPDMDEVINS const    pBridgeDevIns = pDevIns;                                 /* ditto */
     143
     144    PDEVPCIBUS          pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     145    PPDMDEVINS          pDevInsBus;
     146    PPDMPCIDEV          pPciDevBus    = &pBus->PciDev;
     147    uint8_t             uDevFnBridge  = pPciDevBus->uDevFn;
     148    int                 iIrqPinBridge = ((pPciDev->uDevFn >> 3) + iIrq) & 3;
     149
     150    /* Walk the chain until we reach the host bus. */
     151    Assert(pBus->iBus != 0);
     152    for (;;)
     153    {
     154        /* Get the parent. */
     155        pDevInsBus = pBridgeBusCC->CTX_SUFF(pPciHlp)->pfnGetBusByNo(pBridgeDevIns, pPciDevBus->Int.s.idxPdmBus);
     156        AssertLogRelReturnVoid(pDevInsBus);
     157
     158        pBus       = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
     159        pPciDevBus = &pBus->PciDev;
     160        if (pBus->iBus == 0)
     161            break;
     162
     163        uDevFnBridge  = pPciDevBus->uDevFn;
     164        iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
     165    }
     166
     167    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
     168    Assert(pDevInsBus->pReg == &g_DevicePciIch9);
     169
     170    /*
     171     * For MSI/MSI-X enabled devices the iIrq doesn't denote the pin but rather a vector which is completely
     172     * orthogonal to the pin based approach. The vector is not subject to the pin based routing with PCI bridges.
     173     */
     174    int iIrqPinVector = iIrqPinBridge;
     175    if (   MsiIsEnabled(pPciDev)
     176        || MsixIsEnabled(pPciDev))
     177        iIrqPinVector = iIrq;
     178    ich9pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
     179                          uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
     180#else  /* (old code for reference) */
    140181    PDEVPCIBUS     pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    141182    PPDMPCIDEV     pPciDevBus    = pPciDev;
    … …  
    166207    ich9pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
    167208                          uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
     209#endif
    168210}
    169211
    … …  
    182224 * @param   cb          The value size in bytes.
    183225 */
    184 DECLCALLBACK(int) ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
     226static DECLCALLBACK(VBOXSTRICTRC)
     227ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
    185228{
    186229    RT_NOREF2(pvUser, uPort);
    … …  
    210253 * @param   cb          Number of bytes read.
    211254 */
    212 DECLCALLBACK(int) ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
     255static DECLCALLBACK(VBOXSTRICTRC)
     256ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
    213257{
    214258    RT_NOREF5(pDevIns, pvUser, uPort, pu32, cb);
    … …  
    234278 * @param   cb          The value size in bytes.
    235279 */
    236 PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
     280static DECLCALLBACK(VBOXSTRICTRC)
     281ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
    237282{
    238283    LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
    … …  
    258303
    259304/**
    260  * Port I/O Handler for PCI address IN operations.
     305 * @callback_method_impl{FNIOMIOPORTNEWIN,
     306 *                       Port I/O Handler for PCI data IN operations.
    261307 *
    262  * Emulates reads from Configuration Address Port at 0CF8h for
    263  * Configuration Mechanism #1.
    264  *
    265  * @returns VBox status code.
    266  *
    267  * @param   pDevIns     ICH9 device instance.
    268  * @param   pvUser      User argument - ignored.
    269  * @param   uPort       Port number used for the IN operation.
    270  * @param   pu32        Where to store the result.
    271  * @param   cb          Number of bytes read.
    272  */
    273 PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
     308 * Emulates reads from Configuration Address Port at 0CF8h for Configuration
     309 * Mechanism \#1.
     310 */
     311static DECLCALLBACK(VBOXSTRICTRC)
     312ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
    274313{
    275314    RT_NOREF2(uPort, pvUser);
    … …  
    291330
    292331
    293 /*
     332/**
    294333 * Perform configuration space write.
    295334 */
    … …  
    344383
    345384/**
    346  * Port I/O Handler for PCI data OUT operations.
     385 * @callback_method_impl{FNIOMIOPORTNEWOUT,
     386 *                       Port I/O Handler for PCI data OUT operations.
    347387 *
    348  * Emulates writes to Configuration Data Port at 0CFCh for
    349  * Configuration Mechanism #1.
    350  *
    351  * @returns VBox status code.
    352  *
    353  * @param   pDevIns     ICH9 device instance.
    354  * @param   pvUser      User argument - ignored.
    355  * @param   uPort       Port number used for the OUT operation.
    356  * @param   u32         The value to output.
    357  * @param   cb          The value size in bytes.
    358  */
    359 PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
     388 * Emulates writes to Configuration Data Port at 0CFCh for Configuration
     389 * Mechanism \#1.
     390 */
     391static DECLCALLBACK(VBOXSTRICTRC)
     392ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
    360393{
    361394    PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    362395    LogFlowFunc(("Port=%#x u32=%#x cb=%d (config=%#10x)\n", uPort, u32, cb, pThis->uConfigReg));
    363396    NOREF(pvUser);
     397
    364398    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    365399    if (!(uPort % cb))
    … …  
    367401        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
    368402
    369         do /* do-brain-dead-while-false-utter-stupidity-loop */
    370         {
    371             /* Configuration space mapping enabled? */
    372             if (!(pThis->uConfigReg & (1 << 31)))
    373                 break;
     403        if (pThis->uConfigReg & (1 << 31))
     404        {
    374405
    375406            /* Decode target device from Configuration Address Port */
    … …  
    379410            /* Perform configuration space write */
    380411            rcStrict = ich9pciConfigWrite(pDevIns, pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
    381         } while (0);
     412        }
    382413
    383414        PCI_UNLOCK(pDevIns);
    … …  
    385416    else
    386417        AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", uPort, u32, cb));
    387     return VBOXSTRICTRC_TODO(rcStrict);
    388 }
    389 
    390 
    391 /*
     418
     419    return rcStrict;
     420}
     421
     422
     423/**
    392424 * Perform configuration space read.
    393425 */
    … …  
    449481
    450482/**
    451  * Port I/O Handler for PCI data IN operations.
     483 * @callback_method_impl{FNIOMIOPORTNEWIN,
     484 *                       Port I/O Handler for PCI data IN operations.
    452485 *
    453  * Emulates reads from Configuration Data Port at 0CFCh for
    454  * Configuration Mechanism #1.
    455  *
    456  * @returns VBox status code.
    457  *
    458  * @param   pDevIns     ICH9 device instance.
    459  * @param   pvUser      User argument - ignored.
    460  * @param   uPort       Port number used for the IN operation.
    461  * @param   pu32        Where to store the result.
    462  * @param   cb          Number of bytes read.
    463  */
    464 PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
     486 * Emulates reads from Configuration Data Port at 0CFCh for Configuration
     487 * Mechanism \#1.
     488 */
     489static DECLCALLBACK(VBOXSTRICTRC)
     490ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
    465491{
    466492    NOREF(pvUser);
    … …  
    489515
    490516        LogFlowFunc(("Port=%#x cb=%#x (config=%#10x) -> %#x (%Rrc)\n", uPort, cb, *pu32, pThis->uConfigReg, VBOXSTRICTRC_VAL(rcStrict)));
    491         return VBOXSTRICTRC_TODO(rcStrict);
     517        return rcStrict;
    492518    }
    493519    AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", uPort, cb));
    … …  
    30273053    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    30283054
     3055    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     3056    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     3057    PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
     3058    Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot))); /* code used to memset it for some funny reason. just temp insurance. */
     3059
    30293060    /*
    30303061     * Validate and read configuration.
    30313062     */
    3032     if (!CFGMR3AreValuesValid(pCfg,
    3033                               "IOAPIC\0"
    3034                               "GCEnabled\0"
    3035                               "R0Enabled\0"
    3036                               "McfgBase\0"
    3037                               "McfgLength\0"
    3038                               ))
    3039         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
     3063    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC|McfgBase|McfgLength", "");
    30403064
    30413065    /* query whether we got an IOAPIC */
    3042     bool fUseIoApic;
    3043     int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
    3044     if (RT_FAILURE(rc))
    3045         return PDMDEV_SET_ERROR(pDevIns, rc,
    3046                                 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
    3047 
    3048     /* check if RC code is enabled. */
    3049     bool fGCEnabled;
    3050     rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
    3051     if (RT_FAILURE(rc))
    3052         return PDMDEV_SET_ERROR(pDevIns, rc,
    3053                                 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
    3054     /* check if R0 code is enabled. */
    3055     bool fR0Enabled;
    3056     rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
    3057     if (RT_FAILURE(rc))
    3058         return PDMDEV_SET_ERROR(pDevIns, rc,
    3059                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
    3060 
    3061     Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
     3066    int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pPciRoot->fUseIoApic, false /** @todo default to true? */);
     3067    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"IOAPIC\"")));
     3068
     3069    if (!pPciRoot->fUseIoApic)
     3070        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Must use IO-APIC with ICH9 chipset"));
     3071
     3072    rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
     3073    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\"")));
     3074
     3075    rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
     3076    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\"")));
     3077
     3078    Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
     3079         pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
    30623080
    30633081    /*
    30643082     * Init data.
    30653083     */
    3066     PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    3067     PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
    3068     PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    3069 
    3070     /* Zero out everything */
    3071     Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot)));
    3072     memset(pPciRoot, 0, sizeof(*pPciRoot)); /** @todo unnecessary as instance data is always set to zero by the allocator, see assertion above. */
    3073 
    30743084    /* And fill values */
    3075     if (!fUseIoApic)
    3076         return PDMDEV_SET_ERROR(pDevIns, rc,
    3077                                 N_("Must use IO-APIC with ICH9 chipset"));
    3078     rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
    3079     if (RT_FAILURE(rc))
    3080         return PDMDEV_SET_ERROR(pDevIns, rc,
    3081                                 N_("Configuration error: Failed to read \"McfgBase\""));
    3082     rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
    3083     if (RT_FAILURE(rc))
    3084         return PDMDEV_SET_ERROR(pDevIns, rc,
    3085                                 N_("Configuration error: Failed to read \"McfgLength\""));
    3086 
    30873085    pBusCC->pDevInsR3             = pDevIns;
    3088     pPciRoot->fUseIoApic          = fUseIoApic;
    30893086    pPciRoot->PciBus.fTypePiix3   = false;
    30903087    pPciRoot->PciBus.fTypeIch9    = true;
    … …  
    30923089    pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pPciRoot->PciBus.apDevices));
    30933090    AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
     3091
     3092    /*
     3093     * Disable default device locking.
     3094     */
     3095    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3096    AssertRCReturn(rc, rc);
    30943097
    30953098    /*
    … …  
    31403143
    31413144    /*
    3142      * Register I/O ports and save state.
     3145     * Register I/O ports.
    31433146     */
    3144     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
    3145     if (RT_FAILURE(rc))
    3146         return rc;
    3147     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
    3148     if (RT_FAILURE(rc))
    3149         return rc;
    3150     if (fGCEnabled)
    3151     {
    3152         rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
    3153         if (RT_FAILURE(rc))
    3154             return rc;
    3155         rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
    3156         if (RT_FAILURE(rc))
    3157             return rc;
    3158     }
    3159     if (fR0Enabled)
    3160     {
    3161         rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
    3162         if (RT_FAILURE(rc))
    3163             return rc;
    3164         rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
    3165         if (RT_FAILURE(rc))
    3166             return rc;
    3167     }
    3168 
    3169     rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead, NULL, NULL, "ICH9 (Fake PCI BIOS trigger)");
    3170     if (RT_FAILURE(rc))
    3171         return rc;
    3172 
     3147    static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
     3148    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead,
     3149                                     "ICH9 (PCI)", s_aAddrDesc, &pPciRoot->hIoPortAddress);
     3150    AssertLogRelRCReturn(rc, rc);
     3151
     3152    static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
     3153    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, ich9pciIOPortDataWrite, ich9pciIOPortDataRead,
     3154                                     "ICH9 (PCI)", s_aDataDesc, &pPciRoot->hIoPortData);
     3155    AssertLogRelRCReturn(rc, rc);
     3156
     3157    static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
     3158    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead,
     3159                                     "ICH9 (Fake PCI BIOS trigger)", s_aMagicDesc, &pPciRoot->hIoPortMagic);
     3160    AssertLogRelRCReturn(rc, rc);
     3161
     3162    /*
     3163     * MMIO handlers.
     3164     */
    31733165    if (pPciRoot->u64PciConfigMMioAddress != 0)
    31743166    {
     3167/** @todo implement new-style MMIO   */
    31753168        rc = PDMDevHlpMMIORegister(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, NULL /*pvUser*/,
    31763169                                   IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
    … …  
    31783171        AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc,  pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
    31793172
    3180         if (fGCEnabled)
     3173        if (pDevIns->fRCEnabled)
    31813174        {
    31823175            rc = PDMDevHlpMMIORegisterRC(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
    … …  
    31863179
    31873180
    3188         if (fR0Enabled)
     3181        if (pDevIns->fR0Enabled)
    31893182        {
    31903183            rc = PDMDevHlpMMIORegisterR0(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
    … …  
    31943187    }
    31953188
     3189    /*
     3190     * Saved state and info handlers.
     3191     */
    31963192    rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
    31973193                                sizeof(*pBus) + 16*128, "pgm",
    … …  
    31993195                                NULL, ich9pciR3SaveExec, NULL,
    32003196                                NULL, ich9pciR3LoadExec, NULL);
    3201     if (RT_FAILURE(rc))
    3202         return rc;
    3203 
     3197    AssertRCReturn(rc, rc);
    32043198
    32053199    /** @todo other chipset devices shall be registered too */
    … …  
    32933287    if (!RTStrCmp(pszExpressPortType, "EndPtDev"))
    32943288        return VBOX_PCI_EXP_TYPE_ENDPOINT;
    3295     else if (!RTStrCmp(pszExpressPortType, "LegEndPtDev"))
     3289    if (!RTStrCmp(pszExpressPortType, "LegEndPtDev"))
    32963290        return VBOX_PCI_EXP_TYPE_LEG_END;
    3297     else if (!RTStrCmp(pszExpressPortType, "RootCmplxRootPort"))
     3291    if (!RTStrCmp(pszExpressPortType, "RootCmplxRootPort"))
    32983292        return VBOX_PCI_EXP_TYPE_ROOT_PORT;
    3299     else if (!RTStrCmp(pszExpressPortType, "ExpressSwUpstream"))
     3293    if (!RTStrCmp(pszExpressPortType, "ExpressSwUpstream"))
    33003294        return VBOX_PCI_EXP_TYPE_UPSTREAM;
    3301     else if (!RTStrCmp(pszExpressPortType, "ExpressSwDownstream"))
     3295    if (!RTStrCmp(pszExpressPortType, "ExpressSwDownstream"))
    33023296        return VBOX_PCI_EXP_TYPE_DOWNSTREAM;
    3303     else if (!RTStrCmp(pszExpressPortType, "Express2PciBridge"))
     3297    if (!RTStrCmp(pszExpressPortType, "Express2PciBridge"))
    33043298        return VBOX_PCI_EXP_TYPE_PCI_BRIDGE;
    3305     else if (!RTStrCmp(pszExpressPortType, "Pci2ExpressBridge"))
     3299    if (!RTStrCmp(pszExpressPortType, "Pci2ExpressBridge"))
    33063300        return VBOX_PCI_EXP_TYPE_PCIE_BRIDGE;
    3307     else if (!RTStrCmp(pszExpressPortType, "RootCmplxIntEp"))
     3301    if (!RTStrCmp(pszExpressPortType, "RootCmplxIntEp"))
    33083302        return VBOX_PCI_EXP_TYPE_ROOT_INT_EP;
    3309     else if (!RTStrCmp(pszExpressPortType, "RootCmplxEc"))
     3303    if (!RTStrCmp(pszExpressPortType, "RootCmplxEc"))
    33103304        return VBOX_PCI_EXP_TYPE_ROOT_EC;
    33113305
    … …  
    33713365        if (pDev)
    33723366        {
    3373             pDev->Int.s.pBusRC += offDelta;
    33743367            if (pDev->Int.s.pMsixPageRC)
    33753368                pDev->Int.s.pMsixPageRC += offDelta;
    … …  
    34023395}
    34033396
     3397
    34043398/**
    34053399 * @interface_method_impl{PDMDEVREG,pfnDestruct}
    … …  
    34273421     * Validate and read configuration.
    34283422     */
    3429     if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0" "ExpressEnabled\0" "ExpressPortType\0"))
    3430         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
    3431 
    3432     /* check if RC code is enabled. */
    3433     bool fGCEnabled;
    3434     int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
    3435     if (RT_FAILURE(rc))
    3436         return PDMDEV_SET_ERROR(pDevIns, rc,
    3437                                 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
    3438 
    3439     /* check if R0 code is enabled. */
    3440     bool fR0Enabled;
    3441     rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
    3442     if (RT_FAILURE(rc))
    3443         return PDMDEV_SET_ERROR(pDevIns, rc,
    3444                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
    3445     Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
     3423    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "ExpressEnabled|ExpressPortType", "");
    34463424
    34473425    /* check if we're supposed to implement a PCIe bridge. */
    34483426    bool fExpress;
    3449     rc = CFGMR3QueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
    3450     if (RT_FAILURE(rc))
    3451         return PDMDEV_SET_ERROR(pDevIns, rc,
    3452                                 N_("Configuration error: Failed to query boolean value \"ExpressEnabled\""));
    3453 
    3454     char *pszExpressPortType;
    3455     rc = CFGMR3QueryStringAllocDef(pCfg, "ExpressPortType",
    3456                                    &pszExpressPortType, "RootCmplxIntEp");
    3457     if (RT_FAILURE(rc))
    3458         return PDMDEV_SET_ERROR(pDevIns, rc,
    3459                                 N_("LsiLogic configuration error: failed to read \"ExpressPortType\" as string"));
    3460 
    3461     uint8_t uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(pszExpressPortType);
    3462     MMR3HeapFree(pszExpressPortType);
    3463 
    3464     pDevIns->IBase.pfnQueryInterface = ich9pcibridgeQueryInterface;
     3427    int rc = CFGMR3QueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
     3428    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ExpressEnabled\"")));
     3429
     3430    char szExpressPortType[80];
     3431    rc = CFGMR3QueryStringDef(pCfg, "ExpressPortType", szExpressPortType, sizeof(szExpressPortType), "RootCmplxIntEp");
     3432    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string")));
     3433
     3434    uint8_t const uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(szExpressPortType);
     3435    Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n",
     3436         iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType));
    34653437
    34663438    /*
    34673439     * Init data and register the PCI bus.
    34683440     */
     3441    pDevIns->IBase.pfnQueryInterface = ich9pcibridgeQueryInterface;
     3442
    34693443    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    34703444    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     3445
    34713446    pBus->fTypePiix3  = false;
    34723447    pBus->fTypeIch9   = true;
    … …  
    34743449    pBusCC->pDevInsR3 = pDevIns;
    34753450    /** @todo r=klaus figure out how to extend this to allow PCIe config space
    3476      * extension, which increases the config space from 256 bytes to 4K. */
     3451     * extension, which increases the config space from 256 bytes to 4K.
     3452     * bird: What does this allocation have to do with PCIe config space?!?  */
    34773453    pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
    34783454    AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
    … …  
    35953571    rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
    35963572                                PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
    3597     if (RT_FAILURE(rc))
    3598         return rc;
     3573    AssertLogRelRCReturn(rc, rc);
     3574
    35993575    pBus->PciDev.Int.s.pfnBridgeConfigRead  = ich9pcibridgeConfigRead;
    36003576    pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
    … …  
    36103586                                NULL, ich9pcibridgeR3SaveExec, NULL,
    36113587                                NULL, ich9pcibridgeR3LoadExec, NULL);
    3612     if (RT_FAILURE(rc))
    3613         return rc;
    3614 
     3588    AssertLogRelRCReturn(rc, rc);
    36153589
    36163590    return VINF_SUCCESS;
    … …  
    36253599{
    36263600    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    3627     PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     3601    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    36283602    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    36293603
     3604    /* Mirror the ring-3 device lock disabling: */
     3605    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3606    AssertRCReturn(rc, rc);
     3607
     3608    /* Set up the RZ PCI bus callbacks: */
    36303609    PDMPCIBUSREGCC PciBusReg;
    36313610    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
    3632     PciBusReg.iBus          = pGlobals->PciBus.iBus;
     3611    PciBusReg.iBus          = pPciRoot->PciBus.iBus;
    36333612    PciBusReg.pfnSetIrq     = ich9pciSetIrq;
    36343613    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
    3635     int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
    3636     AssertRC(rc);
    3637 
    3638     /* Disable default device locking. */
    3639     rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3614    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
    36403615    AssertRCReturn(rc, rc);
     3616
     3617    /* Set up I/O port callbacks, except for the magic port: */
     3618    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pPciRoot->hIoPortAddress, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL);
     3619    AssertLogRelRCReturn(rc, rc);
     3620
     3621    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pPciRoot->hIoPortData, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL);
     3622    AssertLogRelRCReturn(rc, rc);
     3623
     3624    /* Set up MMIO callbacks: */
     3625    /** @todo new-style MMIO */
    36413626
    36423627    return rc;
    … …  
    36533638    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    36543639
     3640    /* Mirror the ring-3 device lock disabling: */
     3641    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3642    AssertRCReturn(rc, rc);
     3643
     3644    /* Set up the RZ PCI bus callbacks: */
    36553645    PDMPCIBUSREGCC PciBusReg;
    36563646    PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
    … …  
    36583648    PciBusReg.pfnSetIrq     = ich9pcibridgeSetIrq;
    36593649    PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
    3660     int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
    3661     AssertRC(rc);
    3662 
    3663     /* Disable default device locking. */
    3664     rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     3650    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
    36653651    AssertRCReturn(rc, rc);
    36663652
    … …  
    36783664    /* .uReserved0 = */             0,
    36793665    /* .szName = */                 "ich9pci",
    3680     /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
     3666    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
    36813667    /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
    36823668    /* .cMaxInstances = */          1,
    … …  
    37523738    /* .uReserved0 = */             0,
    37533739    /* .szName = */                 "ich9pcibridge",
    3754     /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
     3740    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
    37553741    /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI,
    37563742    /* .cMaxInstances = */          ~0U,

  • trunk/src/VBox/Devices/Bus/DevPciInternal.h

    r80943 r80960  
    169169    } Piix3;
    170170
     171    /** The address I/O port handle. */
     172    IOMIOPORTHANDLE         hIoPortAddress;
     173    /** The data I/O port handle. */
     174    IOMIOPORTHANDLE         hIoPortData;
     175    /** The magic I/O port handle. */
     176    IOMIOPORTHANDLE         hIoPortMagic;
     177
    171178#if 1 /* Will be moved into the BIOS "soon". */
    172179    /** Current bus number - obsolete (still used by DevPCI, but merge will fix that). */

  • trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h

    r80943 r80960  
    192192    pPciDev->Int.s.pBusR3           = pBus;
    193193    Assert(pBus == PDMINS_2_DATA(pDevIns, PDEVPCIBUS));
    194     pPciDev->Int.s.pBusR0           = PDMINS_2_DATA_R0PTR(pDevIns);
    195     pPciDev->Int.s.pBusRC           = PDMINS_2_DATA_RCPTR(pDevIns);
    196194    pPciDev->Int.s.pfnConfigRead    = NULL;
    197195    pPciDev->Int.s.pfnConfigWrite   = NULL;

  • trunk/src/VBox/Devices/PC/DevRTC.cpp

    r80704 r80960  
    348348 * @callback_method_impl{FNIOMIOPORTIN}
    349349 */
    350 PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
     350PDMBOTHCBDECL(VBOXSTRICTRC) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
    351351{
    352352    NOREF(pvUser);
    … …  
    406406 * @callback_method_impl{FNIOMIOPORTOUT}
    407407 */
    408 PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
     408PDMBOTHCBDECL(VBOXSTRICTRC) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
    409409{
    410410    NOREF(pvUser);

  • trunk/src/VBox/VMM/VMMAll/IOMAll.cpp

    r80679 r80960  
    104104         * Found an entry, get the data so we can leave the IOM lock.
    105105         */
    106         PFNIOMIOPORTIN pfnInCallback = pRegEntry->pfnInCallback;
    107         PPDMDEVINS     pDevIns       = pRegEntry->pDevIns;
     106        PFNIOMIOPORTNEWIN pfnInCallback = pRegEntry->pfnInCallback;
     107        PPDMDEVINS        pDevIns       = pRegEntry->pDevIns;
    108108#ifndef IN_RING3
    109109        if (   pfnInCallback
    … …  
    349349         * Found an entry, get the data so we can leave the IOM lock.
    350350         */
    351         PFNIOMIOPORTINSTRING pfnInStrCallback = pRegEntry->pfnInStrCallback;
    352         PFNIOMIOPORTIN       pfnInCallback    = pRegEntry->pfnInCallback;
    353         PPDMDEVINS           pDevIns          = pRegEntry->pDevIns;
     351        PFNIOMIOPORTNEWINSTRING pfnInStrCallback = pRegEntry->pfnInStrCallback;
     352        PFNIOMIOPORTNEWIN       pfnInCallback    = pRegEntry->pfnInCallback;
     353        PPDMDEVINS              pDevIns          = pRegEntry->pDevIns;
    354354#ifndef IN_RING3
    355355        if (   pfnInCallback
    … …  
    671671         * Found an entry, get the data so we can leave the IOM lock.
    672672         */
    673         PFNIOMIOPORTOUT pfnOutCallback   = pRegEntry->pfnOutCallback;
    674         PPDMDEVINS      pDevIns          = pRegEntry->pDevIns;
     673        PFNIOMIOPORTNEWOUT pfnOutCallback   = pRegEntry->pfnOutCallback;
     674        PPDMDEVINS         pDevIns          = pRegEntry->pDevIns;
    675675#ifndef IN_RING3
    676676        if (   pfnOutCallback
    … …  
    892892         * Found an entry, get the data so we can leave the IOM lock.
    893893         */
    894         PFNIOMIOPORTOUTSTRING   pfnOutStrCallback = pRegEntry->pfnOutStrCallback;
    895         PFNIOMIOPORTOUT         pfnOutCallback    = pRegEntry->pfnOutCallback;
    896         PPDMDEVINS              pDevIns           = pRegEntry->pDevIns;
     894        PFNIOMIOPORTNEWOUTSTRING   pfnOutStrCallback = pRegEntry->pfnOutStrCallback;
     895        PFNIOMIOPORTNEWOUT         pfnOutCallback    = pRegEntry->pfnOutCallback;
     896        PPDMDEVINS                 pDevIns           = pRegEntry->pDevIns;
    897897#ifndef IN_RING3
    898898        if (   pfnOutCallback

  • trunk/src/VBox/VMM/VMMR0/IOMR0.cpp

    r80645 r80960  
    9090 */
    9191VMMR0_INT_DECL(int)  IOMR0IoPortSetUpContext(PGVM pGVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    92                                              PFNIOMIOPORTOUT pfnOut,  PFNIOMIOPORTIN pfnIn,
    93                                              PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser)
     92                                             PFNIOMIOPORTNEWOUT pfnOut,  PFNIOMIOPORTNEWIN pfnIn,
     93                                             PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
    9494{
    9595    /*

  • trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

    r80943 r80960  
    192192/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
    193193static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
    194                                                           PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    195                                                           PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
     194                                                          PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     195                                                          PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
    196196                                                          void *pvUser)
    197197{
    … …  
    11101110
    11111111
     1112/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
     1113static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
     1114{
     1115    PDMDEV_ASSERT_DEVINS(pDevIns);
     1116    PGVM pGVM = pDevIns->Internal.s.pGVM;
     1117    AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
     1118    PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
     1119    LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
     1120    return pRetDevIns;
     1121}
     1122
     1123
    11121124/**
    11131125 * The Ring-0 PCI Bus Helper Callbacks.
    … …  
    11211133    pdmR0PciHlp_Lock,
    11221134    pdmR0PciHlp_Unlock,
     1135    pdmR0PciHlp_GetBusByNo,
    11231136    PDM_PCIHLPR0_VERSION, /* the end */
    11241137};

  • trunk/src/VBox/VMM/VMMR3/IOM.cpp

    r80679 r80960  
    148148static FNIOMIOPORTINSTRING  iomR3IOPortDummyInStr;
    149149static FNIOMIOPORTOUTSTRING iomR3IOPortDummyOutStr;
     150static FNIOMIOPORTNEWIN        iomR3IOPortDummyNewIn;
     151static FNIOMIOPORTNEWOUT       iomR3IOPortDummyNewOut;
     152static FNIOMIOPORTNEWINSTRING  iomR3IOPortDummyNewInStr;
     153static FNIOMIOPORTNEWOUTSTRING iomR3IOPortDummyNewOutStr;
    150154
    151155#ifdef VBOX_WITH_STATISTICS
    … …  
    452456 */
    453457VMMR3_INT_DECL(int)  IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
    454                                        uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    455                                        PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
     458                                       uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     459                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
    456460                                       const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
    457461{
    … …  
    524528    pVM->iom.s.paIoPortRegs[idx].pvUser             = pvUser;
    525529    pVM->iom.s.paIoPortRegs[idx].pDevIns            = pDevIns;
    526     pVM->iom.s.paIoPortRegs[idx].pfnOutCallback     = pfnOut    ? pfnOut    : iomR3IOPortDummyOut;
    527     pVM->iom.s.paIoPortRegs[idx].pfnInCallback      = pfnIn     ? pfnIn     : iomR3IOPortDummyIn;
    528     pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback  = pfnOutStr ? pfnOutStr : iomR3IOPortDummyOutStr;
    529     pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback   = pfnInStr  ? pfnInStr  : iomR3IOPortDummyInStr;
     530    pVM->iom.s.paIoPortRegs[idx].pfnOutCallback     = pfnOut    ? pfnOut    : iomR3IOPortDummyNewOut;
     531    pVM->iom.s.paIoPortRegs[idx].pfnInCallback      = pfnIn     ? pfnIn     : iomR3IOPortDummyNewIn;
     532    pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback  = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
     533    pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback   = pfnInStr  ? pfnInStr  : iomR3IOPortDummyNewInStr;
    530534    pVM->iom.s.paIoPortRegs[idx].pszDesc            = pszDesc;
    531535    pVM->iom.s.paIoPortRegs[idx].paExtDescs         = paExtDescs;
    … …  
    592596                        /* Insert after the entry we just considered: */
    593597                        pEntry += 1;
    594                         if (iEnd < cEntries)
    595                             memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - iEnd));
     598                        if (i < cEntries)
     599                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
    596600                        break;
    597601                    }
    … …  
    604608                    {
    605609                        /* Insert at the entry we just considered: */
    606                         if (iEnd < cEntries)
    607                             memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - iEnd));
     610                        if (i < cEntries)
     611                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
    608612                        break;
    609613                    }
    … …  
    761765
    762766        RTIOPORT uPortPrev = paEntries[0].uLastPort;
    763         for (i = 1; i <= cEntries; i++)
     767        for (i = 1; i < cEntries - 1; i++)
    764768        {
    765769            AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
    … …  
    16971701
    16981702/**
     1703 * @callback_method_impl{FNIOMIOPORTNEWIN,
     1704 *      Dummy Port I/O Handler for IN operations.}
     1705 */
     1706static DECLCALLBACK(VBOXSTRICTRC)
     1707iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     1708{
     1709    NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
     1710    switch (cb)
     1711    {
     1712        case 1: *pu32 = 0xff; break;
     1713        case 2: *pu32 = 0xffff; break;
     1714        case 4: *pu32 = UINT32_C(0xffffffff); break;
     1715        default:
     1716            AssertReleaseMsgFailed(("cb=%d\n", cb));
     1717            return VERR_IOM_IOPORT_IPE_2;
     1718    }
     1719    return VINF_SUCCESS;
     1720}
     1721
     1722
     1723/**
     1724 * @callback_method_impl{FNIOMIOPORTNEWINSTRING,
     1725 *      Dummy Port I/O Handler for string IN operations.}
     1726 */
     1727static DECLCALLBACK(VBOXSTRICTRC)
     1728iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst, uint32_t *pcTransfer, unsigned cb)
     1729{
     1730    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
     1731    return VINF_SUCCESS;
     1732}
     1733
     1734
     1735/**
     1736 * @callback_method_impl{FNIOMIOPORTNEWOUT,
     1737 *      Dummy Port I/O Handler for OUT operations.}
     1738 */
     1739static DECLCALLBACK(VBOXSTRICTRC)
     1740iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     1741{
     1742    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
     1743    return VINF_SUCCESS;
     1744}
     1745
     1746
     1747/**
     1748 * @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
     1749 *      Dummy Port I/O Handler for string OUT operations.}
     1750 */
     1751static DECLCALLBACK(VBOXSTRICTRC)
     1752iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc, uint32_t *pcTransfer, unsigned cb)
     1753{
     1754    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
     1755    return VINF_SUCCESS;
     1756}
     1757
     1758
     1759/**
    16991760 * Display a single I/O port ring-3 range.
    17001761 *

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r80949 r80960  
    9999/** @interface_method_impl{PDMDEVHLPR3,pfnIoPortCreateEx} */
    100100static DECLCALLBACK(int) pdmR3DevHlp_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
    101                                                     uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
    102                                                     PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
     101                                                    uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
     102                                                    PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
    103103                                                    const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
    104104{

  • trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

    r80333 r80960  
    295295
    296296
    297 /** @interface_method_impl{PDMPCIHLPR3,pfnGetRCHelpers} */
    298 static DECLCALLBACK(PCPDMPCIHLPRC) pdmR3PciHlp_GetRCHelpers(PPDMDEVINS pDevIns)
    299 {
    300     PDMDEV_ASSERT_DEVINS(pDevIns);
    301     PVM pVM = pDevIns->Internal.s.pVMR3;
    302     VM_ASSERT_EMT(pVM);
    303 
    304     RTRCPTR pRCHelpers = NIL_RTRCPTR;
    305     if (VM_IS_RAW_MODE_ENABLED(pVM))
    306     {
    307         int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciHlp", &pRCHelpers);
    308         AssertReleaseRC(rc);
    309         AssertRelease(pRCHelpers);
    310     }
    311 
    312     LogFlow(("pdmR3PciHlp_GetRCHelpers: caller='%s'/%d: returns %RRv\n",
    313              pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
    314     return pRCHelpers;
    315 }
    316 
    317 
    318 /** @interface_method_impl{PDMPCIHLPR3,pfnGetR0Helpers} */
    319 static DECLCALLBACK(PCPDMPCIHLPR0) pdmR3PciHlp_GetR0Helpers(PPDMDEVINS pDevIns)
    320 {
    321     PDMDEV_ASSERT_DEVINS(pDevIns);
    322     PVM pVM = pDevIns->Internal.s.pVMR3;
    323     VM_ASSERT_EMT(pVM);
    324     PCPDMPCIHLPR0 pR0Helpers = 0;
    325     int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciHlp", &pR0Helpers);
    326     AssertReleaseRC(rc);
    327     AssertRelease(pR0Helpers);
    328     LogFlow(("pdmR3PciHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
    329              pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
    330     return pR0Helpers;
     297/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
     298static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
     299{
     300    PDMDEV_ASSERT_DEVINS(pDevIns);
     301    PVM pVM = pDevIns->Internal.s.pVMR3;
     302    AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
     303    PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
     304    LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
     305    return pRetDevIns;
    331306}
    332307
    … …  
    342317    pdmR3PciHlp_IoApicSendMsi,
    343318    pdmR3PciHlp_IsMMIO2Base,
    344     pdmR3PciHlp_GetRCHelpers,
    345     pdmR3PciHlp_GetR0Helpers,
    346319    pdmR3PciHlp_Lock,
    347320    pdmR3PciHlp_Unlock,
     321    pdmR3PciHlp_GetBusByNo,
    348322    PDM_PCIHLPR3_VERSION, /* the end */
    349323};

  • trunk/src/VBox/VMM/include/IOMInternal.h

    r80679 r80960  
    167167    R0PTRTYPE(PPDMDEVINS)               pDevIns;
    168168    /** Pointer to OUT callback function. */
    169     R0PTRTYPE(PFNIOMIOPORTOUT)          pfnOutCallback;
     169    R0PTRTYPE(PFNIOMIOPORTNEWOUT)       pfnOutCallback;
    170170    /** Pointer to IN callback function. */
    171     R0PTRTYPE(PFNIOMIOPORTIN)           pfnInCallback;
     171    R0PTRTYPE(PFNIOMIOPORTNEWIN)        pfnInCallback;
    172172    /** Pointer to string OUT callback function. */
    173     R0PTRTYPE(PFNIOMIOPORTOUTSTRING)    pfnOutStrCallback;
     173    R0PTRTYPE(PFNIOMIOPORTNEWOUTSTRING) pfnOutStrCallback;
    174174    /** Pointer to string IN callback function. */
    175     R0PTRTYPE(PFNIOMIOPORTINSTRING)     pfnInStrCallback;
     175    R0PTRTYPE(PFNIOMIOPORTNEWINSTRING)  pfnInStrCallback;
    176176    /** The entry of the first statistics entry, UINT16_MAX if no stats. */
    177177    uint16_t                            idxStats;
    … …  
    196196    R3PTRTYPE(PPDMDEVINS)               pDevIns;
    197197    /** Pointer to OUT callback function. */
    198     R3PTRTYPE(PFNIOMIOPORTOUT)          pfnOutCallback;
     198    R3PTRTYPE(PFNIOMIOPORTNEWOUT)       pfnOutCallback;
    199199    /** Pointer to IN callback function. */
    200     R3PTRTYPE(PFNIOMIOPORTIN)           pfnInCallback;
     200    R3PTRTYPE(PFNIOMIOPORTNEWIN)        pfnInCallback;
    201201    /** Pointer to string OUT callback function. */
    202     R3PTRTYPE(PFNIOMIOPORTOUTSTRING)    pfnOutStrCallback;
     202    R3PTRTYPE(PFNIOMIOPORTNEWOUTSTRING) pfnOutStrCallback;
    203203    /** Pointer to string IN callback function. */
    204     R3PTRTYPE(PFNIOMIOPORTINSTRING)     pfnInStrCallback;
     204    R3PTRTYPE(PFNIOMIOPORTNEWINSTRING)  pfnInStrCallback;
    205205    /** Description / Name. For easing debugging. */
    206206    R3PTRTYPE(const char *)             pszDesc;
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