Changeset 81002 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Sep 25, 2019 9:12:34 AM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 133599
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 10 edited
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VMMAll/HMVMXAll.cpp (modified) (3 diffs)
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VMMAll/IEMAll.cpp (modified) (2 diffs)
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VMMAll/IEMAllCImplVmxInstr.cpp.h (modified) (1 diff)
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VMMAll/PGMAllPhys.cpp (modified) (6 diffs)
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VMMAll/TRPMAll.cpp (modified) (9 diffs)
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VMMR0/HMSVMR0.cpp (modified) (1 diff)
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VMMR0/HMVMXR0.cpp (modified) (3 diffs)
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VMMR3/TRPM.cpp (modified) (7 diffs)
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VMMR3/VMMGuruMeditation.cpp (modified) (2 diffs)
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include/TRPMInternal.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp
r80815 r81002 1122 1122 * @param uVector The event vector. 1123 1123 * @param enmTrpmEvent The TRPM event. 1124 * @param fIcebp Whether the \#DB vector is caused by an INT1/ICEBP 1125 * instruction. 1124 1126 */ 1125 VMM_INT_DECL(uint32_t) HMTrpmEventTypeToVmxEventType(uint8_t uVector, TRPMEVENT enmTrpmEvent )1127 VMM_INT_DECL(uint32_t) HMTrpmEventTypeToVmxEventType(uint8_t uVector, TRPMEVENT enmTrpmEvent, bool fIcebp) 1126 1128 { 1127 1129 uint32_t uIntInfoType = 0; 1128 1130 if (enmTrpmEvent == TRPM_TRAP) 1129 1131 { 1130 /** @todo r=ramshankar: TRPM currently offers no way to determine a \#DB that was 1131 * generated using INT1 (ICEBP). */ 1132 Assert(!fIcebp); 1132 1133 switch (uVector) 1133 1134 { … … 1156 1157 } 1157 1158 else if (enmTrpmEvent == TRPM_HARDWARE_INT) 1159 { 1160 Assert(!fIcebp); 1158 1161 uIntInfoType |= (VMX_IDT_VECTORING_INFO_TYPE_EXT_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT); 1162 } 1159 1163 else if (enmTrpmEvent == TRPM_SOFTWARE_INT) 1160 1164 { … … 1166 1170 break; 1167 1171 1172 case X86_XCPT_DB: 1173 { 1174 if (fIcebp) 1175 { 1176 uIntInfoType |= (VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT); 1177 break; 1178 } 1179 RT_FALL_THRU(); 1180 } 1168 1181 default: 1169 1182 uIntInfoType |= (VMX_IDT_VECTORING_INFO_TYPE_SW_INT << VMX_IDT_VECTORING_INFO_TYPE_SHIFT); -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r80808 r81002 14280 14280 uint8_t u8TrapNo; 14281 14281 TRPMEVENT enmType; 14282 RTGCUINTuErrCode;14282 uint32_t uErrCode; 14283 14283 RTGCPTR uCr2; 14284 int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, NULL /* pu8InstLen */); AssertRC(rc2); 14284 int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, NULL /* pu8InstLen */, NULL /* fIcebp */); 14285 AssertRC(rc2); 14285 14286 Assert(enmType == TRPM_HARDWARE_INT); 14286 14287 VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8TrapNo, enmType, (uint16_t)uErrCode, uCr2, 0 /* cbInstr */); … … 14663 14664 uint8_t u8TrapNo; 14664 14665 TRPMEVENT enmType; 14665 RTGCUINTuErrCode;14666 uint32_t uErrCode; 14666 14667 RTGCUINTPTR uCr2; 14667 14668 uint8_t cbInstr; 14668 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, &cbInstr );14669 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, &cbInstr, NULL /* fIcebp */); 14669 14670 if (RT_FAILURE(rc)) 14670 14671 return rc; 14671 14672 14673 /** @todo r=ramshankar: Pass ICEBP info. to IEMInjectTrap() below and handle 14674 * ICEBP \#DB injection as a special case. */ 14672 14675 VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8TrapNo, enmType, uErrCode, uCr2, cbInstr); 14673 14676 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
r80912 r81002 7091 7091 } 7092 7092 7093 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT) 7094 { 7095 TRPMSetTrapDueToIcebp(pVCpu); 7096 Log(("%s: Injecting: icebp\n", pszInstr)); 7097 } 7098 7093 7099 NOREF(pszInstr); 7094 7100 } -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r80333 r81002 3624 3624 VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb) 3625 3625 { 3626 NOREF(pCtxCore); 3626 3627 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 3627 3628 Assert(cb <= PAGE_SIZE); … … 3769 3770 } 3770 3771 Log(("PGMPhysInterpretedRead: GCPtrSrc=%RGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr)); 3771 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc); 3772 rc = TRPMAssertXcptPF(pVCpu, GCPtrSrc, uErr); 3773 if (RT_SUCCESS(rc)) 3774 return VINF_EM_RAW_GUEST_TRAP; 3775 return rc; 3772 3776 } 3773 3777 … … 3807 3811 bool fRaiseTrap) 3808 3812 { 3813 NOREF(pCtxCore); 3809 3814 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 3810 3815 Assert(cb <= PAGE_SIZE); … … 3963 3968 { 3964 3969 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrSrc, cb, uErr)); 3965 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc); 3970 rc = TRPMAssertXcptPF(pVCpu, GCPtrSrc, uErr); 3971 if (RT_SUCCESS(rc)) 3972 return VINF_EM_RAW_GUEST_TRAP; 3973 return rc; 3966 3974 } 3967 3975 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrSrc, cb, uErr)); … … 4000 4008 size_t cb, bool fRaiseTrap) 4001 4009 { 4010 NOREF(pCtxCore); 4002 4011 Assert(cb <= PAGE_SIZE); 4003 4012 PVMCC pVM = pVCpu->CTX_SUFF(pVM); … … 4171 4180 { 4172 4181 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrDst, cb, uErr)); 4173 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrDst); 4182 rc = TRPMAssertXcptPF(pVCpu, GCPtrDst, uErr); 4183 if (RT_SUCCESS(rc)) 4184 return VINF_EM_RAW_GUEST_TRAP; 4185 return rc; 4174 4186 } 4175 4187 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrDst, cb, uErr)); -
trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
r80333 r81002 93 93 * @param pVCpu The cross context virtual CPU structure. 94 94 */ 95 VMMDECL( RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu)95 VMMDECL(uint32_t) TRPMGetErrorCode(PVMCPU pVCpu) 96 96 { 97 97 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); … … 151 151 152 152 /** 153 * Checks if the current \#DB exception is due to an INT1/ICEBP instruction. 154 * 155 * The caller is responsible for making sure there is an active trap. 156 * 157 * @returns @c true if it's due to INT1/ICEBP, @c false if not. 158 * 159 * @param pVCpu The cross context virtual CPU structure. 160 */ 161 VMMDECL(bool) TRPMIsTrapDueToIcebp(PVMCPU pVCpu) 162 { 163 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 164 return pVCpu->trpm.s.fIcebp; 165 } 166 167 168 /** 153 169 * Clears the current active trap/exception/interrupt. 154 170 * … … 204 220 pVCpu->trpm.s.uActiveVector = u8TrapNo; 205 221 pVCpu->trpm.s.enmActiveType = enmType; 206 pVCpu->trpm.s.uActiveErrorCode = ~ (RTGCUINT)0;222 pVCpu->trpm.s.uActiveErrorCode = ~0U; 207 223 pVCpu->trpm.s.uActiveCR2 = 0xdeadface; 208 224 pVCpu->trpm.s.cbInstr = UINT8_MAX; 225 pVCpu->trpm.s.fIcebp = false; 209 226 return VINF_SUCCESS; 210 227 } … … 222 239 * @param uErrorCode The error code for the page-fault. 223 240 */ 224 VMMDECL(int) TRPMAssertXcptPF(PVMCPUCC pVCpu, RTGCUINTPTR uCR2, RTGCUINTuErrorCode)225 { 226 Log2(("TRPMAssertXcptPF: uCR2=%RGv uErrorCode=% RGv\n", uCR2, uErrorCode)); /** @todo RTGCUINT to be fixed. */241 VMMDECL(int) TRPMAssertXcptPF(PVMCPUCC pVCpu, RTGCUINTPTR uCR2, uint32_t uErrorCode) 242 { 243 Log2(("TRPMAssertXcptPF: uCR2=%RGv uErrorCode=%#RX32\n", uCR2, uErrorCode)); 227 244 228 245 /* … … 254 271 * @param uErrorCode The new error code. 255 272 */ 256 VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode) 257 { 258 Log2(("TRPMSetErrorCode: uErrorCode=%RGv\n", uErrorCode)); /** @todo RTGCUINT mess! */ 259 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 273 VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, uint32_t uErrorCode) 274 { 275 Log2(("TRPMSetErrorCode: uErrorCode=%#RX32\n", uErrorCode)); 276 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 277 AssertMsg( pVCpu->trpm.s.enmActiveType == TRPM_TRAP 278 || ( pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT && pVCpu->trpm.s.uActiveVector == X86_XCPT_DB), 279 ("Not hardware exception or privileged software exception (INT1/ICEBP)!\n")); 260 280 pVCpu->trpm.s.uActiveErrorCode = uErrorCode; 261 281 #ifdef VBOX_STRICT 262 switch (pVCpu->trpm.s.uActiveVector) 263 { 264 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP: case X86_XCPT_PF: 265 AssertMsg(uErrorCode != ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 266 break; 267 case X86_XCPT_AC: case X86_XCPT_DF: 268 AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 269 break; 270 default: 271 AssertMsg(uErrorCode == ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 272 break; 282 if (pVCpu->trpm.s.enmActiveType == TRPM_TRAP) 283 { 284 switch (pVCpu->trpm.s.uActiveVector) 285 { 286 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP: case X86_XCPT_PF: 287 AssertMsg(uErrorCode != ~0U, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 288 break; 289 case X86_XCPT_AC: case X86_XCPT_DF: 290 AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 291 break; 292 default: 293 AssertMsg(uErrorCode == ~0U, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector)); 294 break; 295 } 273 296 } 274 297 #endif … … 310 333 Log2(("TRPMSetInstrLength: cbInstr=%u\n", cbInstr)); 311 334 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 312 /** @todo We should be able to set the instruction length for a \#DB raised by313 * INT1/ICEBP as well. However, TRPM currently has no way to distinguish314 * INT1/ICEBP from regular \#DB. */315 335 AssertMsg( pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT 316 336 || ( pVCpu->trpm.s.enmActiveType == TRPM_TRAP … … 323 343 324 344 /** 345 * Sets if the current \#DB exception is due to an INT1/ICEBP instruction. 346 * 347 * The caller is responsible for making sure there is an active trap and it's a 348 * \#DB. 349 * 350 * @param pVCpu The cross context virtual CPU structure. 351 */ 352 VMMDECL(void) TRPMSetTrapDueToIcebp(PVMCPU pVCpu) 353 { 354 AssertMsg(pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT, ("Trap type for INT1/ICEBP invalid!")); 355 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_DB, ("INT1/ICEBP must be indicated by a #DB!\n")); 356 pVCpu->trpm.s.fIcebp = true; 357 } 358 359 360 /** 325 361 * Checks if the current active trap/interrupt/exception/fault/whatever is a software 326 362 * interrupt or not. … … 357 393 * 358 394 * @returns VBox status code. 359 * @param pVCpu The cross context virtual CPU structure. 360 * @param pu8TrapNo Where to store the trap number. 361 * @param pEnmType Where to store the trap type 362 * @param puErrorCode Where to store the error code associated with some traps. 363 * ~0U is stored if the trap has no error code. 364 * @param puCR2 Where to store the CR2 associated with a trap 0E. 365 * @param pcbInstr Where to store the instruction-length 366 * associated with some traps. 367 */ 368 VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, PRTGCUINT puErrorCode, PRTGCUINTPTR puCR2, 369 uint8_t *pcbInstr) 370 { 371 /* 372 * Check if we have a trap at present. 395 * @param pVCpu The cross context virtual CPU structure. 396 * @param pu8TrapNo Where to store the trap number. 397 * @param pEnmType Where to store the trap type. 398 * @param puErrorCode Where to store the error code associated with some 399 * traps. ~0U is stored if the trap has no error code. 400 * @param puCR2 Where to store the CR2 associated with a trap 0E. 401 * @param pcbInstr Where to store the instruction-length associated with 402 * some traps. 403 * @param pfIcebp Where to store whether the trap is a \#DB caused by an 404 * INT1/ICEBP instruction. 405 */ 406 VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, uint32_t *puErrorCode, PRTGCUINTPTR puCR2, 407 uint8_t *pcbInstr, bool *pfIcebp) 408 { 409 /* 410 * Check if we have an active trap. 373 411 */ 374 412 if (pVCpu->trpm.s.uActiveVector == ~0U) … … 385 423 if (pcbInstr) 386 424 *pcbInstr = pVCpu->trpm.s.cbInstr; 425 if (pfIcebp) 426 *pfIcebp = pVCpu->trpm.s.fIcebp; 387 427 return VINF_SUCCESS; 388 428 } 389 429 390 391 /**392 * Save the active trap.393 *394 * This routine useful when doing try/catch in the hypervisor.395 * Any function which uses temporary trap handlers should396 * probably also use this facility to save the original trap.397 *398 * @param pVCpu The cross context virtual CPU structure.399 */400 VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu)401 {402 pVCpu->trpm.s.uSavedVector = pVCpu->trpm.s.uActiveVector;403 pVCpu->trpm.s.enmSavedType = pVCpu->trpm.s.enmActiveType;404 pVCpu->trpm.s.uSavedErrorCode = pVCpu->trpm.s.uActiveErrorCode;405 pVCpu->trpm.s.uSavedCR2 = pVCpu->trpm.s.uActiveCR2;406 pVCpu->trpm.s.cbSavedInstr = pVCpu->trpm.s.cbInstr;407 }408 409 410 /**411 * Restore a saved trap.412 *413 * Multiple restores of a saved trap is possible.414 *415 * @param pVCpu The cross context virtual CPU structure.416 */417 VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu)418 {419 pVCpu->trpm.s.uActiveVector = pVCpu->trpm.s.uSavedVector;420 pVCpu->trpm.s.enmActiveType = pVCpu->trpm.s.enmSavedType;421 pVCpu->trpm.s.uActiveErrorCode = pVCpu->trpm.s.uSavedErrorCode;422 pVCpu->trpm.s.uActiveCR2 = pVCpu->trpm.s.uSavedCR2;423 pVCpu->trpm.s.cbInstr = pVCpu->trpm.s.cbSavedInstr;424 }425 426 427 /**428 * Raises a cpu exception which doesn't take an error code.429 *430 * This function may or may not dispatch the exception before returning.431 *432 * @returns VBox status code fit for scheduling.433 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.434 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.435 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.436 *437 * @param pVCpu The cross context virtual CPU structure of the calling EMT.438 * @param pCtxCore The CPU context core.439 * @param enmXcpt The exception.440 */441 VMMDECL(int) TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt)442 {443 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt));444 NOREF(pCtxCore);445 /** @todo dispatch the trap. */446 pVCpu->trpm.s.uActiveVector = enmXcpt;447 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;448 pVCpu->trpm.s.uActiveErrorCode = 0xdeadbeef;449 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;450 pVCpu->trpm.s.cbInstr = UINT8_MAX;451 return VINF_EM_RAW_GUEST_TRAP;452 }453 454 455 /**456 * Raises a cpu exception with an errorcode.457 *458 * This function may or may not dispatch the exception before returning.459 *460 * @returns VBox status code fit for scheduling.461 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.462 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.463 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.464 *465 * @param pVCpu The cross context virtual CPU structure of the calling EMT.466 * @param pCtxCore The CPU context core.467 * @param enmXcpt The exception.468 * @param uErr The error code.469 */470 VMMDECL(int) TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr)471 {472 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr));473 NOREF(pCtxCore);474 /** @todo dispatch the trap. */475 pVCpu->trpm.s.uActiveVector = enmXcpt;476 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;477 pVCpu->trpm.s.uActiveErrorCode = uErr;478 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;479 pVCpu->trpm.s.cbInstr = UINT8_MAX;480 return VINF_EM_RAW_GUEST_TRAP;481 }482 483 484 /**485 * Raises a cpu exception with an errorcode and CR2.486 *487 * This function may or may not dispatch the exception before returning.488 *489 * @returns VBox status code fit for scheduling.490 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.491 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.492 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.493 *494 * @param pVCpu The cross context virtual CPU structure of the calling EMT.495 * @param pCtxCore The CPU context core.496 * @param enmXcpt The exception.497 * @param uErr The error code.498 * @param uCR2 The CR2 value.499 */500 VMMDECL(int) TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2)501 {502 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr, uCR2));503 NOREF(pCtxCore);504 /** @todo dispatch the trap. */505 pVCpu->trpm.s.uActiveVector = enmXcpt;506 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;507 pVCpu->trpm.s.uActiveErrorCode = uErr;508 pVCpu->trpm.s.uActiveCR2 = uCR2;509 pVCpu->trpm.s.cbInstr = UINT8_MAX;510 return VINF_EM_RAW_GUEST_TRAP;511 }512 -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r80911 r81002 3383 3383 uint8_t uVector; 3384 3384 TRPMEVENT enmTrpmEvent; 3385 RTGCUINTuErrCode;3385 uint32_t uErrCode; 3386 3386 RTGCUINTPTR GCPtrFaultAddress; 3387 3387 uint8_t cbInstr; 3388 3388 3389 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr );3389 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */); 3390 3390 AssertRC(rc); 3391 3391 -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r80911 r81002 7828 7828 uint8_t uVector; 7829 7829 TRPMEVENT enmTrpmEvent; 7830 RTGCUINTuErrCode;7830 uint32_t uErrCode; 7831 7831 RTGCUINTPTR GCPtrFaultAddress; 7832 7832 uint8_t cbInstr; 7833 7834 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr); 7833 bool fIcebp; 7834 7835 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, &fIcebp); 7835 7836 AssertRC(rc); 7836 7837 7837 7838 uint32_t u32IntInfo; 7838 7839 u32IntInfo = uVector | VMX_IDT_VECTORING_INFO_VALID; 7839 u32IntInfo |= HMTrpmEventTypeToVmxEventType(uVector, enmTrpmEvent );7840 u32IntInfo |= HMTrpmEventTypeToVmxEventType(uVector, enmTrpmEvent, fIcebp); 7840 7841 7841 7842 rc = TRPMResetTrap(pVCpu); … … 7876 7877 else if (VMX_IDT_VECTORING_INFO_TYPE(u32IntInfo) == VMX_IDT_VECTORING_INFO_TYPE_SW_INT) 7877 7878 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr); 7879 7880 if (VMX_IDT_VECTORING_INFO_TYPE(u32IntInfo) == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT) 7881 TRPMSetTrapDueToIcebp(pVCpu); 7878 7882 7879 7883 /* We're now done converting the pending event. */ … … 13619 13623 { 13620 13624 /* It's a guest page fault and needs to be reflected to the guest. */ 13621 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);13625 uint32_t const uGstErrorCode = TRPMGetErrorCode(pVCpu); 13622 13626 TRPMResetTrap(pVCpu); 13623 13627 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */ -
trunk/src/VBox/VMM/VMMR3/TRPM.cpp
r80811 r81002 107 107 *********************************************************************************************************************************/ 108 108 /** TRPM saved state version. */ 109 #define TRPM_SAVED_STATE_VERSION 9 110 #define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */ 109 #define TRPM_SAVED_STATE_VERSION 10 110 #define TRPM_SAVED_STATE_VERSION_PRE_ICEBP 9 /* INT1/ICEBP support bumped the version */ 111 #define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */ 111 112 112 113 … … 247 248 LogFlow(("trpmR3Save:\n")); 248 249 249 /*250 * Active and saved traps.251 */252 250 for (VMCPUID i = 0; i < pVM->cCpus; i++) 253 251 { 254 PTRPMCPU pTrpmCpu = &pVM->apCpusR3[i]->trpm.s; 255 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector); 256 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType); 257 SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode); 258 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2); 259 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector); 260 SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType); 261 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode); 262 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2); 263 SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector); 264 } 265 SSMR3PutBool(pSSM, false /* raw-mode enabled */); 266 SSMR3PutUInt(pSSM, 0 /*was VMCPU_FF_TRPM_SYNC_IDT*/); 267 uint32_t au32IdtPatched[8]; 268 RT_ZERO(au32IdtPatched); 269 SSMR3PutMem(pSSM, &au32IdtPatched[0], sizeof(au32IdtPatched)); 270 SSMR3PutU32(pSSM, UINT32_MAX); /* separator. */ 271 /* Next came trampoline gates, terminating with UINT32_MAX. */ 272 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */ 252 PCTRPMCPU pTrpmCpu = &pVM->apCpusR3[i]->trpm.s; 253 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector); 254 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType); 255 SSMR3PutU32(pSSM, pTrpmCpu->uActiveErrorCode); 256 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2); 257 SSMR3PutU8(pSSM, pTrpmCpu->cbInstr); 258 SSMR3PutBool(pSSM, pTrpmCpu->fIcebp); 259 } 260 return VINF_SUCCESS; 273 261 } 274 262 … … 292 280 */ 293 281 if ( uVersion != TRPM_SAVED_STATE_VERSION 282 && uVersion != TRPM_SAVED_STATE_VERSION_PRE_ICEBP 294 283 && uVersion != TRPM_SAVED_STATE_VERSION_UNI) 295 284 { … … 298 287 } 299 288 300 /*301 * Call the reset function to kick out any handled gates and other potential trouble.302 */303 TRPMR3Reset(pVM);304 305 /*306 * Active and saved traps.307 */308 289 if (uVersion == TRPM_SAVED_STATE_VERSION) 309 290 { … … 313 294 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector); 314 295 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType); 315 SSMR3Get GCUInt(pSSM,&pTrpmCpu->uActiveErrorCode);296 SSMR3GetU32(pSSM, &pTrpmCpu->uActiveErrorCode); 316 297 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2); 317 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector); 318 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType); 319 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode); 320 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2); 321 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector); 322 } 323 324 bool fIgnored; 325 SSMR3GetBool(pSSM, &fIgnored); 298 SSMR3GetU8(pSSM, &pTrpmCpu->cbInstr); 299 SSMR3GetBool(pSSM, &pTrpmCpu->fIcebp); 300 } 326 301 } 327 302 else 328 303 { 329 PTRPMCPU pTrpmCpu = &pVM->apCpusR3[0]->trpm.s; 330 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector); 331 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType); 332 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode); 333 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2); 334 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector); 335 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType); 336 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode); 337 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2); 338 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector); 339 340 RTGCUINT fIgnored; 341 SSMR3GetGCUInt(pSSM, &fIgnored); 342 } 343 344 RTUINT fSyncIDT; 345 int rc = SSMR3GetUInt(pSSM, &fSyncIDT); 346 if (RT_FAILURE(rc)) 347 return rc; 348 AssertMsgReturn(!(fSyncIDT & ~1), ("fSyncIDT=%#x\n", fSyncIDT), VERR_SSM_DATA_UNIT_FORMAT_CHANGED); 349 350 uint32_t au32IdtPatched[8]; 351 SSMR3GetMem(pSSM, &au32IdtPatched[0], sizeof(au32IdtPatched)); 352 353 /* check the separator */ 354 uint32_t u32Sep; 355 rc = SSMR3GetU32(pSSM, &u32Sep); 356 if (RT_FAILURE(rc)) 357 return rc; 358 AssertMsgReturn(u32Sep == (uint32_t)~0, ("u32Sep=%#x (first)\n", u32Sep), VERR_SSM_DATA_UNIT_FORMAT_CHANGED); 359 360 /* 361 * Restore any trampoline gates. 362 */ 363 for (;;) 364 { 365 /* gate number / terminator */ 366 uint32_t iTrap; 367 rc = SSMR3GetU32(pSSM, &iTrap); 368 if (RT_FAILURE(rc)) 369 return rc; 370 if (iTrap == (uint32_t)~0) 371 break; 372 AssertMsgReturn(iTrap < 256, ("iTrap=%#x\n", iTrap), VERR_SSM_DATA_UNIT_FORMAT_CHANGED); 373 374 /* restore the IDT entry. */ 375 RTGCPTR GCPtrHandler; 376 SSMR3GetGCPtr(pSSM, &GCPtrHandler); 377 VBOXIDTE Idte; 378 rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte)); 379 if (RT_FAILURE(rc)) 380 return rc; 381 Assert(GCPtrHandler); 382 //pTrpm->aIdt[iTrap] = Idte; - not any more. 304 /* 305 * Active and saved traps. 306 */ 307 if (uVersion == TRPM_SAVED_STATE_VERSION_PRE_ICEBP) 308 { 309 for (VMCPUID i = 0; i < pVM->cCpus; i++) 310 { 311 RTGCUINT GCUIntErrCode; 312 PTRPMCPU pTrpmCpu = &pVM->apCpusR3[i]->trpm.s; 313 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector); 314 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType); 315 SSMR3GetGCUInt(pSSM, &GCUIntErrCode); 316 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2); 317 SSMR3Skip(pSSM, sizeof(RTGCUINT)); /* uSavedVector - No longer used. */ 318 SSMR3Skip(pSSM, sizeof(RTUINT)); /* enmSavedType - No longer used. */ 319 SSMR3Skip(pSSM, sizeof(RTGCUINT)); /* uSavedErrorCode - No longer used. */ 320 SSMR3Skip(pSSM, sizeof(RTGCUINTPTR)); /* uSavedCR2 - No longer used. */ 321 SSMR3Skip(pSSM, sizeof(RTGCUINT)); /* uPrevVector - No longer used. */ 322 323 /* 324 * We lose the high 64-bits here (if RTGCUINT is 64-bit) after making the 325 * active error code as 32-bits. However, for error codes even 16-bit should 326 * be sufficient. Despite this, we decided to use and keep it at 32-bits 327 * since VMX/SVM defines these as 32-bit in their event fields and converting 328 * to/from these events are safer. 329 */ 330 pTrpmCpu->uActiveErrorCode = GCUIntErrCode; 331 } 332 } 333 else 334 { 335 RTGCUINT GCUIntErrCode; 336 PTRPMCPU pTrpmCpu = &pVM->apCpusR3[0]->trpm.s; 337 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector); 338 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType); 339 SSMR3GetGCUInt(pSSM, &GCUIntErrCode); 340 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2); 341 pTrpmCpu->uActiveErrorCode = GCUIntErrCode; 342 } 343 344 /* 345 * Skip rest of TRPM saved-state unit involving IDT and trampoline gates. 346 * With the removal of raw-mode support, we no longer need these. 347 */ 348 SSMR3SkipToEndOfUnit(pSSM); 383 349 } 384 350 … … 467 433 uint8_t cbInstr; 468 434 TRPMEVENT enmTrapEvent; 469 RTGCUINTuErrorCode;435 uint32_t uErrorCode; 470 436 RTGCUINTPTR uCR2; 471 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrapEvent, &uErrorCode, &uCR2, &cbInstr); 437 bool fIcebp; 438 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrapEvent, &uErrorCode, &uCR2, &cbInstr, &fIcebp); 472 439 if (RT_SUCCESS(rc)) 473 440 { … … 483 450 pHlp->pfnPrintf(pHlp, " Type = %s\n", s_apszTrpmEventType[enmTrapEvent]); 484 451 pHlp->pfnPrintf(pHlp, " uVector = %#x\n", uVector); 485 pHlp->pfnPrintf(pHlp, " uErrorCode = %# RGu\n", uErrorCode);452 pHlp->pfnPrintf(pHlp, " uErrorCode = %#x\n", uErrorCode); 486 453 pHlp->pfnPrintf(pHlp, " uCR2 = %#RGp\n", uCR2); 487 454 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", cbInstr); 455 pHlp->pfnPrintf(pHlp, " fIcebp = %RTbool\n", fIcebp); 488 456 } 489 457 else -
trunk/src/VBox/VMM/VMMR3/VMMGuruMeditation.cpp
r80333 r81002 355 355 TRPMEVENT enmType; 356 356 uint8_t u8TrapNo = 0xce; 357 RTGCUINTuErrorCode = 0xdeadface;357 uint32_t uErrorCode = 0xdeadface; 358 358 RTGCUINTPTR uCR2 = 0xdeadface; 359 359 uint8_t cbInstr = UINT8_MAX; 360 int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, &cbInstr); 360 bool fIcebp = false; 361 int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, &cbInstr, &fIcebp); 361 362 if (VM_IS_RAW_MODE_ENABLED(pVM)) 362 363 { 363 364 if (RT_SUCCESS(rc2)) 364 365 pHlp->pfnPrintf(pHlp, 365 "!! TRAP=%02x ERRCD=%R Gv CR2=%RGv EIP=%RX32 Type=%d cbInstr=%02x\n",366 u8TrapNo, uErrorCode, uCR2, uEIP, enmType, cbInstr );366 "!! TRAP=%02x ERRCD=%RX32 CR2=%RGv EIP=%RX32 Type=%d cbInstr=%02x fIcebp=%RTbool\n", 367 u8TrapNo, uErrorCode, uCR2, uEIP, enmType, cbInstr, fIcebp); 367 368 else 368 369 pHlp->pfnPrintf(pHlp, … … 372 373 else if (RT_SUCCESS(rc2)) 373 374 pHlp->pfnPrintf(pHlp, 374 "!! ACTIVE TRAP=%02x ERRCD=%R Gv CR2=%RGv PC=%RGr Type=%d cbInstr=%02x(Guest!)\n",375 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVCpu), enmType, cbInstr );375 "!! ACTIVE TRAP=%02x ERRCD=%RX32 CR2=%RGv PC=%RGr Type=%d cbInstr=%02x fIcebp=%RTbool (Guest!)\n", 376 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVCpu), enmType, cbInstr, fIcebp); 376 377 377 378 /* -
trunk/src/VBox/VMM/include/TRPMInternal.h
r80938 r81002 72 72 73 73 /** Errorcode for the active interrupt/trap. */ 74 RTGCUINT uActiveErrorCode; /**< @todo don't use RTGCUINT */ 75 76 /** CR2 at the time of the active exception. */ 77 RTGCUINTPTR uActiveCR2; 78 79 /** Saved trap vector number. */ 80 RTGCUINT uSavedVector; /**< @todo don't use RTGCUINT */ 81 82 /** Saved errorcode. */ 83 RTGCUINT uSavedErrorCode; 84 85 /** Saved cr2. */ 86 RTGCUINTPTR uSavedCR2; 87 88 /** Saved trap type. */ 89 TRPMEVENT enmSavedType; 74 uint32_t uActiveErrorCode; 90 75 91 76 /** Instruction length for software interrupts and software exceptions … … 93 78 uint8_t cbInstr; 94 79 95 /** Saved instruction length. */96 uint8_t cbSavedInstr;80 /** Whether this \#DB trap is caused due to INT1/ICEBP. */ 81 bool fIcebp; 97 82 98 /** Padding. */ 99 uint8_t au8Padding[2]; 100 101 /** Previous trap vector # - for debugging. */ 102 RTGCUINT uPrevVector; 83 /** CR2 at the time of the active exception. */ 84 RTGCUINTPTR uActiveCR2; 103 85 } TRPMCPU; 104 86 105 87 /** Pointer to TRPMCPU Data. */ 106 88 typedef TRPMCPU *PTRPMCPU; 89 /** Pointer to const TRPMCPU Data. */ 90 typedef const TRPMCPU *PCTRPMCPU; 107 91 108 92 /** @} */
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