Changeset 81605 in vbox for trunk/include/iprt

Timestamp:

Oct 31, 2019 2:29:46 PM (5 years ago)

Author:

vboxsync

Message:

VMM (and related changes): Add support for Hygon Dhyana CPUs. Modified and improved contribution by Hongyong Zang submitted under MIT license. Thank you!

Location:

trunk/include/iprt

Files:

• asm-amd64-x86.h (modified) (1 diff)
• x86.h (modified) (1 diff)
• x86.mac (modified) (1 diff)

trunk/include/iprt/asm-amd64-x86.h

@@ -1587 +1587 @@
 
 /**
+ * Tests if it a genuine Hygon CPU based on the ASMCpuId(0) output.
+ *
+ * @returns true/false.
+ * @param   uEBX    EBX return from ASMCpuId(0)
+ * @param   uECX    ECX return from ASMCpuId(0)
+ * @param   uEDX    EDX return from ASMCpuId(0)
+ */
+DECLINLINE(bool) ASMIsHygonCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
+{
+    return uEBX == UINT32_C(0x6f677948)
+        && uECX == UINT32_C(0x656e6975)
+        && uEDX == UINT32_C(0x6e65476e);
+}
+
+
+/**
+ * Tests if this is a genuine Hygon CPU.
+ *
+ * @returns true/false.
+ * @remarks ASSUMES that cpuid is supported by the CPU.
+ */
+DECLINLINE(bool) ASMIsHygonCpu(void)
+{
+    uint32_t uEAX, uEBX, uECX, uEDX;
+    ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
+    return ASMIsHygonCpuEx(uEBX, uECX, uEDX);
+}
+
+
+/**
  * Checks whether ASMCpuId_EAX(0x00000000) indicates a valid range.
  *

trunk/include/iprt/x86.h

@@ -401 +401 @@
 #define X86_CPUID_VENDOR_SHANGHAI_ECX   0x20206961      /* ai   */
 #define X86_CPUID_VENDOR_SHANGHAI_EDX   0x68676e61      /* angh */
+
+#define X86_CPUID_VENDOR_HYGON_EBX      0x6f677948      /* Hygo */
+#define X86_CPUID_VENDOR_HYGON_ECX      0x656e6975      /* uine */
+#define X86_CPUID_VENDOR_HYGON_EDX      0x6e65476e      /* nGen */
 /** @} */
 

trunk/include/iprt/x86.mac

@@ -91 +91 @@
 %define X86_CPUID_VENDOR_SHANGHAI_ECX   0x20206961
 %define X86_CPUID_VENDOR_SHANGHAI_EDX   0x68676e61
+%define X86_CPUID_VENDOR_HYGON_EBX      0x6f677948
+%define X86_CPUID_VENDOR_HYGON_ECX      0x656e6975
+%define X86_CPUID_VENDOR_HYGON_EDX      0x6e65476e
 %define X86_CPUID_FEATURE_ECX_SSE3      RT_BIT_32(0)
 %define X86_CPUID_FEATURE_ECX_PCLMUL    RT_BIT_32(1)