Changeset 81860 in vbox for trunk/src/VBox/Devices/Storage
- Timestamp:
- Nov 15, 2019 3:45:18 AM (5 years ago)
- File:
-
- 1 edited
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- Added
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trunk/src/VBox/Devices/Storage/DevATA.cpp
r81859 r81860 156 156 /** @} */ 157 157 158 #define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) ) 159 #define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) ) 160 158 161 159 162 /********************************************************************************************************************************* … … 167 170 { 168 171 /** Command register. */ 169 uint8_t u8Cmd;172 uint8_t u8Cmd; 170 173 /** Status register. */ 171 uint8_t u8Status; 174 uint8_t u8Status; 175 /** Explicit alignment padding. */ 176 uint8_t abAlignment[2]; 172 177 /** Address of the MMIO region in the guest's memory space. */ 173 RTGCPHYS32 GCPhysAddr;178 RTGCPHYS32 GCPhysAddr; 174 179 } BMDMAState; 175 180 … … 186 191 187 192 /** 188 * The state of an ATA device. 189 * 190 * @implements PDMIBASE 191 * @implements PDMIBLOCKPORT 192 * @implements PDMIMOUNTNOTIFY 193 * The shared state of an ATA device. 193 194 */ 194 195 typedef struct ATADevState … … 354 355 uint64_t u64CmdTS; 355 356 357 /** The LUN number. */ 358 uint32_t iLUN; 359 /** The controller number. */ 360 uint8_t iCtl; 361 /** The device number. */ 362 uint8_t iDev; 363 /** Set if the device is present. */ 364 bool fPresent; 365 /** Explicit alignment. */ 366 uint8_t bAlignment2; 367 368 /** The serial number to use for IDENTIFY DEVICE commands. */ 369 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1]; 370 /** The firmware revision to use for IDENTIFY DEVICE commands. */ 371 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1]; 372 /** The model number to use for IDENTIFY DEVICE commands. */ 373 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1]; 374 /** The vendor identification string for SCSI INQUIRY commands. */ 375 char szInquiryVendorId[SCSI_INQUIRY_VENDOR_ID_LENGTH+1]; 376 /** The product identification string for SCSI INQUIRY commands. */ 377 char szInquiryProductId[SCSI_INQUIRY_PRODUCT_ID_LENGTH+1]; 378 /** The revision string for SCSI INQUIRY commands. */ 379 char szInquiryRevision[SCSI_INQUIRY_REVISION_LENGTH+1]; 380 381 /** Padding the structure to a multiple of 4096 for better I/O buffer alignment. */ 382 uint8_t abAlignment4[7 + 3544]; 383 } ATADEVSTATE, ATADevState; 384 AssertCompileMemberAlignment(ATADEVSTATE, cTotalSectors, 8); 385 AssertCompileMemberAlignment(ATADEVSTATE, StatATADMA, 8); 386 AssertCompileMemberAlignment(ATADEVSTATE, u64CmdTS, 8); 387 AssertCompileMemberAlignment(ATADEVSTATE, szSerialNumber, 8); 388 AssertCompileSizeAlignment(ATADEVSTATE, 4096); /* To align the buffer on a page boundrary. */ 389 /** Pointer to the shared state of an ATA device. */ 390 typedef ATADEVSTATE *PATADEVSTATE; 391 392 393 /** 394 * The ring-3 state of an ATA device. 395 * 396 * @implements PDMIBASE 397 * @implements PDMIBLOCKPORT 398 * @implements PDMIMOUNTNOTIFY 399 */ 400 typedef struct ATADEVSTATER3 401 { 356 402 /** Pointer to the attached driver's base interface. */ 357 403 R3PTRTYPE(PPDMIBASE) pDrvBase; … … 367 413 /** The mount notify interface. */ 368 414 PDMIMOUNTNOTIFY IMountNotify; 369 /** The LUN #. */ 370 RTUINT iLUN; 371 372 RTUINT Alignment2; /**< Align pDevInsR3 correctly. */ 373 374 /** Pointer to device instance. */ 375 PPDMDEVINSR3 pDevInsR3; 376 /** Pointer to controller instance. */ 377 R3PTRTYPE(struct ATACONTROLLER *) pControllerR3; 378 /** Pointer to device instance. */ 379 PPDMDEVINSR0 pDevInsR0; 380 /** Pointer to controller instance. */ 381 R0PTRTYPE(struct ATACONTROLLER *) pControllerR0; 382 /** Pointer to device instance. */ 383 PPDMDEVINSRC pDevInsRC; 384 /** Pointer to controller instance. */ 385 RCPTRTYPE(struct ATACONTROLLER *) pControllerRC; 386 387 /** The serial number to use for IDENTIFY DEVICE commands. */ 388 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1]; 389 /** The firmware revision to use for IDENTIFY DEVICE commands. */ 390 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1]; 391 /** The model number to use for IDENTIFY DEVICE commands. */ 392 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1]; 393 /** The vendor identification string for SCSI INQUIRY commands. */ 394 char szInquiryVendorId[SCSI_INQUIRY_VENDOR_ID_LENGTH+1]; 395 /** The product identification string for SCSI INQUIRY commands. */ 396 char szInquiryProductId[SCSI_INQUIRY_PRODUCT_ID_LENGTH+1]; 397 /** The revision string for SCSI INQUIRY commands. */ 398 char szInquiryRevision[SCSI_INQUIRY_REVISION_LENGTH+1]; 415 416 /** The LUN number. */ 417 uint32_t iLUN; 418 /** The controller number. */ 419 uint8_t iCtl; 420 /** The device number. */ 421 uint8_t iDev; 422 /** Explicit alignment. */ 423 uint8_t abAlignment2[2]; 424 /** The device instance so we can get our bearings from an interface method. */ 425 PPDMDEVINSR3 pDevIns; 426 399 427 /** The current tracklist of the loaded medium if passthrough is used. */ 400 428 R3PTRTYPE(PTRACKLIST) pTrackList; 401 402 uint8_t abAlignment4[HC_ARCH_BITS == 64 ? 7 + 3432 : 3 + 3432 + 13*4]; 403 } ATADevState; 404 AssertCompileMemberAlignment(ATADevState, cTotalSectors, 8); 405 AssertCompileMemberAlignment(ATADevState, StatATADMA, 8); 406 AssertCompileMemberAlignment(ATADevState, u64CmdTS, 8); 407 AssertCompileMemberAlignment(ATADevState, pDevInsR3, 8); 408 AssertCompileMemberAlignment(ATADevState, szSerialNumber, 8); 409 AssertCompileSizeAlignment(ATADevState, 4096); /* To align the buffer on a page boundrary. */ 429 } ATADEVSTATER3; 430 /** Pointer to the ring-3 state of an ATA device. */ 431 typedef ATADEVSTATER3 *PATADEVSTATER3; 410 432 411 433 … … 421 443 /** The index of the source sink callback to call for doing the transfer. */ 422 444 uint8_t iSourceSink; 445 /** Transfer direction. */ 446 uint8_t uTxDir; 423 447 /** How many bytes to transfer. */ 424 448 uint32_t cbTotalTransfer; 425 /** Transfer direction. */426 uint8_t uTxDir;427 449 } ATATransferRequest; 428 450 … … 480 502 481 503 /** 482 * The state of an ATA controller containing to devices (master and slave). 504 * The shared state of an ATA controller. 505 * 506 * Has two devices, the master (0) and the slave (1). 483 507 */ 484 508 typedef struct ATACONTROLLER … … 492 516 RTIOPORT IOPortBase2; 493 517 /** The assigned IRQ. */ 494 RTUINTirq;518 uint32_t irq; 495 519 /** Access critical section */ 496 520 PDMCRITSECT lock; … … 523 547 uint32_t cbRedoDMABuffer; 524 548 525 /** Pointer to device instance. */526 PPDMDEVINSR3 pDevInsR3;527 /** Pointer to device instance. */528 PPDMDEVINSR0 pDevInsR0;529 /** Pointer to device instance. */530 PPDMDEVINSRC pDevInsRC;531 532 /** Set when the destroying the device instance and the thread must exit. */533 uint32_t volatile fShutdown;534 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */535 RTTHREAD AsyncIOThread;536 549 /** The event semaphore the thread is waiting on for requests. */ 537 550 SUPSEMEVENT hAsyncIOSem; … … 542 555 /** The position at which to get a new request for the AIO thread. */ 543 556 volatile uint8_t AsyncIOReqTail; 544 /** Whether to call PDMDevHlpAsyncNotificationCompleted when idle. */ 545 bool volatile fSignalIdle; 546 uint8_t Alignment3[1]; /**< Explicit padding of the 1 byte gap. */ 557 /** The controller number. */ 558 uint8_t iCtl; 547 559 /** Magic delay before triggering interrupts in DMA mode. */ 548 560 uint32_t msDelayIRQ; 549 /** The event semaphore the thread is waiting on during suspended I/O. */550 RTSEMEVENT SuspendIOSem;551 561 /** The lock protecting the request queue. */ 552 562 PDMCRITSECT AsyncIORequestLock; … … 573 583 STAMPROFILEADV StatAsyncTime; 574 584 STAMPROFILE StatLockWait; 575 uint8_t abAlignment4[34 00];576 } ATACONTROLLER , *PATACONTROLLER;585 uint8_t abAlignment4[3456]; 586 } ATACONTROLLER; 577 587 AssertCompileMemberAlignment(ATACONTROLLER, lock, 8); 578 588 AssertCompileMemberAlignment(ATACONTROLLER, aIfs, 8); … … 580 590 AssertCompileMemberAlignment(ATACONTROLLER, StatAsyncOps, 8); 581 591 AssertCompileMemberAlignment(ATACONTROLLER, AsyncIORequestLock, 8); 582 AssertCompileSizeAlignment(ATACONTROLLER, 8);583 592 AssertCompileSizeAlignment(ATACONTROLLER, 4096); /* To align the controllers, devices and I/O buffers on page boundaries. */ 584 593 585 594 /** Pointer to the shared state of an ATA controller. */ 595 typedef ATACONTROLLER *PATACONTROLLER; 596 597 598 /** 599 * The ring-3 state of an ATA controller. 600 */ 601 typedef struct ATACONTROLLERR3 602 { 603 /** The ATA/ATAPI interfaces of this controller. */ 604 ATADEVSTATER3 aIfs[2]; 605 606 /** Pointer to device instance. */ 607 PPDMDEVINSR3 pDevIns; 608 609 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */ 610 RTTHREAD hAsyncIOThread; 611 /** The event semaphore the thread is waiting on during suspended I/O. */ 612 RTSEMEVENT hSuspendIOSem; 613 /** Set when the destroying the device instance and the thread must exit. */ 614 uint32_t volatile fShutdown; 615 /** Whether to call PDMDevHlpAsyncNotificationCompleted when idle. */ 616 bool volatile fSignalIdle; 617 618 /** The controller number. */ 619 uint8_t iCtl; 620 621 uint8_t abAlignment[3]; 622 } ATACONTROLLERR3; 623 /** Pointer to the ring-3 state of an ATA controller. */ 624 typedef ATACONTROLLERR3 *PATACONTROLLERR3; 625 626 627 /** ATA chipset type. */ 586 628 typedef enum CHIPSET 587 629 { … … 595 637 596 638 /** 597 * The state of the ATA PCI device. 639 * The shared state of a ATA PCI device. 640 */ 641 typedef struct PCIATAState 642 { 643 /** The controllers. */ 644 ATACONTROLLER aCts[2]; 645 /** Flag indicating chipset being emulated (CHIPSET). */ 646 uint8_t u8Type; 647 /** Explicit alignment padding. */ 648 uint8_t abAlignment1[7]; 649 /** PCI region \#4: Bus-master DMA I/O ports. */ 650 IOMIOPORTHANDLE hIoPortsBmDma; 651 } PCIATAState, ATASTATE; 652 /** Pointer to the shared state of an ATA PCI device. */ 653 typedef ATASTATE *PATASTATE; 654 655 656 /** 657 * The ring-3 state of a ATA PCI device. 598 658 * 599 659 * @implements PDMILEDPORTS 600 660 */ 601 typedef struct PCIATAState661 typedef struct ATASTATER3 602 662 { 603 663 /** The controllers. */ 604 ATACONTROLLER aCts[2]; 605 /** Pointer to device instance. */ 606 PPDMDEVINSR3 pDevIns; 664 ATACONTROLLERR3 aCts[2]; 607 665 /** Status LUN: Base interface. */ 608 666 PDMIBASE IBase; … … 613 671 /** Status LUN: Media Notify. */ 614 672 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify; 615 /** Flag whether RC is enabled. */ 616 bool fRCEnabled; 617 /** Flag whether R0 is enabled. */ 618 bool fR0Enabled; 619 /** Flag indicating chipset being emulated. */ 620 uint8_t u8Type; 621 bool Alignment0[HC_ARCH_BITS == 64 ? 5 : 1 ]; /**< Align the struct size. */ 622 /** PCI region \#4: Bus-master DMA I/O ports. */ 623 IOMIOPORTHANDLE hIoPortsBmDma; 624 } PCIATAState; 625 626 #define ATACONTROLLER_IDX(pController) ( (pController) - PDMDEVINS_2_DATA(CONTROLLER_2_DEVINS(pController), PCIATAState *)->aCts ) 627 628 #define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) ) 629 #define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) ) 630 #define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) ) 673 /** Pointer to device instance (for getting our bearings in interface methods). */ 674 PPDMDEVINSR3 pDevIns; 675 } ATASTATER3; 676 /** Pointer to the ring-3 state of an ATA PCI device. */ 677 typedef ATASTATER3 *PATASTATER3; 678 679 680 /** 681 * The ring-0 state of the ATA PCI device. 682 */ 683 typedef struct ATASTATER0 684 { 685 uint64_t uUnused; 686 } ATASTATER0; 687 /** Pointer to the ring-0 state of an ATA PCI device. */ 688 typedef ATASTATER0 *PATASTATER0; 689 690 691 /** 692 * The raw-mode state of the ATA PCI device. 693 */ 694 typedef struct ATASTATERC 695 { 696 uint64_t uUnused; 697 } ATASTATERC; 698 /** Pointer to the raw-mode state of an ATA PCI device. */ 699 typedef ATASTATERC *PATASTATERC; 700 701 702 /** The current context state of an ATA PCI device. */ 703 typedef CTX_SUFF(ATASTATE) ATASTATECC; 704 /** Pointer to the current context state of an ATA PCI device. */ 705 typedef CTX_SUFF(PATASTATE) PATASTATECC; 706 631 707 632 708 #ifndef VBOX_DEVICE_STRUCT_TESTCASE … … 634 710 635 711 #ifdef IN_RING3 636 DECLINLINE(void) ataSetStatusValue(ATADevState *s, uint8_t stat) 637 { 638 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 639 712 DECLINLINE(void) ataSetStatusValue(PATACONTROLLER pCtl, ATADevState *s, uint8_t stat) 713 { 640 714 /* Freeze status register contents while processing RESET. */ 641 715 if (!pCtl->fReset) … … 648 722 649 723 650 DECLINLINE(void) ataSetStatus(ATADevState *s, uint8_t stat) 651 { 652 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 653 724 DECLINLINE(void) ataSetStatus(PATACONTROLLER pCtl, ATADevState *s, uint8_t stat) 725 { 654 726 /* Freeze status register contents while processing RESET. */ 655 727 if (!pCtl->fReset) … … 661 733 662 734 663 DECLINLINE(void) ataUnsetStatus(ATADevState *s, uint8_t stat) 664 { 665 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 666 735 DECLINLINE(void) ataUnsetStatus(PATACONTROLLER pCtl, ATADevState *s, uint8_t stat) 736 { 667 737 /* Freeze status register contents while processing RESET. */ 668 738 if (!pCtl->fReset) … … 676 746 677 747 # ifdef IN_RING3 678 typedef void (*PFNBEGINTRANSFER)(ATADevState *); 679 typedef bool (*PFNSOURCESINK)(ATADevState *); 680 681 static void ataR3ReadWriteSectorsBT(ATADevState *); 682 static void ataR3PacketBT(ATADevState *); 683 static void atapiR3CmdBT(ATADevState *); 684 static void atapiR3PassthroughCmdBT(ATADevState *); 685 686 static bool ataR3IdentifySS(ATADevState *); 687 static bool ataR3FlushSS(ATADevState *); 688 static bool ataR3ReadSectorsSS(ATADevState *); 689 static bool ataR3WriteSectorsSS(ATADevState *); 690 static bool ataR3ExecuteDeviceDiagnosticSS(ATADevState *); 691 static bool ataR3TrimSS(ATADevState *); 692 static bool ataR3PacketSS(ATADevState *); 693 static bool ataR3InitDevParmSS(ATADevState *); 694 static bool ataR3RecalibrateSS(ATADevState *); 695 static bool atapiR3GetConfigurationSS(ATADevState *); 696 static bool atapiR3GetEventStatusNotificationSS(ATADevState *); 697 static bool atapiR3IdentifySS(ATADevState *); 698 static bool atapiR3InquirySS(ATADevState *); 699 static bool atapiR3MechanismStatusSS(ATADevState *); 700 static bool atapiR3ModeSenseErrorRecoverySS(ATADevState *); 701 static bool atapiR3ModeSenseCDStatusSS(ATADevState *); 702 static bool atapiR3ReadSS(ATADevState *); 703 static bool atapiR3ReadCapacitySS(ATADevState *); 704 static bool atapiR3ReadDiscInformationSS(ATADevState *); 705 static bool atapiR3ReadTOCNormalSS(ATADevState *); 706 static bool atapiR3ReadTOCMultiSS(ATADevState *); 707 static bool atapiR3ReadTOCRawSS(ATADevState *); 708 static bool atapiR3ReadTrackInformationSS(ATADevState *); 709 static bool atapiR3RequestSenseSS(ATADevState *); 710 static bool atapiR3PassthroughSS(ATADevState *); 711 static bool atapiR3ReadDVDStructureSS(ATADevState *); 748 typedef void FNBEGINTRANSFER(PATACONTROLLER pCtl, PATADEVSTATE s); 749 typedef FNBEGINTRANSFER *PFNBEGINTRANSFER; 750 typedef bool FNSOURCESINK(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3); 751 typedef FNSOURCESINK *PFNSOURCESINK; 752 753 static FNBEGINTRANSFER ataR3ReadWriteSectorsBT; 754 static FNBEGINTRANSFER ataR3PacketBT; 755 static FNBEGINTRANSFER atapiR3CmdBT; 756 static FNBEGINTRANSFER atapiR3PassthroughCmdBT; 757 758 static FNSOURCESINK ataR3IdentifySS; 759 static FNSOURCESINK ataR3FlushSS; 760 static FNSOURCESINK ataR3ReadSectorsSS; 761 static FNSOURCESINK ataR3WriteSectorsSS; 762 static FNSOURCESINK ataR3ExecuteDeviceDiagnosticSS; 763 static FNSOURCESINK ataR3TrimSS; 764 static FNSOURCESINK ataR3PacketSS; 765 static FNSOURCESINK ataR3InitDevParmSS; 766 static FNSOURCESINK ataR3RecalibrateSS; 767 static FNSOURCESINK atapiR3GetConfigurationSS; 768 static FNSOURCESINK atapiR3GetEventStatusNotificationSS; 769 static FNSOURCESINK atapiR3IdentifySS; 770 static FNSOURCESINK atapiR3InquirySS; 771 static FNSOURCESINK atapiR3MechanismStatusSS; 772 static FNSOURCESINK atapiR3ModeSenseErrorRecoverySS; 773 static FNSOURCESINK atapiR3ModeSenseCDStatusSS; 774 static FNSOURCESINK atapiR3ReadSS; 775 static FNSOURCESINK atapiR3ReadCapacitySS; 776 static FNSOURCESINK atapiR3ReadDiscInformationSS; 777 static FNSOURCESINK atapiR3ReadTOCNormalSS; 778 static FNSOURCESINK atapiR3ReadTOCMultiSS; 779 static FNSOURCESINK atapiR3ReadTOCRawSS; 780 static FNSOURCESINK atapiR3ReadTrackInformationSS; 781 static FNSOURCESINK atapiR3RequestSenseSS; 782 static FNSOURCESINK atapiR3PassthroughSS; 783 static FNSOURCESINK atapiR3ReadDVDStructureSS; 712 784 # endif /* IN_RING3 */ 713 785 … … 821 893 822 894 # ifdef IN_RING3 823 static void ataR3AsyncIOClearRequests(P ATACONTROLLER pCtl)824 { 825 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);895 static void ataR3AsyncIOClearRequests(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 896 { 897 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 826 898 AssertRC(rc); 827 899 … … 829 901 pCtl->AsyncIOReqTail = 0; 830 902 831 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);903 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 832 904 AssertRC(rc); 833 905 } 834 906 # endif /* IN_RING3 */ 835 907 836 static void ataHCAsyncIOPutRequest(P ATACONTROLLER pCtl, const ATARequest *pReq)837 { 838 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);908 static void ataHCAsyncIOPutRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, const ATARequest *pReq) 909 { 910 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 839 911 AssertRC(rc); 840 912 841 Assert((pCtl->AsyncIOReqHead + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail);842 memcpy(&pCtl->aAsyncIORequests[pCtl->AsyncIOReqHead], pReq, sizeof(*pReq));843 pCtl->AsyncIOReqHead++;844 pCtl->AsyncIOReqHead %=RT_ELEMENTS(pCtl->aAsyncIORequests);845 846 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);913 uint8_t const iAsyncIORequest = pCtl->AsyncIOReqHead % RT_ELEMENTS(pCtl->aAsyncIORequests); 914 Assert((iAsyncIORequest + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail); 915 memcpy(&pCtl->aAsyncIORequests[iAsyncIORequest], pReq, sizeof(*pReq)); 916 pCtl->AsyncIOReqHead = (iAsyncIORequest + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests); 917 918 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 847 919 AssertRC(rc); 848 920 849 rc = PDMDevHlpCritSectScheduleExitEvent(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, pCtl->hAsyncIOSem);921 rc = PDMDevHlpCritSectScheduleExitEvent(pDevIns, &pCtl->lock, pCtl->hAsyncIOSem); 850 922 if (RT_FAILURE(rc)) 851 923 { 852 rc = PDMDevHlpSUPSemEventSignal(p Ctl->CTX_SUFF(pDevIns), pCtl->hAsyncIOSem);924 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pCtl->hAsyncIOSem); 853 925 AssertRC(rc); 854 926 } … … 857 929 # ifdef IN_RING3 858 930 859 static const ATARequest *ataR3AsyncIOGetCurrentRequest(P ATACONTROLLER pCtl)931 static const ATARequest *ataR3AsyncIOGetCurrentRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 860 932 { 861 933 const ATARequest *pReq; 862 934 863 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);935 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 864 936 AssertRC(rc); 865 937 … … 869 941 pReq = NULL; 870 942 871 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);943 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 872 944 AssertRC(rc); 873 945 return pReq; … … 883 955 * @param ReqType Type of the request to remove. 884 956 */ 885 static void ataR3AsyncIORemoveCurrentRequest(P ATACONTROLLER pCtl, ATAAIO ReqType)886 { 887 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);957 static void ataR3AsyncIORemoveCurrentRequest(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATAAIO ReqType) 958 { 959 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 888 960 AssertRC(rc); 889 961 … … 894 966 } 895 967 896 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);968 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 897 969 AssertRC(rc); 898 970 } … … 906 978 * @param pCtl Controller for which to dump the queue. 907 979 */ 908 static void ataR3AsyncIODumpRequests(P ATACONTROLLER pCtl)909 { 910 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);980 static void ataR3AsyncIODumpRequests(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 981 { 982 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 911 983 AssertRC(rc); 912 984 913 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", ATACONTROLLER_IDX(pCtl)));985 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", pCtl->iCtl)); 914 986 uint8_t curr = pCtl->AsyncIOReqTail; 915 987 do 916 988 { 917 989 if (curr == pCtl->AsyncIOReqHead) 918 LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", ATACONTROLLER_IDX(pCtl)));990 LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", pCtl->iCtl)); 919 991 switch (pCtl->aAsyncIORequests[curr].ReqType) 920 992 { … … 947 1019 } while (curr != pCtl->AsyncIOReqTail); 948 1020 949 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);1021 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 950 1022 AssertRC(rc); 951 1023 } … … 959 1031 * @param fStrict If set then the controller is checked to be idle. 960 1032 */ 961 static bool ataR3AsyncIOIsIdle(P ATACONTROLLER pCtl, bool fStrict)962 { 963 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);1033 static bool ataR3AsyncIOIsIdle(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, bool fStrict) 1034 { 1035 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 964 1036 AssertRC(rc); 965 1037 … … 970 1042 fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW); 971 1043 972 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);1044 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 973 1045 AssertRC(rc); 974 1046 return fIdle; … … 979 1051 * Send a transfer request to the async I/O thread. 980 1052 * 1053 * @param pDevIns The device instance. 1054 * @param pCtl The ATA controller. 981 1055 * @param s Pointer to the ATA device state data. 982 1056 * @param cbTotalTransfer Data transfer size. … … 986 1060 * @param fChainedTransfer Whether this is a transfer that is part of the previous command/transfer. 987 1061 */ 988 static void ataR3StartTransfer(ATADevState *s, uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer, 1062 static void ataR3StartTransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s, 1063 uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer, 989 1064 ATAFNSS iSourceSink, bool fChainedTransfer) 990 1065 { 991 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);992 1066 ATARequest Req; 993 1067 994 Assert(PDMDevHlpCritSectIsOwner(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock));1068 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock)); 995 1069 996 1070 /* Do not issue new requests while the RESET line is asserted. */ 997 1071 if (pCtl->fReset) 998 1072 { 999 Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));1073 Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, pCtl->iCtl)); 1000 1074 return; 1001 1075 } … … 1004 1078 * the command that is being submitted. Some broken guests issue commands 1005 1079 * twice (e.g. the Linux kernel that comes with Acronis True Image 8). */ 1006 if (!fChainedTransfer && !ataR3AsyncIOIsIdle(pCtl, true /*fStrict*/)) 1007 { 1008 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", 1009 __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegCommand, pCtl->uAsyncIOState)); 1080 if (!fChainedTransfer && !ataR3AsyncIOIsIdle(pDevIns, pCtl, true /*fStrict*/)) 1081 { 1082 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, pCtl->iCtl, s->uATARegCommand, pCtl->uAsyncIOState)); 1010 1083 LogRel(("PIIX3 IDE: guest issued command %#04x while controller busy\n", s->uATARegCommand)); 1011 1084 return; … … 1021 1094 Req.u.t.iBeginTransfer = iBeginTransfer; 1022 1095 Req.u.t.iSourceSink = iSourceSink; 1023 ataSetStatusValue( s, ATA_STAT_BUSY);1096 ataSetStatusValue(pCtl, s, ATA_STAT_BUSY); 1024 1097 pCtl->fChainedTransfer = fChainedTransfer; 1025 1098 … … 1027 1100 * Kick the worker thread into action. 1028 1101 */ 1029 Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));1030 ataHCAsyncIOPutRequest(p Ctl, &Req);1102 Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, pCtl->iCtl)); 1103 ataHCAsyncIOPutRequest(pDevIns, pCtl, &Req); 1031 1104 } 1032 1105 … … 1035 1108 * Send an abort command request to the async I/O thread. 1036 1109 * 1110 * @param pDevIns The device instance. 1111 * @param pCtl The ATA controller. 1037 1112 * @param s Pointer to the ATA device state data. 1038 1113 * @param fResetDrive Whether to reset the drive or just abort a command. 1039 1114 */ 1040 static void ataR3AbortCurrentCommand(ATADevState *s, bool fResetDrive) 1041 { 1042 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1115 static void ataR3AbortCurrentCommand(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s, bool fResetDrive) 1116 { 1043 1117 ATARequest Req; 1044 1118 1045 Assert(PDMDevHlpCritSectIsOwner(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock));1119 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock)); 1046 1120 1047 1121 /* Do not issue new requests while the RESET line is asserted. */ 1048 1122 if (pCtl->fReset) 1049 1123 { 1050 Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));1124 Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, pCtl->iCtl)); 1051 1125 return; 1052 1126 } … … 1055 1129 Req.u.a.iIf = pCtl->iSelectedIf; 1056 1130 Req.u.a.fResetDrive = fResetDrive; 1057 ataSetStatus(s, ATA_STAT_BUSY); 1058 Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->iLUN)); 1059 ataHCAsyncIOPutRequest(pCtl, &Req); 1060 } 1131 ataSetStatus(pCtl, s, ATA_STAT_BUSY); 1132 Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, pCtl->iCtl, s->iLUN)); 1133 ataHCAsyncIOPutRequest(pDevIns, pCtl, &Req); 1134 } 1135 1061 1136 # endif /* IN_RING3 */ 1062 1137 … … 1064 1139 * Set the internal interrupt pending status, update INTREQ as appropriate. 1065 1140 * 1141 * @param pDevIns The device instance. 1142 * @param pCtl The ATA controller. 1066 1143 * @param s Pointer to the ATA device state data. 1067 1144 */ 1068 static void ataHCSetIRQ(ATADevState *s) 1069 { 1070 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1071 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s); 1072 1073 if (!s->fIrqPending) { 1145 static void ataHCSetIRQ(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s) 1146 { 1147 if (!s->fIrqPending) 1148 { 1074 1149 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)) 1075 1150 { … … 1098 1173 * Clear the internal interrupt pending status, update INTREQ as appropriate. 1099 1174 * 1175 * @param pDevIns The device instance. 1176 * @param pCtl The ATA controller. 1100 1177 * @param s Pointer to the ATA device state data. 1101 1178 */ 1102 static void ataUnsetIRQ(ATADevState *s) 1103 { 1104 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1105 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s); 1106 1107 if (s->fIrqPending) { 1179 static void ataUnsetIRQ(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s) 1180 { 1181 if (s->fIrqPending) 1182 { 1108 1183 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)) 1109 1184 { … … 1124 1199 #if defined(IN_RING0) || defined(IN_RING3) 1125 1200 1126 static void ataHCPIOTransferStart( ATADevState *s, uint32_t start, uint32_t size)1201 static void ataHCPIOTransferStart(PATACONTROLLER pCtl, ATADevState *s, uint32_t start, uint32_t size) 1127 1202 { 1128 1203 Log2(("%s: LUN#%d start %d size %d\n", __FUNCTION__, s->iLUN, start, size)); 1129 1204 s->iIOBufferPIODataStart = start; 1130 1205 s->iIOBufferPIODataEnd = start + size; 1131 ataSetStatus( s, ATA_STAT_DRQ | ATA_STAT_SEEK);1132 ataUnsetStatus( s, ATA_STAT_BUSY);1133 } 1134 1135 1136 static void ataHCPIOTransferStop( ATADevState *s)1206 ataSetStatus(pCtl, s, ATA_STAT_DRQ | ATA_STAT_SEEK); 1207 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY); 1208 } 1209 1210 1211 static void ataHCPIOTransferStop(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s) 1137 1212 { 1138 1213 Log2(("%s: LUN#%d\n", __FUNCTION__, s->iLUN)); … … 1141 1216 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD; 1142 1217 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector)); 1143 ataHCSetIRQ( s);1218 ataHCSetIRQ(pDevIns, pCtl, s); 1144 1219 s->fATAPITransfer = false; 1145 1220 } … … 1183 1258 * 1184 1259 * @returns nothing. 1260 * @param pDevIns The device instance. 1185 1261 * @param pCtl The controller to lock. 1186 1262 */ 1187 DECLINLINE(void) ataR3LockEnter(P ATACONTROLLER pCtl)1263 DECLINLINE(void) ataR3LockEnter(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 1188 1264 { 1189 1265 STAM_PROFILE_START(&pCtl->StatLockWait, a); 1190 PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_SUCCESS);1266 PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_SUCCESS); 1191 1267 STAM_PROFILE_STOP(&pCtl->StatLockWait, a); 1192 1268 } … … 1196 1272 * 1197 1273 * @returns nothing. 1274 * @param pDevIns The device instance. 1198 1275 * @param pCtl The controller to unlock. 1199 1276 */ 1200 DECLINLINE(void) ataR3LockLeave(P ATACONTROLLER pCtl)1201 { 1202 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);1277 DECLINLINE(void) ataR3LockLeave(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 1278 { 1279 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 1203 1280 } 1204 1281 … … 1265 1342 #endif /* unused */ 1266 1343 1267 static void ataR3CmdOK( ATADevState *s, uint8_t status)1344 static void ataR3CmdOK(PATACONTROLLER pCtl, ATADevState *s, uint8_t status) 1268 1345 { 1269 1346 s->uATARegError = 0; /* Not needed by ATA spec, but cannot hurt. */ 1270 ataSetStatusValue( s, ATA_STAT_READY | status);1271 } 1272 1273 1274 static void ataR3CmdError( ATADevState *s, uint8_t uErrorCode)1347 ataSetStatusValue(pCtl, s, ATA_STAT_READY | status); 1348 } 1349 1350 1351 static void ataR3CmdError(PATACONTROLLER pCtl, ATADevState *s, uint8_t uErrorCode) 1275 1352 { 1276 1353 Log(("%s: code=%#x\n", __FUNCTION__, uErrorCode)); 1277 1354 Assert(uErrorCode); 1278 1355 s->uATARegError = uErrorCode; 1279 ataSetStatusValue( s, ATA_STAT_READY | ATA_STAT_ERR);1356 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_ERR); 1280 1357 s->cbTotalTransfer = 0; 1281 1358 s->cbElementaryTransfer = 0; … … 1300 1377 } 1301 1378 1302 static bool ataR3IdentifySS(ATADevState *s) 1379 /** 1380 * Sink/Source: IDENTIFY 1381 */ 1382 static bool ataR3IdentifySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1303 1383 { 1304 1384 uint16_t *p; 1385 RT_NOREF(pDevIns); 1305 1386 1306 1387 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 1358 1439 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */ 1359 1440 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */ 1360 if ( s->pDrvMedia->pfnDiscard1441 if ( pDevR3->pDrvMedia->pfnDiscard 1361 1442 || s->cbSector != 512 1362 || s->pDrvMedia->pfnIsNonRotational(s->pDrvMedia))1443 || pDevR3->pDrvMedia->pfnIsNonRotational(pDevR3->pDrvMedia)) 1363 1444 { 1364 1445 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */ … … 1401 1482 } 1402 1483 1403 if ( s->pDrvMedia->pfnDiscard) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */1484 if (pDevR3->pDrvMedia->pfnDiscard) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */ 1404 1485 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */ 1405 if ( s->pDrvMedia->pfnIsNonRotational(s->pDrvMedia))1486 if (pDevR3->pDrvMedia->pfnIsNonRotational(pDevR3->pDrvMedia)) 1406 1487 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */ 1407 1488 uint32_t uCsum = ataR3Checksum(p, 510); 1408 1489 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */ 1409 1490 s->iSourceSink = ATAFN_SS_NULL; 1410 ataR3CmdOK( s, ATA_STAT_SEEK);1491 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 1411 1492 return false; 1412 1493 } 1413 1494 1414 1495 1415 static bool ataR3FlushSS(ATADevState *s) 1416 { 1417 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1496 /** 1497 * Sink/Source: FLUSH 1498 */ 1499 static bool ataR3FlushSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1500 { 1418 1501 int rc; 1419 1502 … … 1421 1504 Assert(!s->cbElementaryTransfer); 1422 1505 1423 ataR3LockLeave(p Ctl);1506 ataR3LockLeave(pDevIns, pCtl); 1424 1507 1425 1508 STAM_PROFILE_START(&s->StatFlushes, f); 1426 rc = s->pDrvMedia->pfnFlush(s->pDrvMedia);1509 rc = pDevR3->pDrvMedia->pfnFlush(pDevR3->pDrvMedia); 1427 1510 AssertRC(rc); 1428 1511 STAM_PROFILE_STOP(&s->StatFlushes, f); 1429 1512 1430 ataR3LockEnter(p Ctl);1431 ataR3CmdOK( s, 0);1513 ataR3LockEnter(pDevIns, pCtl); 1514 ataR3CmdOK(pCtl, s, 0); 1432 1515 return false; 1433 1516 } 1434 1517 1435 static bool atapiR3IdentifySS(ATADevState *s) 1518 /** 1519 * Sink/Source: ATAPI IDENTIFY 1520 */ 1521 static bool atapiR3IdentifySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1436 1522 { 1437 1523 uint16_t *p; 1524 RT_NOREF(pDevIns, pDevR3); 1438 1525 1439 1526 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 1490 1577 1491 1578 s->iSourceSink = ATAFN_SS_NULL; 1492 ataR3CmdOK( s, ATA_STAT_SEEK);1579 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 1493 1580 return false; 1494 1581 } … … 1523 1610 { 1524 1611 /* LBA48 */ 1525 iLBA = ((uint64_t)s->uATARegHCylHOB << 40) |1526 ((uint64_t)s->uATARegLCylHOB << 32) |1527 ((uint64_t)s->uATARegSectorHOB << 24) |1528 ((uint64_t)s->uATARegHCyl << 16) |1529 ((uint64_t)s->uATARegLCyl << 8) |1530 s->uATARegSector;1612 iLBA = ((uint64_t)s->uATARegHCylHOB << 40) 1613 | ((uint64_t)s->uATARegLCylHOB << 32) 1614 | ((uint64_t)s->uATARegSectorHOB << 24) 1615 | ((uint64_t)s->uATARegHCyl << 16) 1616 | ((uint64_t)s->uATARegLCyl << 8) 1617 | s->uATARegSector; 1531 1618 } 1532 1619 else 1533 1620 { 1534 1621 /* LBA */ 1535 iLBA = ((s->uATARegSelect & 0x0f) << 24) | (s->uATARegHCyl << 16) | 1536 (s->uATARegLCyl << 8) | s->uATARegSector; 1622 iLBA = ((uint32_t)(s->uATARegSelect & 0x0f) << 24) 1623 | ((uint32_t)s->uATARegHCyl << 16) 1624 | ((uint32_t)s->uATARegLCyl << 8) 1625 | s->uATARegSector; 1537 1626 } 1538 1627 } … … 1540 1629 { 1541 1630 /* CHS */ 1542 iLBA = (( s->uATARegHCyl << 8) | s->uATARegLCyl) * s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors +1543 (s->uATARegSelect & 0x0f) * s->PCHSGeometry.cSectors +1544 (s->uATARegSector - 1);1545 LogFlowFunc(("CHS %u/%u/%u -> LBA %llu\n", ( s->uATARegHCyl << 8) | s->uATARegLCyl, s->uATARegSelect & 0x0f, s->uATARegSector, iLBA));1631 iLBA = (((uint32_t)s->uATARegHCyl << 8) | s->uATARegLCyl) * s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors 1632 + (s->uATARegSelect & 0x0f) * s->PCHSGeometry.cSectors 1633 + (s->uATARegSector - 1); 1634 LogFlowFunc(("CHS %u/%u/%u -> LBA %llu\n", ((uint32_t)s->uATARegHCyl << 8) | s->uATARegLCyl, s->uATARegSelect & 0x0f, s->uATARegSector, iLBA)); 1546 1635 } 1547 1636 return iLBA; … … 1614 1703 } 1615 1704 1616 static bool ataR3IsRedoSetWarning(ATADevState *s, int rc) 1617 { 1618 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1619 Assert(!PDMDevHlpCritSectIsOwner(pCtl->CTX_SUFF(pDevIns), &pCtl->lock)); 1705 static bool ataR3IsRedoSetWarning(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, int rc) 1706 { 1707 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, &pCtl->lock)); 1620 1708 if (rc == VERR_DISK_FULL) 1621 1709 { 1622 1710 pCtl->fRedoIdle = true; 1623 ataR3WarningDiskFull( ATADEVSTATE_2_DEVINS(s));1711 ataR3WarningDiskFull(pDevIns); 1624 1712 return true; 1625 1713 } … … 1627 1715 { 1628 1716 pCtl->fRedoIdle = true; 1629 ataR3WarningFileTooBig( ATADEVSTATE_2_DEVINS(s));1717 ataR3WarningFileTooBig(pDevIns); 1630 1718 return true; 1631 1719 } … … 1635 1723 /* iSCSI connection abort (first error) or failure to reestablish 1636 1724 * connection (second error). Pause VM. On resume we'll retry. */ 1637 ataR3WarningISCSI( ATADEVSTATE_2_DEVINS(s));1725 ataR3WarningISCSI(pDevIns); 1638 1726 return true; 1639 1727 } … … 1649 1737 1650 1738 1651 static int ataR3ReadSectors(ATADevState *s, uint64_t u64Sector, void *pvBuf, 1652 uint32_t cSectors, bool *pfRedo) 1653 { 1654 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1739 static int ataR3ReadSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s, PATADEVSTATER3 pDevR3, 1740 uint64_t u64Sector, void *pvBuf, uint32_t cSectors, bool *pfRedo) 1741 { 1655 1742 int rc; 1656 1743 uint32_t const cbSector = s->cbSector; … … 1659 1746 AssertReturnStmt(cbToRead <= sizeof(s->abIOBuffer), *pfRedo = false, VERR_BUFFER_OVERFLOW); 1660 1747 1661 ataR3LockLeave(p Ctl);1748 ataR3LockLeave(pDevIns, pCtl); 1662 1749 1663 1750 STAM_PROFILE_ADV_START(&s->StatReads, r); 1664 1751 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1; 1665 rc = s->pDrvMedia->pfnRead(s->pDrvMedia, u64Sector * cbSector, pvBuf, cbToRead);1752 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, u64Sector * cbSector, pvBuf, cbToRead); 1666 1753 s->Led.Actual.s.fReading = 0; 1667 1754 STAM_PROFILE_ADV_STOP(&s->StatReads, r); … … 1674 1761 *pfRedo = false; 1675 1762 else 1676 *pfRedo = ataR3IsRedoSetWarning( s, rc);1677 1678 ataR3LockEnter(p Ctl);1763 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc); 1764 1765 ataR3LockEnter(pDevIns, pCtl); 1679 1766 return rc; 1680 1767 } 1681 1768 1682 1769 1683 static int ataR3WriteSectors(ATADevState *s, uint64_t u64Sector, 1684 const void *pvBuf, uint32_t cSectors, bool *pfRedo) 1685 { 1686 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1770 static int ataR3WriteSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s, PATADEVSTATER3 pDevR3, 1771 uint64_t u64Sector, const void *pvBuf, uint32_t cSectors, bool *pfRedo) 1772 { 1687 1773 int rc; 1688 1774 uint32_t const cbSector = s->cbSector; … … 1691 1777 AssertReturnStmt(cbToWrite <= sizeof(s->abIOBuffer), *pfRedo = false, VERR_BUFFER_OVERFLOW); 1692 1778 1693 ataR3LockLeave(p Ctl);1779 ataR3LockLeave(pDevIns, pCtl); 1694 1780 1695 1781 STAM_PROFILE_ADV_START(&s->StatWrites, w); … … 1699 1785 STAM_PROFILE_ADV_START(&s->StatInstrVDWrites, vw); 1700 1786 # endif 1701 rc = s->pDrvMedia->pfnWrite(s->pDrvMedia, u64Sector * cbSector, pvBuf, cbToWrite);1787 rc = pDevR3->pDrvMedia->pfnWrite(pDevR3->pDrvMedia, u64Sector * cbSector, pvBuf, cbToWrite); 1702 1788 # ifdef VBOX_INSTRUMENT_DMA_WRITES 1703 1789 if (s->fDMA) … … 1714 1800 *pfRedo = false; 1715 1801 else 1716 *pfRedo = ataR3IsRedoSetWarning( s, rc);1717 1718 ataR3LockEnter(p Ctl);1802 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc); 1803 1804 ataR3LockEnter(pDevIns, pCtl); 1719 1805 return rc; 1720 1806 } 1721 1807 1722 1808 1723 static void ataR3ReadWriteSectorsBT(ATADevState *s) 1809 /** 1810 * Begin Transfer: READ/WRITE SECTORS 1811 */ 1812 static void ataR3ReadWriteSectorsBT(PATACONTROLLER pCtl, ATADevState *s) 1724 1813 { 1725 1814 uint32_t const cbSector = RT_MAX(s->cbSector, 1); … … 1732 1821 s->cbElementaryTransfer = cSectors * cbSector; 1733 1822 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE) 1734 ataR3CmdOK(s, 0); 1735 } 1736 1737 1738 static bool ataR3ReadSectorsSS(ATADevState *s) 1823 ataR3CmdOK(pCtl, s, 0); 1824 } 1825 1826 1827 /** 1828 * Sink/Source: READ SECTORS 1829 */ 1830 static bool ataR3ReadSectorsSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1739 1831 { 1740 1832 uint32_t const cbSector = RT_MAX(s->cbSector, 1); … … 1748 1840 iLBA = ataR3GetSector(s); 1749 1841 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA)); 1750 rc = ataR3ReadSectors( s, iLBA, s->abIOBuffer, cSectors, &fRedo);1842 rc = ataR3ReadSectors(pDevIns, pCtl, s, pDevR3, iLBA, s->abIOBuffer, cSectors, &fRedo); 1751 1843 if (RT_SUCCESS(rc)) 1752 1844 { … … 1754 1846 if (s->cbElementaryTransfer == s->cbTotalTransfer) 1755 1847 s->iSourceSink = ATAFN_SS_NULL; 1756 ataR3CmdOK( s, ATA_STAT_SEEK);1848 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 1757 1849 } 1758 1850 else … … 1769 1861 */ 1770 1862 if (rc != VERR_INTERRUPTED) 1771 ataR3CmdError( s, ID_ERR);1863 ataR3CmdError(pCtl, s, ID_ERR); 1772 1864 } 1773 1865 return false; … … 1775 1867 1776 1868 1777 static bool ataR3WriteSectorsSS(ATADevState *s) 1869 /** 1870 * Sink/Source: WRITE SECTOR 1871 */ 1872 static bool ataR3WriteSectorsSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1778 1873 { 1779 1874 uint32_t const cbSector = RT_MAX(s->cbSector, 1); … … 1787 1882 iLBA = ataR3GetSector(s); 1788 1883 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA)); 1789 rc = ataR3WriteSectors( s, iLBA, s->abIOBuffer, cSectors, &fRedo);1884 rc = ataR3WriteSectors(pDevIns, pCtl, s, pDevR3, iLBA, s->abIOBuffer, cSectors, &fRedo); 1790 1885 if (RT_SUCCESS(rc)) 1791 1886 { … … 1793 1888 if (!s->cbTotalTransfer) 1794 1889 s->iSourceSink = ATAFN_SS_NULL; 1795 ataR3CmdOK( s, ATA_STAT_SEEK);1890 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 1796 1891 } 1797 1892 else … … 1808 1903 */ 1809 1904 if (rc != VERR_INTERRUPTED) 1810 ataR3CmdError( s, ID_ERR);1905 ataR3CmdError(pCtl, s, ID_ERR); 1811 1906 } 1812 1907 return false; … … 1814 1909 1815 1910 1816 static void atapiR3CmdOK( ATADevState *s)1911 static void atapiR3CmdOK(PATACONTROLLER pCtl, ATADevState *s) 1817 1912 { 1818 1913 s->uATARegError = 0; 1819 ataSetStatusValue( s, ATA_STAT_READY);1914 ataSetStatusValue(pCtl, s, ATA_STAT_READY); 1820 1915 s->uATARegNSector = (s->uATARegNSector & ~7) 1821 1916 | ((s->uTxDir != PDMMEDIATXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0) … … 1829 1924 1830 1925 1831 static void atapiR3CmdError( ATADevState *s, const uint8_t *pabATAPISense, size_t cbATAPISense)1926 static void atapiR3CmdError(PATACONTROLLER pCtl, ATADevState *s, const uint8_t *pabATAPISense, size_t cbATAPISense) 1832 1927 { 1833 1928 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f), 1834 1929 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13]))); 1835 1930 s->uATARegError = pabATAPISense[2] << 4; 1836 ataSetStatusValue( s, ATA_STAT_READY | ATA_STAT_ERR);1931 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_ERR); 1837 1932 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD; 1838 1933 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector)); … … 1852 1947 /** @todo deprecated function - doesn't provide enough info. Replace by direct 1853 1948 * calls to atapiR3CmdError() with full data. */ 1854 static void atapiR3CmdErrorSimple( ATADevState *s, uint8_t uATAPISenseKey, uint8_t uATAPIASC)1949 static void atapiR3CmdErrorSimple(PATACONTROLLER pCtl, ATADevState *s, uint8_t uATAPISenseKey, uint8_t uATAPIASC) 1855 1950 { 1856 1951 uint8_t abATAPISense[ATAPI_SENSE_SIZE]; … … 1860 1955 abATAPISense[7] = 10; 1861 1956 abATAPISense[12] = uATAPIASC; 1862 atapiR3CmdError(s, abATAPISense, sizeof(abATAPISense)); 1863 } 1864 1865 1866 static void atapiR3CmdBT(ATADevState *s) 1957 atapiR3CmdError(pCtl, s, abATAPISense, sizeof(abATAPISense)); 1958 } 1959 1960 1961 /** 1962 * Begin Transfer: ATAPI command 1963 */ 1964 static void atapiR3CmdBT(PATACONTROLLER pCtl, ATADevState *s) 1867 1965 { 1868 1966 s->fATAPITransfer = true; … … 1871 1969 s->cbPIOTransferLimit = s->uATARegLCyl | (s->uATARegHCyl << 8); 1872 1970 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE) 1873 atapiR3CmdOK(s); 1874 } 1875 1876 1877 static void atapiR3PassthroughCmdBT(ATADevState *s) 1878 { 1879 atapiR3CmdBT(s); 1880 } 1881 1882 static bool atapiR3ReadSS(ATADevState *s) 1883 { 1884 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 1971 atapiR3CmdOK(pCtl, s); 1972 } 1973 1974 1975 /** 1976 * Begin Transfer: ATAPI Passthrough command 1977 */ 1978 static void atapiR3PassthroughCmdBT(PATACONTROLLER pCtl, ATADevState *s) 1979 { 1980 atapiR3CmdBT(pCtl, s); 1981 } 1982 1983 1984 /** 1985 * Sink/Source: READ 1986 */ 1987 static bool atapiR3ReadSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 1988 { 1885 1989 int rc; 1886 1990 uint64_t cbBlockRegion = 0; … … 1895 1999 AssertLogRelReturn(cSectors * cbATAPISector <= sizeof(s->abIOBuffer), false); 1896 2000 1897 ataR3LockLeave(p Ctl);1898 1899 rc = s->pDrvMedia->pfnQueryRegionPropertiesForLba(s->pDrvMedia, iATAPILBA, NULL, NULL,2001 ataR3LockLeave(pDevIns, pCtl); 2002 2003 rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA, NULL, NULL, 1900 2004 &cbBlockRegion, NULL); 1901 2005 if (RT_SUCCESS(rc)) … … 1906 2010 /* If the region block size and requested sector matches we can just pass the request through. */ 1907 2011 if (cbBlockRegion == cbATAPISector) 1908 rc = s->pDrvMedia->pfnRead(s->pDrvMedia, (uint64_t)iATAPILBA * cbATAPISector,2012 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)iATAPILBA * cbATAPISector, 1909 2013 s->abIOBuffer, cbATAPISector * cSectors); 1910 2014 else … … 1929 2033 *pbBuf++ = 0x01; /* mode 1 data */ 1930 2034 /* data */ 1931 rc = s->pDrvMedia->pfnRead(s->pDrvMedia, (uint64_t)i * 2048, pbBuf, 2048);2035 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)i * 2048, pbBuf, 2048); 1932 2036 if (RT_FAILURE(rc)) 1933 2037 break; … … 1951 2055 { 1952 2056 uint8_t abTmp[2352]; 1953 rc = s->pDrvMedia->pfnRead(s->pDrvMedia, (uint64_t)i * 2352, &abTmp[0], 2352);2057 rc = pDevR3->pDrvMedia->pfnRead(pDevR3->pDrvMedia, (uint64_t)i * 2352, &abTmp[0], 2352); 1954 2058 if (RT_FAILURE(rc)) 1955 2059 break; … … 1966 2070 } 1967 2071 1968 ataR3LockEnter(p Ctl);2072 ataR3LockEnter(pDevIns, pCtl); 1969 2073 1970 2074 if (RT_SUCCESS(rc)) … … 1978 2082 if (cbTransfer >= s->cbTotalTransfer) 1979 2083 s->iSourceSink = ATAFN_SS_NULL; 1980 atapiR3CmdOK( s);2084 atapiR3CmdOK(pCtl, s); 1981 2085 s->iATAPILBA = iATAPILBA + cSectors; 1982 2086 } … … 1991 2095 */ 1992 2096 if (rc != VERR_INTERRUPTED) 1993 atapiR3CmdErrorSimple( s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR);2097 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR); 1994 2098 } 1995 2099 return false; … … 2004 2108 } 2005 2109 2006 static bool atapiR3PassthroughSS(ATADevState *s) 2007 { 2008 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 2110 2111 /** 2112 * Sink/Source: Passthrough 2113 */ 2114 static bool atapiR3PassthroughSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2115 { 2009 2116 int rc = VINF_SUCCESS; 2010 2117 uint8_t abATAPISense[ATAPI_SENSE_SIZE]; … … 2033 2140 } 2034 2141 2035 ataR3LockLeave(p Ctl);2142 ataR3LockLeave(pDevIns, pCtl); 2036 2143 2037 2144 # if defined(LOG_ENABLED) … … 2109 2216 if (s->cErrors++ < MAX_LOG_REL_ERRORS) 2110 2217 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN)); 2111 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);2112 ataR3LockEnter(p Ctl);2218 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE); 2219 ataR3LockEnter(pDevIns, pCtl); 2113 2220 return false; 2114 2221 } … … 2146 2253 } 2147 2254 AssertLogRelReturn((uintptr_t)(pbBuf - &s->abIOBuffer[0]) + cbCurrTX <= sizeof(s->abIOBuffer), false); 2148 rc = s->pDrvMedia->pfnSendCmd(s->pDrvMedia, abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir,2255 rc = pDevR3->pDrvMedia->pfnSendCmd(pDevR3->pDrvMedia, abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir, 2149 2256 pbBuf, &cbCurrTX, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */); 2150 2257 if (rc != VINF_SUCCESS) … … 2182 2289 if (s->cErrors++ < MAX_LOG_REL_ERRORS) 2183 2290 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN)); 2184 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);2291 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE); 2185 2292 return false; 2186 2293 } … … 2190 2297 { 2191 2298 AssertLogRelReturn(cbTransfer <= sizeof(s->abIOBuffer), false); 2192 rc = s->pDrvMedia->pfnSendCmd(s->pDrvMedia, s->abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir,2299 rc = pDevR3->pDrvMedia->pfnSendCmd(pDevR3->pDrvMedia, s->abATAPICmd, ATAPI_PACKET_SIZE, (PDMMEDIATXDIR)s->uTxDir, 2193 2300 s->abIOBuffer, &cbTransfer, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */); 2194 2301 } 2195 2302 if (pProf) { STAM_PROFILE_ADV_STOP(pProf, b); } 2196 2303 2197 ataR3LockEnter(p Ctl);2304 ataR3LockEnter(pDevIns, pCtl); 2198 2305 2199 2306 /* Update the LEDs and the read/write statistics. */ … … 2220 2327 case SCSI_READ_TOC_PMA_ATIP: 2221 2328 { 2222 if (! s->pTrackList)2223 rc = ATAPIPassthroughTrackListCreateEmpty(& s->pTrackList);2329 if (!pDevR3->pTrackList) 2330 rc = ATAPIPassthroughTrackListCreateEmpty(&pDevR3->pTrackList); 2224 2331 2225 2332 if (RT_SUCCESS(rc)) 2226 rc = ATAPIPassthroughTrackListUpdate( s->pTrackList, s->abATAPICmd, s->abIOBuffer, sizeof(s->abIOBuffer));2333 rc = ATAPIPassthroughTrackListUpdate(pDevR3->pTrackList, s->abATAPICmd, s->abIOBuffer, sizeof(s->abIOBuffer)); 2227 2334 2228 2335 if ( RT_FAILURE(rc) … … 2234 2341 case SCSI_SYNCHRONIZE_CACHE: 2235 2342 { 2236 if ( s->pTrackList)2237 ATAPIPassthroughTrackListClear( s->pTrackList);2343 if (pDevR3->pTrackList) 2344 ATAPIPassthroughTrackListClear(pDevR3->pTrackList); 2238 2345 break; 2239 2346 } … … 2274 2381 { 2275 2382 s->iSourceSink = ATAFN_SS_NULL; 2276 atapiR3CmdOK( s);2383 atapiR3CmdOK(pCtl, s); 2277 2384 } 2278 2385 } … … 2296 2403 } while (0); 2297 2404 } 2298 atapiR3CmdError( s, abATAPISense, sizeof(abATAPISense));2405 atapiR3CmdError(pCtl, s, abATAPISense, sizeof(abATAPISense)); 2299 2406 } 2300 2407 return false; 2301 2408 } 2302 2409 2303 static bool atapiR3ReadDVDStructureSS(ATADevState *s) 2410 2411 /** 2412 * Begin Transfer: Read DVD structures 2413 */ 2414 static bool atapiR3ReadDVDStructureSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2304 2415 { 2305 2416 uint8_t *buf = s->abIOBuffer; 2306 2417 int media = s->abATAPICmd[1]; 2307 2418 int format = s->abATAPICmd[7]; 2419 RT_NOREF(pDevIns, pDevR3); 2308 2420 2309 2421 AssertCompile(sizeof(s->abIOBuffer) > UINT16_MAX /* want a RT_MIN() below, but clang takes offence at always false stuff */); … … 2432 2544 { 2433 2545 s->iSourceSink = ATAFN_SS_NULL; 2434 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);2546 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, -uASC); 2435 2547 return false; 2436 2548 } … … 2449 2561 default: 2450 2562 s->iSourceSink = ATAFN_SS_NULL; 2451 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);2563 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 2452 2564 return false; 2453 2565 } 2454 2566 2455 2567 s->iSourceSink = ATAFN_SS_NULL; 2456 atapiR3CmdOK( s);2568 atapiR3CmdOK(pCtl, s); 2457 2569 return false; 2458 2570 } 2459 2571 2460 static bool atapiR3ReadSectors(ATADevState *s, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector) 2572 2573 static bool atapiR3ReadSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s, 2574 uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector) 2461 2575 { 2462 2576 Assert(cSectors > 0); 2463 2577 s->iATAPILBA = iATAPILBA; 2464 2578 s->cbATAPISector = cbSector; 2465 ataR3StartTransfer(s, cSectors * cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true); 2579 ataR3StartTransfer(pDevIns, pCtl, s, cSectors * cbSector, 2580 PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true); 2466 2581 return false; 2467 2582 } 2468 2583 2469 2584 2470 static bool atapiR3ReadCapacitySS(ATADevState *s) 2585 /** 2586 * Sink/Source: ATAPI READ CAPACITY 2587 */ 2588 static bool atapiR3ReadCapacitySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2471 2589 { 2472 2590 uint8_t *pbBuf = s->abIOBuffer; 2591 RT_NOREF(pDevIns, pDevR3); 2473 2592 2474 2593 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2477 2596 scsiH2BE_U32(pbBuf + 4, 2048); 2478 2597 s->iSourceSink = ATAFN_SS_NULL; 2479 atapiR3CmdOK( s);2598 atapiR3CmdOK(pCtl, s); 2480 2599 return false; 2481 2600 } 2482 2601 2483 2602 2484 static bool atapiR3ReadDiscInformationSS(ATADevState *s) 2603 /** 2604 * Sink/Source: ATAPI READ DISCK INFORMATION 2605 */ 2606 static bool atapiR3ReadDiscInformationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2485 2607 { 2486 2608 uint8_t *pbBuf = s->abIOBuffer; 2609 RT_NOREF(pDevIns, pDevR3); 2487 2610 2488 2611 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2494 2617 pbBuf[4] = 1; /* number of sessions (LSB) */ 2495 2618 pbBuf[5] = 1; /* first track number in last session (LSB) */ 2496 pbBuf[6] = (uint8_t) s->pDrvMedia->pfnGetRegionCount(s->pDrvMedia); /* last track number in last session (LSB) */2619 pbBuf[6] = (uint8_t)pDevR3->pDrvMedia->pfnGetRegionCount(pDevR3->pDrvMedia); /* last track number in last session (LSB) */ 2497 2620 pbBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */ 2498 2621 pbBuf[8] = 0; /* disc type = CD-ROM */ … … 2503 2626 scsiH2BE_U32(pbBuf + 20, 0xffffffff); /* last possible start time for lead-out is not available */ 2504 2627 s->iSourceSink = ATAFN_SS_NULL; 2505 atapiR3CmdOK( s);2628 atapiR3CmdOK(pCtl, s); 2506 2629 return false; 2507 2630 } 2508 2631 2509 2632 2510 static bool atapiR3ReadTrackInformationSS(ATADevState *s) 2633 /** 2634 * Sink/Source: ATAPI READ TRACK INFORMATION 2635 */ 2636 static bool atapiR3ReadTrackInformationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2511 2637 { 2512 2638 uint8_t *pbBuf = s->abIOBuffer; 2513 2639 uint32_t u32LogAddr = scsiBE2H_U32(&s->abATAPICmd[2]); 2514 2640 uint8_t u8LogAddrType = s->abATAPICmd[1] & 0x03; 2641 RT_NOREF(pDevIns); 2515 2642 2516 2643 int rc; … … 2529 2656 { 2530 2657 case 0x00: 2531 rc = s->pDrvMedia->pfnQueryRegionPropertiesForLba(s->pDrvMedia, u32LogAddr, &uRegion,2532 NULL, NULL, NULL);2658 rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, u32LogAddr, &uRegion, 2659 NULL, NULL, NULL); 2533 2660 if (RT_SUCCESS(rc)) 2534 rc = s->pDrvMedia->pfnQueryRegionProperties(s->pDrvMedia, uRegion, &u64LbaStart,2535 &cBlocks, &cbBlock, &enmDataForm);2661 rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, uRegion, &u64LbaStart, 2662 &cBlocks, &cbBlock, &enmDataForm); 2536 2663 break; 2537 2664 case 0x01: … … 2540 2667 { 2541 2668 uRegion = u32LogAddr - 1; 2542 rc = s->pDrvMedia->pfnQueryRegionProperties(s->pDrvMedia, uRegion, &u64LbaStart,2543 &cBlocks, &cbBlock, &enmDataForm);2669 rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, uRegion, &u64LbaStart, 2670 &cBlocks, &cbBlock, &enmDataForm); 2544 2671 } 2545 2672 else … … 2549 2676 case 0x02: 2550 2677 default: 2551 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);2678 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 2552 2679 return false; 2553 2680 } … … 2555 2682 if (RT_FAILURE(rc)) 2556 2683 { 2557 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);2684 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 2558 2685 return false; 2559 2686 } … … 2595 2722 pbBuf[33] = 0; /* session number (MSB) */ 2596 2723 s->iSourceSink = ATAFN_SS_NULL; 2597 atapiR3CmdOK( s);2724 atapiR3CmdOK(pCtl, s); 2598 2725 return false; 2599 2726 } … … 2601 2728 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureListProfiles(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2602 2729 { 2603 RT_NOREF 1(s);2730 RT_NOREF(s); 2604 2731 if (cbBuf < 3*4) 2605 2732 return 0; … … 2620 2747 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureCore(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2621 2748 { 2622 RT_NOREF 1(s);2749 RT_NOREF(s); 2623 2750 if (cbBuf < 12) 2624 2751 return 0; … … 2636 2763 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureMorphing(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2637 2764 { 2638 RT_NOREF 1(s);2765 RT_NOREF(s); 2639 2766 if (cbBuf < 8) 2640 2767 return 0; … … 2651 2778 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureRemovableMedium(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2652 2779 { 2653 RT_NOREF 1(s);2780 RT_NOREF(s); 2654 2781 if (cbBuf < 8) 2655 2782 return 0; … … 2667 2794 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureRandomReadable (ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2668 2795 { 2669 RT_NOREF 1(s);2796 RT_NOREF(s); 2670 2797 if (cbBuf < 12) 2671 2798 return 0; … … 2684 2811 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureCDRead(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2685 2812 { 2686 RT_NOREF 1(s);2813 RT_NOREF(s); 2687 2814 if (cbBuf < 8) 2688 2815 return 0; … … 2699 2826 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeaturePowerManagement(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2700 2827 { 2701 RT_NOREF 1(s);2828 RT_NOREF(s); 2702 2829 if (cbBuf < 4) 2703 2830 return 0; … … 2712 2839 static DECLCALLBACK(uint32_t) atapiR3GetConfigurationFillFeatureTimeout(ATADevState *s, uint8_t *pbBuf, size_t cbBuf) 2713 2840 { 2714 RT_NOREF 1(s);2841 RT_NOREF(s); 2715 2842 if (cbBuf < 8) 2716 2843 return 0; … … 2762 2889 }; 2763 2890 2764 static bool atapiR3GetConfigurationSS(ATADevState *s) 2891 /** 2892 * Sink/Source: ATAPI GET CONFIGURATION 2893 */ 2894 static bool atapiR3GetConfigurationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2765 2895 { 2766 2896 uint32_t const cbIOBuffer = RT_MIN(s->cbIOBuffer, ATA_MAX_IO_BUFFER_SIZE); … … 2770 2900 uint16_t u16Sfn = scsiBE2H_U16(&s->abATAPICmd[2]); 2771 2901 uint8_t u8Rt = s->abATAPICmd[1] & 0x03; 2902 RT_NOREF(pDevIns, pDevR3); 2772 2903 2773 2904 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2776 2907 if (u8Rt == 3) 2777 2908 { 2778 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);2909 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 2779 2910 return false; 2780 2911 } … … 2820 2951 /* Other profiles we might want to add in the future: 0x40 (BD-ROM) and 0x50 (HDDVD-ROM) */ 2821 2952 s->iSourceSink = ATAFN_SS_NULL; 2822 atapiR3CmdOK( s);2953 atapiR3CmdOK(pCtl, s); 2823 2954 return false; 2824 2955 } 2825 2956 2826 2957 2827 static bool atapiR3GetEventStatusNotificationSS(ATADevState *s) 2958 /** 2959 * Sink/Source: ATAPI GET EVENT STATUS NOTIFICATION 2960 */ 2961 static bool atapiR3GetEventStatusNotificationSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2828 2962 { 2829 2963 uint8_t *pbBuf = s->abIOBuffer; 2964 RT_NOREF(pDevIns, pDevR3); 2830 2965 2831 2966 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2835 2970 { 2836 2971 /* no asynchronous operation supported */ 2837 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);2972 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 2838 2973 return false; 2839 2974 } … … 2895 3030 2896 3031 s->iSourceSink = ATAFN_SS_NULL; 2897 atapiR3CmdOK( s);3032 atapiR3CmdOK(pCtl, s); 2898 3033 return false; 2899 3034 } 2900 3035 2901 3036 2902 static bool atapiR3InquirySS(ATADevState *s) 3037 /** 3038 * Sink/Source: ATAPI INQUIRY 3039 */ 3040 static bool atapiR3InquirySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2903 3041 { 2904 3042 uint8_t *pbBuf = s->abIOBuffer; 3043 RT_NOREF(pDevIns, pDevR3); 2905 3044 2906 3045 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2923 3062 scsiPadStr(pbBuf + 32, s->szInquiryRevision, 4); 2924 3063 s->iSourceSink = ATAFN_SS_NULL; 2925 atapiR3CmdOK( s);3064 atapiR3CmdOK(pCtl, s); 2926 3065 return false; 2927 3066 } 2928 3067 2929 3068 2930 static bool atapiR3ModeSenseErrorRecoverySS(ATADevState *s) 3069 /** 3070 * Sink/Source: ATAPI MODE SENSE ERROR RECOVERY 3071 */ 3072 static bool atapiR3ModeSenseErrorRecoverySS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2931 3073 { 2932 3074 uint8_t *pbBuf = s->abIOBuffer; 3075 RT_NOREF(pDevIns, pDevR3); 2933 3076 2934 3077 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2951 3094 pbBuf[15] = 0x00; 2952 3095 s->iSourceSink = ATAFN_SS_NULL; 2953 atapiR3CmdOK( s);3096 atapiR3CmdOK(pCtl, s); 2954 3097 return false; 2955 3098 } 2956 3099 2957 3100 2958 static bool atapiR3ModeSenseCDStatusSS(ATADevState *s) 3101 /** 3102 * Sink/Source: ATAPI MODE SENSE CD STATUS 3103 */ 3104 static bool atapiR3ModeSenseCDStatusSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 2959 3105 { 2960 3106 uint8_t *pbBuf = s->abIOBuffer; 3107 RT_NOREF(pDevIns); 2961 3108 2962 3109 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 2980 3127 pbBuf[13] = 0x00; /* no subchannel reads supported */ 2981 3128 pbBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */ 2982 if ( s->pDrvMount->pfnIsLocked(s->pDrvMount))3129 if (pDevR3->pDrvMount->pfnIsLocked(pDevR3->pDrvMount)) 2983 3130 pbBuf[14] |= 1 << 1; /* report lock state */ 2984 3131 pbBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */ … … 2999 3146 scsiH2BE_U16(&pbBuf[38], 0); /* number of write speed performance descriptors */ 3000 3147 s->iSourceSink = ATAFN_SS_NULL; 3001 atapiR3CmdOK( s);3148 atapiR3CmdOK(pCtl, s); 3002 3149 return false; 3003 3150 } 3004 3151 3005 3152 3006 static bool atapiR3RequestSenseSS(ATADevState *s) 3153 /** 3154 * Sink/Source: ATAPI REQUEST SENSE 3155 */ 3156 static bool atapiR3RequestSenseSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3007 3157 { 3008 3158 uint8_t *pbBuf = s->abIOBuffer; 3159 RT_NOREF(pDevIns, pDevR3); 3009 3160 3010 3161 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 3013 3164 memcpy(pbBuf, s->abATAPISense, RT_MIN(s->cbElementaryTransfer, sizeof(s->abATAPISense))); 3014 3165 s->iSourceSink = ATAFN_SS_NULL; 3015 atapiR3CmdOK( s);3166 atapiR3CmdOK(pCtl, s); 3016 3167 return false; 3017 3168 } 3018 3169 3019 3170 3020 static bool atapiR3MechanismStatusSS(ATADevState *s) 3171 /** 3172 * Sink/Source: ATAPI MECHANISM STATUS 3173 */ 3174 static bool atapiR3MechanismStatusSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3021 3175 { 3022 3176 uint8_t *pbBuf = s->abIOBuffer; 3177 RT_NOREF(pDevIns, pDevR3); 3023 3178 3024 3179 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 3032 3187 scsiH2BE_U16(pbBuf + 6, 0); 3033 3188 s->iSourceSink = ATAFN_SS_NULL; 3034 atapiR3CmdOK( s);3189 atapiR3CmdOK(pCtl, s); 3035 3190 return false; 3036 3191 } 3037 3192 3038 3193 3039 static bool atapiR3ReadTOCNormalSS(ATADevState *s) 3194 /** 3195 * Sink/Source: ATAPI READ TOC NORMAL 3196 */ 3197 static bool atapiR3ReadTOCNormalSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3040 3198 { 3041 3199 uint8_t *pbBuf = s->abIOBuffer; … … 3044 3202 bool fMSF; 3045 3203 uint32_t cbSize; 3204 RT_NOREF(pDevIns); 3046 3205 3047 3206 /* Track fields are 8-bit and 1-based, so cut the track count at 255, 3048 3207 avoiding any potentially buffer overflow issues below. */ 3049 uint32_t cTracks = s->pDrvMedia->pfnGetRegionCount(s->pDrvMedia);3208 uint32_t cTracks = pDevR3->pDrvMedia->pfnGetRegionCount(pDevR3->pDrvMedia); 3050 3209 AssertStmt(cTracks <= UINT8_MAX, cTracks = UINT8_MAX); 3051 3210 AssertCompile(sizeof(s->abIOBuffer) >= 2 + 256 + 8); … … 3059 3218 if (iStartTrack > cTracks && iStartTrack != 0xaa) 3060 3219 { 3061 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);3220 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 3062 3221 return false; 3063 3222 } … … 3070 3229 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_MODE1_2048; 3071 3230 3072 int rc = s->pDrvMedia->pfnQueryRegionProperties(s->pDrvMedia, iTrack - 1, &uLbaStart,3073 NULL, NULL, &enmDataForm);3231 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, iTrack - 1, &uLbaStart, 3232 NULL, NULL, &enmDataForm); 3074 3233 AssertRC(rc); 3075 3234 … … 3106 3265 uint64_t cBlocks = 0; 3107 3266 3108 int rc = s->pDrvMedia->pfnQueryRegionProperties(s->pDrvMedia, cTracks - 1, &uLbaStart,3267 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, cTracks - 1, &uLbaStart, 3109 3268 &cBlocks, NULL, NULL); 3110 3269 AssertRC(rc); … … 3127 3286 s->cbTotalTransfer = cbSize; 3128 3287 s->iSourceSink = ATAFN_SS_NULL; 3129 atapiR3CmdOK( s);3288 atapiR3CmdOK(pCtl, s); 3130 3289 return false; 3131 3290 } 3132 3291 3133 3292 3134 static bool atapiR3ReadTOCMultiSS(ATADevState *s) 3293 /** 3294 * Sink/Source: ATAPI READ TOC MULTI 3295 */ 3296 static bool atapiR3ReadTOCMultiSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3135 3297 { 3136 3298 uint8_t *pbBuf = s->abIOBuffer; 3137 3299 bool fMSF; 3300 RT_NOREF(pDevIns); 3138 3301 3139 3302 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 3150 3313 3151 3314 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_MODE1_2048; 3152 int rc = s->pDrvMedia->pfnQueryRegionProperties(s->pDrvMedia, 0, NULL, 3153 NULL, NULL, &enmDataForm); 3315 int rc = pDevR3->pDrvMedia->pfnQueryRegionProperties(pDevR3->pDrvMedia, 0, NULL, NULL, NULL, &enmDataForm); 3154 3316 AssertRC(rc); 3155 3317 … … 3171 3333 } 3172 3334 s->iSourceSink = ATAFN_SS_NULL; 3173 atapiR3CmdOK( s);3335 atapiR3CmdOK(pCtl, s); 3174 3336 return false; 3175 3337 } 3176 3338 3177 3339 3178 static bool atapiR3ReadTOCRawSS(ATADevState *s) 3340 /** 3341 * Sink/Source: ATAPI READ TOC RAW 3342 */ 3343 static bool atapiR3ReadTOCRawSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3179 3344 { 3180 3345 uint8_t *pbBuf = s->abIOBuffer; … … 3183 3348 bool fMSF; 3184 3349 uint32_t cbSize; 3350 RT_NOREF(pDevIns, pDevR3); 3185 3351 3186 3352 Assert(s->uTxDir == PDMMEDIATXDIR_FROM_DEVICE); … … 3260 3426 s->cbTotalTransfer = cbSize; 3261 3427 s->iSourceSink = ATAFN_SS_NULL; 3262 atapiR3CmdOK( s);3428 atapiR3CmdOK(pCtl, s); 3263 3429 return false; 3264 3430 } 3265 3431 3266 3432 3267 static void atapiR3ParseCmdVirtualATAPI( ATADevState *s)3433 static void atapiR3ParseCmdVirtualATAPI(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3268 3434 { 3269 3435 const uint8_t *pbPacket = s->abATAPICmd; … … 3277 3443 { 3278 3444 if (s->cNotifiedMediaChange-- > 2) 3279 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3445 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3280 3446 else 3281 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3447 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3282 3448 } 3283 else if ( s->pDrvMount->pfnIsMounted(s->pDrvMount))3284 atapiR3CmdOK( s);3449 else if (pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3450 atapiR3CmdOK(pCtl, s); 3285 3451 else 3286 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3452 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3287 3453 break; 3288 3454 case SCSI_GET_EVENT_STATUS_NOTIFICATION: 3289 3455 cbMax = scsiBE2H_U16(pbPacket + 7); 3290 ataR3StartTransfer( s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);3456 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true); 3291 3457 break; 3292 3458 case SCSI_MODE_SENSE_6: … … 3302 3468 { 3303 3469 case SCSI_MODEPAGE_ERROR_RECOVERY: 3304 ataR3StartTransfer( s, RT_MIN(cbMax, 16), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);3470 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 16), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true); 3305 3471 break; 3306 3472 case SCSI_MODEPAGE_CD_STATUS: 3307 ataR3StartTransfer( s, RT_MIN(cbMax, 40), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);3473 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 40), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true); 3308 3474 break; 3309 3475 default: … … 3317 3483 default: 3318 3484 case SCSI_PAGECONTROL_SAVED: 3319 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);3485 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED); 3320 3486 break; 3321 3487 } … … 3334 3500 { 3335 3501 case SCSI_MODEPAGE_ERROR_RECOVERY: 3336 ataR3StartTransfer( s, RT_MIN(cbMax, 16), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);3502 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 16), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true); 3337 3503 break; 3338 3504 case SCSI_MODEPAGE_CD_STATUS: 3339 ataR3StartTransfer( s, RT_MIN(cbMax, 40), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);3505 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 40), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true); 3340 3506 break; 3341 3507 default: … … 3349 3515 default: 3350 3516 case SCSI_PAGECONTROL_SAVED: 3351 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);3517 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED); 3352 3518 break; 3353 3519 } … … 3356 3522 case SCSI_REQUEST_SENSE: 3357 3523 cbMax = pbPacket[4]; 3358 ataR3StartTransfer( s, RT_MIN(cbMax, 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);3524 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true); 3359 3525 break; 3360 3526 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL: 3361 if ( s->pDrvMount->pfnIsMounted(s->pDrvMount))3527 if (pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3362 3528 { 3363 3529 if (pbPacket[4] & 1) 3364 s->pDrvMount->pfnLock(s->pDrvMount);3530 pDevR3->pDrvMount->pfnLock(pDevR3->pDrvMount); 3365 3531 else 3366 s->pDrvMount->pfnUnlock(s->pDrvMount);3367 atapiR3CmdOK( s);3532 pDevR3->pDrvMount->pfnUnlock(pDevR3->pDrvMount); 3533 atapiR3CmdOK(pCtl, s); 3368 3534 } 3369 3535 else 3370 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3536 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3371 3537 break; 3372 3538 case SCSI_READ_10: … … 3376 3542 { 3377 3543 s->cNotifiedMediaChange-- ; 3378 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3544 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3379 3545 break; 3380 3546 } 3381 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3547 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3382 3548 { 3383 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3549 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3384 3550 break; 3385 3551 } … … 3392 3558 if (cSectors == 0) 3393 3559 { 3394 atapiR3CmdOK( s);3560 atapiR3CmdOK(pCtl, s); 3395 3561 break; 3396 3562 } … … 3398 3564 /* Check that the sector size is valid. */ 3399 3565 VDREGIONDATAFORM enmDataForm = VDREGIONDATAFORM_INVALID; 3400 int rc = s->pDrvMedia->pfnQueryRegionPropertiesForLba(s->pDrvMedia, iATAPILBA,3566 int rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA, 3401 3567 NULL, NULL, NULL, &enmDataForm); 3402 3568 if (RT_UNLIKELY( rc == VERR_NOT_FOUND … … 3413 3579 uLastLogTS = RTTimeMilliTS(); 3414 3580 } 3415 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);3581 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR); 3416 3582 break; 3417 3583 } … … 3430 3596 abATAPISense[7] = 10; 3431 3597 abATAPISense[12] = SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK; 3432 atapiR3CmdError( s, &abATAPISense[0], sizeof(abATAPISense));3598 atapiR3CmdError(pCtl, s, &abATAPISense[0], sizeof(abATAPISense)); 3433 3599 break; 3434 3600 } 3435 atapiR3ReadSectors( s, iATAPILBA, cSectors, 2048);3601 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2048); 3436 3602 break; 3437 3603 } … … 3442 3608 { 3443 3609 s->cNotifiedMediaChange-- ; 3444 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3610 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3445 3611 break; 3446 3612 } 3447 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3613 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3448 3614 { 3449 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3615 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3450 3616 break; 3451 3617 } 3452 3618 if ((pbPacket[10] & 0x7) != 0) 3453 3619 { 3454 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);3620 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 3455 3621 break; 3456 3622 } … … 3467 3633 Log2(("Start MSF %02u:%02u:%02u > end MSF %02u:%02u:%02u!\n", *(pbPacket + 3), *(pbPacket + 4), *(pbPacket + 5), 3468 3634 *(pbPacket + 6), *(pbPacket + 7), *(pbPacket + 8))); 3469 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);3635 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 3470 3636 break; 3471 3637 } … … 3476 3642 if (cSectors == 0) 3477 3643 { 3478 atapiR3CmdOK( s);3644 atapiR3CmdOK(pCtl, s); 3479 3645 break; 3480 3646 } … … 3491 3657 uLastLogTS = RTTimeMilliTS(); 3492 3658 } 3493 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);3659 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR); 3494 3660 break; 3495 3661 } … … 3503 3669 uint8_t uChnSel = pbPacket[9] & 0xf8; 3504 3670 VDREGIONDATAFORM enmDataForm; 3505 int rc = s->pDrvMedia->pfnQueryRegionPropertiesForLba(s->pDrvMedia, iATAPILBA,3506 NULL, NULL, NULL, &enmDataForm);3671 int rc = pDevR3->pDrvMedia->pfnQueryRegionPropertiesForLba(pDevR3->pDrvMedia, iATAPILBA, 3672 NULL, NULL, NULL, &enmDataForm); 3507 3673 AssertRC(rc); 3508 3674 … … 3512 3678 { 3513 3679 /* nothing */ 3514 atapiR3CmdOK( s);3680 atapiR3CmdOK(pCtl, s); 3515 3681 } 3516 3682 else 3517 atapiR3ReadSectors( s, iATAPILBA, cSectors, 2352);3683 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2352); 3518 3684 } 3519 3685 else … … 3523 3689 case 0x00: 3524 3690 /* nothing */ 3525 atapiR3CmdOK( s);3691 atapiR3CmdOK(pCtl, s); 3526 3692 break; 3527 3693 case 0x10: 3528 3694 /* normal read */ 3529 atapiR3ReadSectors( s, iATAPILBA, cSectors, 2048);3695 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2048); 3530 3696 break; 3531 3697 case 0xf8: 3532 3698 /* read all data */ 3533 atapiR3ReadSectors( s, iATAPILBA, cSectors, 2352);3699 atapiR3ReadSectors(pDevIns, pCtl, s, iATAPILBA, cSectors, 2352); 3534 3700 break; 3535 3701 default: 3536 3702 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM sector format not supported (%#x)\n", s->iLUN, pbPacket[9] & 0xf8)); 3537 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);3703 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 3538 3704 break; 3539 3705 } … … 3546 3712 { 3547 3713 s->cNotifiedMediaChange-- ; 3548 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3714 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3549 3715 break; 3550 3716 } 3551 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3717 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3552 3718 { 3553 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3719 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3554 3720 break; 3555 3721 } … … 3567 3733 uLastLogTS = RTTimeMilliTS(); 3568 3734 } 3569 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);3735 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR); 3570 3736 break; 3571 3737 } 3572 atapiR3CmdOK( s);3573 ataSetStatus( s, ATA_STAT_SEEK); /* Linux expects this. */3738 atapiR3CmdOK(pCtl, s); 3739 ataSetStatus(pCtl, s, ATA_STAT_SEEK); /* Linux expects this. */ 3574 3740 break; 3575 3741 } … … 3585 3751 { 3586 3752 /* This must be done from EMT. */ 3587 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 3588 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s); 3589 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 3590 3591 ataR3LockLeave(pCtl); 3753 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 3754 3755 ataR3LockLeave(pDevIns, pCtl); 3592 3756 rc = VMR3ReqPriorityCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY, 3593 (PFNRT) s->pDrvMount->pfnUnmount, 3,3594 s->pDrvMount, false /*=fForce*/, true /*=fEject*/);3757 (PFNRT)pDevR3->pDrvMount->pfnUnmount, 3, 3758 pDevR3->pDrvMount, false /*=fForce*/, true /*=fEject*/); 3595 3759 Assert(RT_SUCCESS(rc) || rc == VERR_PDM_MEDIA_LOCKED || rc == VERR_PDM_MEDIA_NOT_MOUNTED); 3596 if (RT_SUCCESS(rc) && pThis ->pMediaNotify)3760 if (RT_SUCCESS(rc) && pThisCC->pMediaNotify) 3597 3761 { 3598 3762 rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY, 3599 (PFNRT)pThis ->pMediaNotify->pfnEjected, 2,3600 pThis ->pMediaNotify, s->iLUN);3763 (PFNRT)pThisCC->pMediaNotify->pfnEjected, 2, 3764 pThisCC->pMediaNotify, s->iLUN); 3601 3765 AssertRC(rc); 3602 3766 } 3603 3767 3604 ataR3LockEnter(p Ctl);3768 ataR3LockEnter(pDevIns, pCtl); 3605 3769 break; 3606 3770 } 3607 3771 case 3: /* 11 - Load media */ 3608 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */3772 /** @todo rc = pDevR3->pDrvMount->pfnLoadMedia(pDevR3->pDrvMount) */ 3609 3773 break; 3610 3774 } 3611 3775 if (RT_SUCCESS(rc)) 3612 atapiR3CmdOK( s);3776 atapiR3CmdOK(pCtl, s); 3613 3777 else 3614 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);3778 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED); 3615 3779 break; 3616 3780 } … … 3618 3782 { 3619 3783 cbMax = scsiBE2H_U16(pbPacket + 8); 3620 ataR3StartTransfer( s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true);3784 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true); 3621 3785 break; 3622 3786 } … … 3628 3792 { 3629 3793 s->cNotifiedMediaChange-- ; 3630 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3794 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3631 3795 break; 3632 3796 } 3633 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3797 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3634 3798 { 3635 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3799 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3636 3800 break; 3637 3801 } … … 3644 3808 { 3645 3809 case 0: 3646 ataR3StartTransfer( s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true);3810 ataR3StartTransfer(pDevIns, pCtl, s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true); 3647 3811 break; 3648 3812 case 1: 3649 ataR3StartTransfer( s, RT_MIN(cbMax, 12), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true);3813 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 12), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true); 3650 3814 break; 3651 3815 case 2: 3652 ataR3StartTransfer( s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true);3816 ataR3StartTransfer(pDevIns, pCtl, s, cbMax, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true); 3653 3817 break; 3654 3818 default: 3655 3819 error_cmd: 3656 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);3820 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET); 3657 3821 break; 3658 3822 } … … 3663 3827 { 3664 3828 s->cNotifiedMediaChange-- ; 3665 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3829 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3666 3830 break; 3667 3831 } 3668 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3832 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3669 3833 { 3670 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3834 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3671 3835 break; 3672 3836 } 3673 ataR3StartTransfer( s, 8, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true);3837 ataR3StartTransfer(pDevIns, pCtl, s, 8, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true); 3674 3838 break; 3675 3839 case SCSI_READ_DISC_INFORMATION: … … 3677 3841 { 3678 3842 s->cNotifiedMediaChange-- ; 3679 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3843 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3680 3844 break; 3681 3845 } 3682 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3846 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3683 3847 { 3684 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3848 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3685 3849 break; 3686 3850 } 3687 3851 cbMax = scsiBE2H_U16(pbPacket + 7); 3688 ataR3StartTransfer( s, RT_MIN(cbMax, 34), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true);3852 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 34), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true); 3689 3853 break; 3690 3854 case SCSI_READ_TRACK_INFORMATION: … … 3692 3856 { 3693 3857 s->cNotifiedMediaChange-- ; 3694 atapiR3CmdErrorSimple( s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */3858 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */ 3695 3859 break; 3696 3860 } 3697 else if (! s->pDrvMount->pfnIsMounted(s->pDrvMount))3861 else if (!pDevR3->pDrvMount->pfnIsMounted(pDevR3->pDrvMount)) 3698 3862 { 3699 atapiR3CmdErrorSimple( s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);3863 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT); 3700 3864 break; 3701 3865 } 3702 3866 cbMax = scsiBE2H_U16(pbPacket + 7); 3703 ataR3StartTransfer( s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true);3867 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true); 3704 3868 break; 3705 3869 case SCSI_GET_CONFIGURATION: 3706 3870 /* No media change stuff here, it can confuse Linux guests. */ 3707 3871 cbMax = scsiBE2H_U16(pbPacket + 7); 3708 ataR3StartTransfer( s, RT_MIN(cbMax, 80), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true);3872 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 80), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true); 3709 3873 break; 3710 3874 case SCSI_INQUIRY: 3711 3875 cbMax = scsiBE2H_U16(pbPacket + 3); 3712 ataR3StartTransfer( s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true);3876 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 36), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true); 3713 3877 break; 3714 3878 case SCSI_READ_DVD_STRUCTURE: 3715 3879 { 3716 3880 cbMax = scsiBE2H_U16(pbPacket + 8); 3717 ataR3StartTransfer( s, RT_MIN(cbMax, 4), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE, true);3881 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbMax, 4), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE, true); 3718 3882 break; 3719 3883 } 3720 3884 default: 3721 atapiR3CmdErrorSimple( s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);3885 atapiR3CmdErrorSimple(pCtl, s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE); 3722 3886 break; 3723 3887 } … … 3728 3892 * Parse ATAPI commands, passing them directly to the CD/DVD drive. 3729 3893 */ 3730 static void atapiR3ParseCmdPassthrough( ATADevState *s)3894 static void atapiR3ParseCmdPassthrough(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3731 3895 { 3732 3896 const uint8_t *pbPacket = &s->abATAPICmd[0]; … … 3737 3901 { 3738 3902 uint32_t cbTransfer = scsiBE2H_U16(pbPacket + 7); 3739 ataR3StartTransfer( s, RT_MIN(cbTransfer, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);3903 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(cbTransfer, 8), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true); 3740 3904 } 3741 3905 else if ( pbPacket[0] == SCSI_REQUEST_SENSE 3742 3906 && (s->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE) 3743 ataR3StartTransfer( s, RT_MIN(pbPacket[4], 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);3907 ataR3StartTransfer(pDevIns, pCtl, s, RT_MIN(pbPacket[4], 18), PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true); 3744 3908 else 3745 3909 { … … 3753 3917 cbBuf = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */ 3754 3918 3755 bool fPassthrough = ATAPIPassthroughParseCdb(pbPacket, sizeof(s->abATAPICmd), cbBuf, s->pTrackList,3919 bool fPassthrough = ATAPIPassthroughParseCdb(pbPacket, sizeof(s->abATAPICmd), cbBuf, pDevR3->pTrackList, 3756 3920 &s->abATAPISense[0], sizeof(s->abATAPISense), &uTxDir, &cbTransfer, 3757 3921 &cbATAPISector, &u8ScsiSts); … … 3770 3934 if (cbTransfer == 0) 3771 3935 uTxDir = PDMMEDIATXDIR_NONE; 3772 ataR3StartTransfer( s, (uint32_t)cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true);3936 ataR3StartTransfer(pDevIns, pCtl, s, (uint32_t)cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true); 3773 3937 } 3774 3938 else if (u8ScsiSts == SCSI_STATUS_CHECK_CONDITION) … … 3778 3942 s->abATAPISense[12], s->abATAPISense[13], SCSISenseExtText(s->abATAPISense[12], s->abATAPISense[13]))); 3779 3943 s->uATARegError = s->abATAPISense[2] << 4; 3780 ataSetStatusValue( s, ATA_STAT_READY | ATA_STAT_ERR);3944 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_ERR); 3781 3945 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD; 3782 3946 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector)); … … 3791 3955 } 3792 3956 else if (u8ScsiSts == SCSI_STATUS_OK) 3793 atapiR3CmdOK( s);3794 } 3795 } 3796 3797 3798 static void atapiR3ParseCmd( ATADevState *s)3957 atapiR3CmdOK(pCtl, s); 3958 } 3959 } 3960 3961 3962 static void atapiR3ParseCmd(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3799 3963 { 3800 3964 const uint8_t *pbPacket; … … 3809 3973 3810 3974 if (s->fATAPIPassthrough) 3811 atapiR3ParseCmdPassthrough( s);3975 atapiR3ParseCmdPassthrough(pDevIns, pCtl, s, pDevR3); 3812 3976 else 3813 atapiR3ParseCmdVirtualATAPI(s); 3814 } 3815 3816 3817 static bool ataR3PacketSS(ATADevState *s) 3977 atapiR3ParseCmdVirtualATAPI(pDevIns, pCtl, s, pDevR3); 3978 } 3979 3980 3981 /** 3982 * Sink/Source: PACKET 3983 */ 3984 static bool ataR3PacketSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 3818 3985 { 3819 3986 s->fDMA = !!(s->uATARegFeature & 1); … … 3823 3990 s->cbElementaryTransfer = 0; 3824 3991 s->cbAtapiPassthroughTransfer = 0; 3825 atapiR3ParseCmd( s);3992 atapiR3ParseCmd(pDevIns, pCtl, s, pDevR3); 3826 3993 return false; 3827 3994 } … … 3869 4036 static DECLCALLBACK(void) ataR3MountNotify(PPDMIMOUNTNOTIFY pInterface) 3870 4037 { 3871 ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IMountNotify); 3872 Log(("%s: changing LUN#%d\n", __FUNCTION__, pIf->iLUN)); 4038 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IMountNotify); 4039 PATASTATE pThis = PDMDEVINS_2_DATA(pIfR3->pDevIns, PATASTATE); 4040 PATADEVSTATE pIf = &pThis->aCts[pIfR3->iCtl % RT_ELEMENTS(pThis->aCts)].aIfs[pIfR3->iDev % RT_ELEMENTS(pThis->aCts[0].aIfs)]; 4041 Log(("%s: changing LUN#%d\n", __FUNCTION__, pIfR3->iLUN)); 3873 4042 3874 4043 /* Ignore the call if we're called while being attached. */ 3875 if (!pIf ->pDrvMedia)4044 if (!pIfR3->pDrvMedia) 3876 4045 return; 3877 4046 3878 uint32_t cRegions = pIf ->pDrvMedia->pfnGetRegionCount(pIf->pDrvMedia);4047 uint32_t cRegions = pIfR3->pDrvMedia->pfnGetRegionCount(pIfR3->pDrvMedia); 3879 4048 for (uint32_t i = 0; i < cRegions; i++) 3880 4049 { 3881 4050 uint64_t cBlocks = 0; 3882 int rc = pIf ->pDrvMedia->pfnQueryRegionProperties(pIf->pDrvMedia, i, NULL, &cBlocks,4051 int rc = pIfR3->pDrvMedia->pfnQueryRegionProperties(pIfR3->pDrvMedia, i, NULL, &cBlocks, 3883 4052 NULL, NULL); 3884 4053 AssertRC(rc); … … 3900 4069 static DECLCALLBACK(void) ataR3UnmountNotify(PPDMIMOUNTNOTIFY pInterface) 3901 4070 { 3902 ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IMountNotify); 4071 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IMountNotify); 4072 PATASTATE pThis = PDMDEVINS_2_DATA(pIfR3->pDevIns, PATASTATE); 4073 PATADEVSTATE pIf = &pThis->aCts[pIfR3->iCtl % RT_ELEMENTS(pThis->aCts)].aIfs[pIfR3->iDev % RT_ELEMENTS(pThis->aCts[0].aIfs)]; 3903 4074 Log(("%s:\n", __FUNCTION__)); 3904 4075 pIf->cTotalSectors = 0; … … 3915 4086 } 3916 4087 3917 static void ataR3PacketBT(ATADevState *s) 4088 /** 4089 * Begin Transfer: PACKET 4090 */ 4091 static void ataR3PacketBT(PATACONTROLLER pCtl, ATADevState *s) 3918 4092 { 3919 4093 s->cbElementaryTransfer = s->cbTotalTransfer; … … 3921 4095 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_CD; 3922 4096 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector)); 3923 ataSetStatusValue( s, ATA_STAT_READY);3924 } 3925 3926 3927 static void ataR3ResetDevice( ATADevState *s)4097 ataSetStatusValue(pCtl, s, ATA_STAT_READY); 4098 } 4099 4100 4101 static void ataR3ResetDevice(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s) 3928 4102 { 3929 4103 s->cMultSectors = ATA_MAX_MULT_SECTORS; … … 3931 4105 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED); 3932 4106 ASMAtomicWriteU32(&s->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN); 3933 ataUnsetIRQ( s);4107 ataUnsetIRQ(pDevIns, pCtl, s); 3934 4108 3935 4109 s->uATARegSelect = 0x20; 3936 ataSetStatusValue( s, ATA_STAT_READY);4110 ataSetStatusValue(pCtl, s, ATA_STAT_READY); 3937 4111 ataR3SetSignature(s); 3938 4112 s->cbTotalTransfer = 0; … … 3951 4125 3952 4126 3953 static void ataR3DeviceDiag( ATADevState *s)4127 static void ataR3DeviceDiag(PATACONTROLLER pCtl, ATADevState *s) 3954 4128 { 3955 4129 ataR3SetSignature(s); 3956 4130 if (s->fATAPI) 3957 ataSetStatusValue( s, 0); /* NOTE: READY is _not_ set */4131 ataSetStatusValue(pCtl, s, 0); /* NOTE: READY is _not_ set */ 3958 4132 else 3959 ataSetStatusValue( s, ATA_STAT_READY | ATA_STAT_SEEK);4133 ataSetStatusValue(pCtl, s, ATA_STAT_READY | ATA_STAT_SEEK); 3960 4134 s->uATARegError = 0x01; 3961 4135 } 3962 4136 3963 4137 3964 static bool ataR3ExecuteDeviceDiagnosticSS(ATADevState *s) 3965 { 3966 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 4138 /** 4139 * Sink/Source: EXECUTE DEVICE DIAGNOTIC 4140 */ 4141 static bool ataR3ExecuteDeviceDiagnosticSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 4142 { 4143 RT_NOREF(pDevIns, s, pDevR3); 3967 4144 3968 4145 /* EXECUTE DEVICE DIAGNOSTIC is a very special command which always … … 3971 4148 */ 3972 4149 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++) 3973 ataR3DeviceDiag(&pCtl->aIfs[i]); 3974 3975 LogRel(("ATA: LUN#%d: EXECUTE DEVICE DIAGNOSTIC, status %02X\n", 3976 s->iLUN, s->uATARegStatus)); 4150 ataR3DeviceDiag(pCtl, &pCtl->aIfs[i]); 4151 4152 LogRel(("ATA: LUN#%d: EXECUTE DEVICE DIAGNOSTIC, status %02X\n", s->iLUN, s->uATARegStatus)); 3977 4153 pCtl->iSelectedIf = 0; 3978 4154 … … 3981 4157 3982 4158 3983 static bool ataR3InitDevParmSS(ATADevState *s) 3984 { 3985 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 3986 4159 /** 4160 * Sink/Source: INITIALIZE DEVICE PARAMETERS 4161 */ 4162 static bool ataR3InitDevParmSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 4163 { 4164 RT_NOREF(pDevR3); 3987 4165 LogFlowFunc(("\n")); 3988 4166 LogRel(("ATA: LUN#%d: INITIALIZE DEVICE PARAMETERS: %u logical sectors, %u heads\n", 3989 4167 s->iLUN, s->uATARegNSector, s->uATARegSelect & 0x0f)); 3990 ataR3LockLeave(p Ctl);4168 ataR3LockLeave(pDevIns, pCtl); 3991 4169 RTThreadSleep(pCtl->msDelayIRQ); 3992 ataR3LockEnter(p Ctl);3993 ataR3CmdOK( s, ATA_STAT_SEEK);3994 ataHCSetIRQ( s);4170 ataR3LockEnter(pDevIns, pCtl); 4171 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4172 ataHCSetIRQ(pDevIns, pCtl, s); 3995 4173 return false; 3996 4174 } 3997 4175 3998 4176 3999 static bool ataR3RecalibrateSS(ATADevState *s) 4000 { 4001 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s); 4002 4177 /** 4178 * Sink/Source: RECALIBRATE 4179 */ 4180 static bool ataR3RecalibrateSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 4181 { 4182 RT_NOREF(pDevR3); 4003 4183 LogFlowFunc(("\n")); 4004 ataR3LockLeave(p Ctl);4184 ataR3LockLeave(pDevIns, pCtl); 4005 4185 RTThreadSleep(pCtl->msDelayIRQ); 4006 ataR3LockEnter(p Ctl);4007 ataR3CmdOK( s, ATA_STAT_SEEK);4008 ataHCSetIRQ( s);4186 ataR3LockEnter(pDevIns, pCtl); 4187 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4188 ataHCSetIRQ(pDevIns, pCtl, s); 4009 4189 return false; 4010 4190 } 4011 4191 4012 4192 4013 static int ataR3TrimSectors( ATADevState *s, uint64_t u64Sector, uint32_t cSectors,4014 bool *pfRedo)4193 static int ataR3TrimSectors(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3, 4194 uint64_t u64Sector, uint32_t cSectors, bool *pfRedo) 4015 4195 { 4016 4196 RTRANGE TrimRange; 4017 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);4018 4197 int rc; 4019 4198 4020 ataR3LockLeave(p Ctl);4199 ataR3LockLeave(pDevIns, pCtl); 4021 4200 4022 4201 TrimRange.offStart = u64Sector * s->cbSector; … … 4024 4203 4025 4204 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1; 4026 rc = s->pDrvMedia->pfnDiscard(s->pDrvMedia, &TrimRange, 1);4205 rc = pDevR3->pDrvMedia->pfnDiscard(pDevR3->pDrvMedia, &TrimRange, 1); 4027 4206 s->Led.Actual.s.fWriting = 0; 4028 4207 … … 4030 4209 *pfRedo = false; 4031 4210 else 4032 *pfRedo = ataR3IsRedoSetWarning( s, rc);4033 4034 ataR3LockEnter(p Ctl);4211 *pfRedo = ataR3IsRedoSetWarning(pDevIns, pCtl, rc); 4212 4213 ataR3LockEnter(pDevIns, pCtl); 4035 4214 return rc; 4036 4215 } 4037 4216 4038 4217 4039 static bool ataR3TrimSS(ATADevState *s) 4218 /** 4219 * Sink/Source: TRIM 4220 */ 4221 static bool ataR3TrimSS(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3) 4040 4222 { 4041 4223 int rc = VERR_GENERAL_FAILURE; … … 4052 4234 break; 4053 4235 4054 rc = ataR3TrimSectors( s, *pu64Range & ATA_RANGE_LBA_MASK,4236 rc = ataR3TrimSectors(pDevIns, pCtl, s, pDevR3, *pu64Range & ATA_RANGE_LBA_MASK, 4055 4237 ATA_RANGE_LENGTH_GET(*pu64Range), &fRedo); 4056 4238 if (RT_FAILURE(rc)) … … 4063 4245 { 4064 4246 s->iSourceSink = ATAFN_SS_NULL; 4065 ataR3CmdOK( s, ATA_STAT_SEEK);4247 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4066 4248 } 4067 4249 else … … 4078 4260 */ 4079 4261 if (rc != VERR_INTERRUPTED) 4080 ataR3CmdError( s, ID_ERR);4262 ataR3CmdError(pCtl, s, ID_ERR); 4081 4263 } 4082 4264 … … 4085 4267 4086 4268 4087 static void ataR3ParseCmd( ATADevState *s, uint8_t cmd)4269 static void ataR3ParseCmd(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATADEVSTATE s, PATADEVSTATER3 pDevR3, uint8_t cmd) 4088 4270 { 4089 4271 # ifdef DEBUG … … 4109 4291 { 4110 4292 case ATA_IDENTIFY_DEVICE: 4111 if ( s->pDrvMedia && !s->fATAPI)4112 ataR3StartTransfer( s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false);4293 if (pDevR3->pDrvMedia && !s->fATAPI) 4294 ataR3StartTransfer(pDevIns, pCtl, s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false); 4113 4295 else 4114 4296 { 4115 4297 if (s->fATAPI) 4116 4298 ataR3SetSignature(s); 4117 ataR3CmdError( s, ABRT_ERR);4118 ataUnsetStatus( s, ATA_STAT_READY);4119 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4299 ataR3CmdError(pCtl, s, ABRT_ERR); 4300 ataUnsetStatus(pCtl, s, ATA_STAT_READY); 4301 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4120 4302 } 4121 4303 break; … … 4123 4305 if (s->fATAPI) 4124 4306 goto abort_cmd; 4125 ataR3StartTransfer( s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_RECALIBRATE, false);4307 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_RECALIBRATE, false); 4126 4308 break; 4127 4309 case ATA_INITIALIZE_DEVICE_PARAMETERS: 4128 4310 if (s->fATAPI) 4129 4311 goto abort_cmd; 4130 ataR3StartTransfer( s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_INITIALIZE_DEVICE_PARAMETERS, false);4312 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_INITIALIZE_DEVICE_PARAMETERS, false); 4131 4313 break; 4132 4314 case ATA_SET_MULTIPLE_MODE: … … 4135 4317 || (s->uATARegNSector & (s->uATARegNSector - 1)) != 0)) 4136 4318 { 4137 ataR3CmdError( s, ABRT_ERR);4319 ataR3CmdError(pCtl, s, ABRT_ERR); 4138 4320 } 4139 4321 else … … 4141 4323 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, s->uATARegNSector)); 4142 4324 s->cMultSectors = s->uATARegNSector; 4143 ataR3CmdOK( s, 0);4325 ataR3CmdOK(pCtl, s, 0); 4144 4326 } 4145 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4327 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4146 4328 break; 4147 4329 case ATA_READ_VERIFY_SECTORS_EXT: … … 4151 4333 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES: 4152 4334 /* do sector number check ? */ 4153 ataR3CmdOK( s, ATA_STAT_SEEK);4154 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4335 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4336 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4155 4337 break; 4156 4338 case ATA_READ_SECTORS_EXT: … … 4159 4341 case ATA_READ_SECTORS: 4160 4342 case ATA_READ_SECTORS_WITHOUT_RETRIES: 4161 if (! s->pDrvMedia || s->fATAPI)4343 if (!pDevR3->pDrvMedia || s->fATAPI) 4162 4344 goto abort_cmd; 4163 4345 s->cSectorsPerIRQ = 1; 4164 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);4346 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false); 4165 4347 break; 4166 4348 case ATA_WRITE_SECTORS_EXT: … … 4169 4351 case ATA_WRITE_SECTORS: 4170 4352 case ATA_WRITE_SECTORS_WITHOUT_RETRIES: 4171 if (! s->pDrvMedia || s->fATAPI)4353 if (!pDevR3->pDrvMedia || s->fATAPI) 4172 4354 goto abort_cmd; 4173 4355 s->cSectorsPerIRQ = 1; 4174 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);4356 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false); 4175 4357 break; 4176 4358 case ATA_READ_MULTIPLE_EXT: … … 4178 4360 RT_FALL_THRU(); 4179 4361 case ATA_READ_MULTIPLE: 4180 if (! s->pDrvMedia || !s->cMultSectors || s->fATAPI)4362 if (!pDevR3->pDrvMedia || !s->cMultSectors || s->fATAPI) 4181 4363 goto abort_cmd; 4182 4364 s->cSectorsPerIRQ = s->cMultSectors; 4183 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);4365 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false); 4184 4366 break; 4185 4367 case ATA_WRITE_MULTIPLE_EXT: … … 4187 4369 RT_FALL_THRU(); 4188 4370 case ATA_WRITE_MULTIPLE: 4189 if (! s->pDrvMedia || !s->cMultSectors || s->fATAPI)4371 if (!pDevR3->pDrvMedia || !s->cMultSectors || s->fATAPI) 4190 4372 goto abort_cmd; 4191 4373 s->cSectorsPerIRQ = s->cMultSectors; 4192 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);4374 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false); 4193 4375 break; 4194 4376 case ATA_READ_DMA_EXT: … … 4197 4379 case ATA_READ_DMA: 4198 4380 case ATA_READ_DMA_WITHOUT_RETRIES: 4199 if (! s->pDrvMedia || s->fATAPI)4381 if (!pDevR3->pDrvMedia || s->fATAPI) 4200 4382 goto abort_cmd; 4201 4383 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS; 4202 4384 s->fDMA = true; 4203 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);4385 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false); 4204 4386 break; 4205 4387 case ATA_WRITE_DMA_EXT: … … 4208 4390 case ATA_WRITE_DMA: 4209 4391 case ATA_WRITE_DMA_WITHOUT_RETRIES: 4210 if (! s->pDrvMedia || s->fATAPI)4392 if (!pDevR3->pDrvMedia || s->fATAPI) 4211 4393 goto abort_cmd; 4212 4394 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS; 4213 4395 s->fDMA = true; 4214 ataR3StartTransfer( s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);4396 ataR3StartTransfer(pDevIns, pCtl, s, ataR3GetNSectors(s) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false); 4215 4397 break; 4216 4398 case ATA_READ_NATIVE_MAX_ADDRESS_EXT: 4217 4399 s->fLBA48 = true; 4218 4400 ataR3SetSector(s, s->cTotalSectors - 1); 4219 ataR3CmdOK( s, 0);4220 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4401 ataR3CmdOK(pCtl, s, 0); 4402 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4221 4403 break; 4222 4404 case ATA_SEEK: /* Used by the SCO OpenServer. Command is marked as obsolete */ 4223 ataR3CmdOK( s, 0);4224 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4405 ataR3CmdOK(pCtl, s, 0); 4406 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4225 4407 break; 4226 4408 case ATA_READ_NATIVE_MAX_ADDRESS: 4227 4409 ataR3SetSector(s, RT_MIN(s->cTotalSectors, 1 << 28) - 1); 4228 ataR3CmdOK( s, 0);4229 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4410 ataR3CmdOK(pCtl, s, 0); 4411 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4230 4412 break; 4231 4413 case ATA_CHECK_POWER_MODE: 4232 4414 s->uATARegNSector = 0xff; /* drive active or idle */ 4233 ataR3CmdOK( s, 0);4234 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4415 ataR3CmdOK(pCtl, s, 0); 4416 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4235 4417 break; 4236 4418 case ATA_SET_FEATURES: 4237 4419 Log2(("%s: feature=%#x\n", __FUNCTION__, s->uATARegFeature)); 4238 if (! s->pDrvMedia)4420 if (!pDevR3->pDrvMedia) 4239 4421 goto abort_cmd; 4240 4422 switch (s->uATARegFeature) … … 4242 4424 case 0x02: /* write cache enable */ 4243 4425 Log2(("%s: write cache enable\n", __FUNCTION__)); 4244 ataR3CmdOK( s, ATA_STAT_SEEK);4245 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4426 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4427 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4246 4428 break; 4247 4429 case 0xaa: /* read look-ahead enable */ 4248 4430 Log2(("%s: read look-ahead enable\n", __FUNCTION__)); 4249 ataR3CmdOK( s, ATA_STAT_SEEK);4250 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4431 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4432 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4251 4433 break; 4252 4434 case 0x55: /* read look-ahead disable */ 4253 4435 Log2(("%s: read look-ahead disable\n", __FUNCTION__)); 4254 ataR3CmdOK( s, ATA_STAT_SEEK);4255 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4436 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4437 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4256 4438 break; 4257 4439 case 0xcc: /* reverting to power-on defaults enable */ 4258 4440 Log2(("%s: revert to power-on defaults enable\n", __FUNCTION__)); 4259 ataR3CmdOK( s, ATA_STAT_SEEK);4260 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4441 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4442 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4261 4443 break; 4262 4444 case 0x66: /* reverting to power-on defaults disable */ 4263 4445 Log2(("%s: revert to power-on defaults disable\n", __FUNCTION__)); 4264 ataR3CmdOK( s, ATA_STAT_SEEK);4265 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4446 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4447 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4266 4448 break; 4267 4449 case 0x82: /* write cache disable */ … … 4269 4451 /* As per the ATA/ATAPI-6 specs, a write cache disable 4270 4452 * command MUST flush the write buffers to disc. */ 4271 ataR3StartTransfer( s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);4453 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false); 4272 4454 break; 4273 4455 case 0x03: { /* set transfer mode */ … … 4287 4469 goto abort_cmd; 4288 4470 } 4289 ataR3CmdOK( s, ATA_STAT_SEEK);4290 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4471 ataR3CmdOK(pCtl, s, ATA_STAT_SEEK); 4472 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4291 4473 break; 4292 4474 } … … 4304 4486 case ATA_FLUSH_CACHE_EXT: 4305 4487 case ATA_FLUSH_CACHE: 4306 if (! s->pDrvMedia || s->fATAPI)4488 if (!pDevR3->pDrvMedia || s->fATAPI) 4307 4489 goto abort_cmd; 4308 ataR3StartTransfer( s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);4490 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false); 4309 4491 break; 4310 4492 case ATA_STANDBY_IMMEDIATE: 4311 ataR3CmdOK( s, 0);4312 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4493 ataR3CmdOK(pCtl, s, 0); 4494 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4313 4495 break; 4314 4496 case ATA_IDLE_IMMEDIATE: 4315 4497 LogRel(("PIIX3 ATA: LUN#%d: aborting current command\n", s->iLUN)); 4316 ataR3AbortCurrentCommand( s, false);4498 ataR3AbortCurrentCommand(pDevIns, pCtl, s, false); 4317 4499 break; 4318 4500 case ATA_SLEEP: 4319 ataR3CmdOK( s, 0);4320 ataHCSetIRQ( s);4501 ataR3CmdOK(pCtl, s, 0); 4502 ataHCSetIRQ(pDevIns, pCtl, s); 4321 4503 break; 4322 4504 /* ATAPI commands */ 4323 4505 case ATA_IDENTIFY_PACKET_DEVICE: 4324 4506 if (s->fATAPI) 4325 ataR3StartTransfer( s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false);4507 ataR3StartTransfer(pDevIns, pCtl, s, 512, PDMMEDIATXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false); 4326 4508 else 4327 4509 { 4328 ataR3CmdError( s, ABRT_ERR);4329 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4510 ataR3CmdError(pCtl, s, ABRT_ERR); 4511 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4330 4512 } 4331 4513 break; 4332 4514 case ATA_EXECUTE_DEVICE_DIAGNOSTIC: 4333 ataR3StartTransfer( s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false);4515 ataR3StartTransfer(pDevIns, pCtl, s, 0, PDMMEDIATXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false); 4334 4516 break; 4335 4517 case ATA_DEVICE_RESET: … … 4337 4519 goto abort_cmd; 4338 4520 LogRel(("PIIX3 ATA: LUN#%d: performing device RESET\n", s->iLUN)); 4339 ataR3AbortCurrentCommand( s, true);4521 ataR3AbortCurrentCommand(pDevIns, pCtl, s, true); 4340 4522 break; 4341 4523 case ATA_PACKET: … … 4345 4527 if (s->uATARegFeature & 0x02) 4346 4528 goto abort_cmd; 4347 ataR3StartTransfer( s, ATAPI_PACKET_SIZE, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false);4529 ataR3StartTransfer(pDevIns, pCtl, s, ATAPI_PACKET_SIZE, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false); 4348 4530 break; 4349 4531 case ATA_DATA_SET_MANAGEMENT: 4350 if (! s->pDrvMedia || !s->pDrvMedia->pfnDiscard)4532 if (!pDevR3->pDrvMedia || !pDevR3->pDrvMedia->pfnDiscard) 4351 4533 goto abort_cmd; 4352 4534 if ( !(s->uATARegFeature & UINT8_C(0x01)) … … 4354 4536 goto abort_cmd; 4355 4537 s->fDMA = true; 4356 ataR3StartTransfer( s, (s->uATARegNSectorHOB << 8 | s->uATARegNSector) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_NULL, ATAFN_SS_TRIM, false);4538 ataR3StartTransfer(pDevIns, pCtl, s, (s->uATARegNSectorHOB << 8 | s->uATARegNSector) * s->cbSector, PDMMEDIATXDIR_TO_DEVICE, ATAFN_BT_NULL, ATAFN_SS_TRIM, false); 4357 4539 break; 4358 4540 default: 4359 4541 abort_cmd: 4360 ataR3CmdError( s, ABRT_ERR);4542 ataR3CmdError(pCtl, s, ABRT_ERR); 4361 4543 if (s->fATAPI) 4362 ataUnsetStatus( s, ATA_STAT_READY);4363 ataHCSetIRQ( s); /* Shortcut, do not use AIO thread. */4544 ataUnsetStatus(pCtl, s, ATA_STAT_READY); 4545 ataHCSetIRQ(pDevIns, pCtl, s); /* Shortcut, do not use AIO thread. */ 4364 4546 break; 4365 4547 } … … 4392 4574 */ 4393 4575 4394 static VBOXSTRICTRC ataIOPortWriteU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t val) 4395 { 4576 static VBOXSTRICTRC ataIOPortWriteU8(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t val, uintptr_t iCtl) 4577 { 4578 RT_NOREF(iCtl); 4396 4579 Log2(("%s: LUN#%d write addr=%#x val=%#04x\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN, addr, val)); 4397 4580 addr &= 7; … … 4446 4629 if (((val >> 4) & ATA_SELECTED_IF_MASK) != pCtl->iSelectedIf) 4447 4630 { 4448 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);4449 4450 4631 /* select another drive */ 4451 4632 uintptr_t const iSelectedIf = (val >> 4) & ATA_SELECTED_IF_MASK; … … 4486 4667 /* ignore commands to non-existent device */ 4487 4668 uintptr_t iSelectedIf = pCtl->iSelectedIf & ATA_SELECTED_IF_MASK; 4488 if (iSelectedIf && !pCtl->aIfs[iSelectedIf].pDrvMedia) 4669 PATADEVSTATE pDev = &pCtl->aIfs[iSelectedIf]; 4670 if (iSelectedIf && !pDev->fPresent) /** @todo r=bird the iSelectedIf test here looks bogus... explain. */ 4489 4671 break; 4490 4672 #ifndef IN_RING3 … … 4492 4674 return VINF_IOM_R3_IOPORT_WRITE; 4493 4675 #else /* IN_RING3 */ 4494 ataUnsetIRQ(&pCtl->aIfs[iSelectedIf]); 4495 ataR3ParseCmd(&pCtl->aIfs[iSelectedIf], val); 4676 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 4677 ataUnsetIRQ(pDevIns, pCtl, &pCtl->aIfs[iSelectedIf]); 4678 ataR3ParseCmd(pDevIns, pCtl, &pCtl->aIfs[iSelectedIf], &pThisCC->aCts[iCtl].aIfs[iSelectedIf], val); 4679 break; 4496 4680 #endif /* !IN_RING3 */ 4497 4681 } … … 4501 4685 4502 4686 4503 static VBOXSTRICTRC ataIOPortReadU8(P ATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32)4687 static VBOXSTRICTRC ataIOPortReadU8(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32) 4504 4688 { 4505 4689 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK]; … … 4508 4692 4509 4693 /* Check if the guest is reading from a non-existent device. */ 4510 if (RT_UNLIKELY(!s->pDrvMedia)) 4694 if (RT_LIKELY(s->fPresent)) 4695 { /* likely */ } 4696 else 4511 4697 { 4512 4698 if (pCtl->iSelectedIf) /* Device 1 selected, Device 0 responding for it. */ 4513 4699 { 4514 Assert(pCtl->aIfs[0]. pDrvMedia);4700 Assert(pCtl->aIfs[0].fPresent); 4515 4701 4516 4702 /* When an ATAPI device 0 responds for non-present device 1, it generally … … 4518 4704 * table 16 in ATA-6 specification. 4519 4705 */ 4520 if (((addr & 7) != 1) && pCtl->aIfs[0].fATAPI) { 4706 if (((addr & 7) != 1) && pCtl->aIfs[0].fATAPI) 4707 { 4521 4708 Log2(("%s: addr=%#x, val=0: LUN#%d not attached/LUN#%d ATAPI\n", __FUNCTION__, addr, s->iLUN, pCtl->aIfs[0].iLUN)); 4522 4709 *pu32 = 0; … … 4536 4723 } 4537 4724 } 4725 4538 4726 fHOB = !!(s->uATARegDevCtl & (1 << 7)); 4539 4727 switch (addr & 7) … … 4548 4736 * the feature register (write-only), so it seems that it's not 4549 4737 * necessary to support the usual HOB readback here. */ 4550 if (!s-> pDrvMedia)4738 if (!s->fPresent) 4551 4739 val = 0; 4552 4740 else … … 4581 4769 * one drive attached to the controller. It is common between 4582 4770 * both drives anyway (completely identical content). */ 4583 if (!pCtl->aIfs[0]. pDrvMedia && !pCtl->aIfs[1].pDrvMedia)4771 if (!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent) 4584 4772 val = 0; 4585 4773 else … … 4589 4777 case 7: /* primary status */ 4590 4778 { 4591 if (!s-> pDrvMedia)4779 if (!s->fPresent) 4592 4780 val = 0; 4593 4781 else … … 4609 4797 || pCtl->fReset; 4610 4798 4611 ataR3LockLeave(p Ctl);4799 ataR3LockLeave(pDevIns, pCtl); 4612 4800 4613 4801 /* … … 4631 4819 pCtl->u64ResetTime = u64ResetTimeStop; 4632 4820 # ifndef RT_OS_WINDOWS /* We've got this API on windows, but it doesn't necessarily interrupt I/O. */ 4633 RTThreadPoke(pCtl->AsyncIOThread); 4821 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 4822 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[pCtl->iCtl % RT_ELEMENTS(pThisCC->aCts)]; 4823 RTThreadPoke(pCtlR3->hAsyncIOThread); 4634 4824 # endif 4635 4825 Assert(fYield); … … 4645 4835 ASMNopPause(); 4646 4836 4647 ataR3LockEnter(p Ctl);4837 ataR3LockEnter(pDevIns, pCtl); 4648 4838 4649 4839 val = s->uATARegStatus; … … 4665 4855 s->cBusyStatusHackR3 = 0; 4666 4856 } 4667 ataUnsetIRQ( s);4857 ataUnsetIRQ(pDevIns, pCtl, s); 4668 4858 break; 4669 4859 } … … 4682 4872 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK]; 4683 4873 uint32_t val; 4684 RT_NOREF 1(uIoPortForLog);4685 4686 Assert(pCtl->aIfs[0]. pDrvMedia || pCtl->aIfs[1].pDrvMedia); /* Channel must not be empty. */4687 if (pCtl->iSelectedIf == 1 && !s-> pDrvMedia)4874 RT_NOREF(uIoPortForLog); 4875 4876 Assert(pCtl->aIfs[0].fPresent || pCtl->aIfs[1].fPresent); /* Channel must not be empty. */ 4877 if (pCtl->iSelectedIf == 1 && !s->fPresent) 4688 4878 val = 0; /* Device 1 selected, Device 0 responding for it. */ 4689 4879 else … … 4693 4883 } 4694 4884 4695 static int ataControlWrite(P ATACONTROLLER pCtl, uint32_t val, uint32_t uIoPortForLog)4696 { 4697 RT_NOREF 1(uIoPortForLog);4885 static int ataControlWrite(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t val, uint32_t uIoPortForLog) 4886 { 4887 RT_NOREF(uIoPortForLog); 4698 4888 #ifndef IN_RING3 4699 4889 if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_RESET) … … 4716 4906 uCmdWait1 = (uNow - pCtl->aIfs[1].u64CmdTS) / 1000; 4717 4907 LogRel(("PIIX3 ATA: Ctl#%d: RESET, DevSel=%d AIOIf=%d CmdIf0=%#04x (%d usec ago) CmdIf1=%#04x (%d usec ago)\n", 4718 ATACONTROLLER_IDX(pCtl), pCtl->iSelectedIf, pCtl->iAIOIf,4908 pCtl->iCtl, pCtl->iSelectedIf, pCtl->iAIOIf, 4719 4909 pCtl->aIfs[0].uATARegCommand, uCmdWait0, 4720 4910 pCtl->aIfs[1].uATARegCommand, uCmdWait1)); … … 4726 4916 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++) 4727 4917 { 4728 ataR3ResetDevice( &pCtl->aIfs[i]);4918 ataR3ResetDevice(pDevIns, pCtl, &pCtl->aIfs[i]); 4729 4919 /* The following cannot be done using ataSetStatusValue() since the 4730 4920 * reset flag is already set, which suppresses all status changes. */ … … 4734 4924 } 4735 4925 pCtl->iSelectedIf = 0; 4736 ataR3AsyncIOClearRequests(p Ctl);4737 Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));4926 ataR3AsyncIOClearRequests(pDevIns, pCtl); 4927 Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, pCtl->iCtl)); 4738 4928 if (val & ATA_DEVCTL_HOB) 4739 4929 { … … 4746 4936 4747 4937 /* Issue the reset request now. */ 4748 ataHCAsyncIOPutRequest(p Ctl, &g_ataResetARequest);4938 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataResetARequest); 4749 4939 #else /* !IN_RING3 */ 4750 4940 AssertMsgFailed(("RESET handling is too complicated for GC\n")); … … 4757 4947 /* Software RESET high to low */ 4758 4948 Log(("%s: deasserting RESET\n", __FUNCTION__)); 4759 Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));4949 Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, pCtl->iCtl)); 4760 4950 if (val & ATA_DEVCTL_HOB) 4761 4951 { … … 4763 4953 Log2(("%s: ignored setting HOB\n", __FUNCTION__)); 4764 4954 } 4765 ataHCAsyncIOPutRequest(p Ctl, &g_ataResetCRequest);4955 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataResetCRequest); 4766 4956 #else /* !IN_RING3 */ 4767 4957 AssertMsgFailed(("RESET handling is too complicated for GC\n")); … … 4782 4972 pCtl->BmDma.u8Status |= BM_STATUS_INT; 4783 4973 if (pCtl->irq == 16) 4784 PDMDevHlpPCISetIrq( CONTROLLER_2_DEVINS(pCtl), 0, 1);4974 PDMDevHlpPCISetIrq(pDevIns, 0, 1); 4785 4975 else 4786 PDMDevHlpISASetIrq( CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 1);4976 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1); 4787 4977 } 4788 4978 else … … 4790 4980 Log2(("%s: LUN#%d deasserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf & ATA_SELECTED_IF_MASK].iLUN)); 4791 4981 if (pCtl->irq == 16) 4792 PDMDevHlpPCISetIrq( CONTROLLER_2_DEVINS(pCtl), 0, 0);4982 PDMDevHlpPCISetIrq(pDevIns, 0, 0); 4793 4983 else 4794 PDMDevHlpISASetIrq( CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 0);4984 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0); 4795 4985 } 4796 4986 } … … 4807 4997 #if defined(IN_RING0) || defined(IN_RING3) 4808 4998 4809 static void ataHCPIOTransfer(P ATACONTROLLER pCtl)4999 static void ataHCPIOTransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl) 4810 5000 { 4811 5001 ATADevState *s; … … 4828 5018 { 4829 5019 bool fRedo; 4830 uint8_t status = s->uATARegStatus; 4831 ataSetStatusValue(s, ATA_STAT_BUSY); 5020 uint8_t status = s->uATARegStatus; 5021 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 5022 PATADEVSTATER3 pDevR3 = &pThisCC->aCts[pCtl->iCtl % RT_ELEMENTS(pThisCC->aCts)].aIfs[s->iDev % RT_ELEMENTS(pThisCC->aCts[0].aIfs)]; 5023 5024 ataSetStatusValue(pCtl, s, ATA_STAT_BUSY); 4832 5025 Log2(("%s: calling source/sink function\n", __FUNCTION__)); 4833 fRedo = g_apfnSourceSinkFuncs[iSourceSink]( s);5026 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3); 4834 5027 pCtl->fRedo = fRedo; 4835 5028 if (RT_UNLIKELY(fRedo)) 4836 5029 return; 4837 ataSetStatusValue( s, status);5030 ataSetStatusValue(pCtl, s, status); 4838 5031 s->iIOBufferCur = 0; 4839 5032 s->iIOBufferEnd = s->cbElementaryTransfer; … … 4857 5050 s->cbTotalTransfer, s->cbElementaryTransfer, 4858 5051 s->iIOBufferCur, s->iIOBufferEnd)); 4859 ataHCPIOTransferStart( s, s->iIOBufferCur, s->cbElementaryTransfer);5052 ataHCPIOTransferStart(pCtl, s, s->iIOBufferCur, s->cbElementaryTransfer); 4860 5053 s->cbTotalTransfer -= s->cbElementaryTransfer; 4861 5054 s->iIOBufferCur += s->cbElementaryTransfer; … … 4865 5058 } 4866 5059 else 4867 ataHCPIOTransferStop( s);4868 } 4869 4870 4871 DECLINLINE(void) ataHCPIOTransferFinish(P ATACONTROLLER pCtl, ATADevState *s)5060 ataHCPIOTransferStop(pDevIns, pCtl, s); 5061 } 5062 5063 5064 DECLINLINE(void) ataHCPIOTransferFinish(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, ATADevState *s) 4872 5065 { 4873 5066 /* Do not interfere with RESET processing if the PIO transfer finishes … … 4875 5068 if (pCtl->fReset) 4876 5069 { 4877 Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5070 Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, pCtl->iCtl)); 4878 5071 return; 4879 5072 } … … 4886 5079 * the case for write operations or generally for not yet finished 4887 5080 * transfers (some data might need to be read). */ 4888 ataSetStatus( s, ATA_STAT_BUSY);4889 ataUnsetStatus( s, ATA_STAT_READY | ATA_STAT_DRQ);4890 4891 Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));4892 ataHCAsyncIOPutRequest(p Ctl, &g_ataPIORequest);5081 ataSetStatus(pCtl, s, ATA_STAT_BUSY); 5082 ataUnsetStatus(pCtl, s, ATA_STAT_READY | ATA_STAT_DRQ); 5083 5084 Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, pCtl->iCtl)); 5085 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataPIORequest); 4893 5086 } 4894 5087 else … … 4898 5091 4899 5092 /* Continue a previously started transfer. */ 4900 ataUnsetStatus( s, ATA_STAT_DRQ);4901 ataSetStatus( s, ATA_STAT_READY);5093 ataUnsetStatus(pCtl, s, ATA_STAT_DRQ); 5094 ataSetStatus(pCtl, s, ATA_STAT_READY); 4902 5095 4903 5096 if (s->cbTotalTransfer) … … 4905 5098 /* There is more to transfer, happens usually for large ATAPI 4906 5099 * reads - the protocol limits the chunk size to 65534 bytes. */ 4907 ataHCPIOTransfer(p Ctl);4908 ataHCSetIRQ( s);5100 ataHCPIOTransfer(pDevIns, pCtl); 5101 ataHCSetIRQ(pDevIns, pCtl, s); 4909 5102 } 4910 5103 else 4911 5104 { 4912 Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5105 Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, pCtl->iCtl)); 4913 5106 /* Finish PIO transfer. */ 4914 ataHCPIOTransfer(p Ctl);5107 ataHCPIOTransfer(pDevIns, pCtl); 4915 5108 Assert(!pCtl->fRedo); 4916 5109 } … … 5010 5203 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 5011 5204 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 5012 RT_NOREF 1(offPort);5205 RT_NOREF(offPort); 5013 5206 5014 5207 Assert((uintptr_t)pvUser < 2); … … 5016 5209 Assert(cb == 2 || cb == 4); /* Writes to the data port may be 16-bit or 32-bit. */ 5017 5210 5018 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);5211 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE); 5019 5212 if (rc == VINF_SUCCESS) 5020 5213 { … … 5045 5238 { 5046 5239 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb); 5047 ataHCPIOTransferFinish(p Ctl, s);5240 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5048 5241 } 5049 5242 else … … 5056 5249 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cb); 5057 5250 if (s->iIOBufferPIODataStart >= iIOBufferPIODataEnd) 5058 ataHCPIOTransferFinish(p Ctl, s);5251 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5059 5252 #endif /* IN_RING 3*/ 5060 5253 } … … 5063 5256 5064 5257 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, offPort + pCtl->IOPortBase1, cb, &u32, VBOXSTRICTRC_VAL(rc))); 5065 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);5258 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 5066 5259 } 5067 5260 else … … 5081 5274 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 5082 5275 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 5083 RT_NOREF 1(offPort);5276 RT_NOREF(offPort); 5084 5277 5085 5278 Assert((uintptr_t)pvUser < 2); … … 5092 5285 *pu32 = 0; 5093 5286 5094 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_READ);5287 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ); 5095 5288 if (rc == VINF_SUCCESS) 5096 5289 { … … 5125 5318 { 5126 5319 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual); 5127 ataHCPIOTransferFinish(p Ctl, s);5320 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5128 5321 } 5129 5322 else … … 5136 5329 ataCopyPioData124(s, pbDst, pbSrc, iIOBufferPIODataStart, cbActual); 5137 5330 if (s->iIOBufferPIODataStart >= iIOBufferPIODataEnd) 5138 ataHCPIOTransferFinish(p Ctl, s);5331 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5139 5332 #endif /* IN_RING3 */ 5140 5333 … … 5150 5343 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, offPort, cb, pu32, VBOXSTRICTRC_VAL(rc))); 5151 5344 5152 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);5345 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 5153 5346 } 5154 5347 else … … 5169 5362 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 5170 5363 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 5171 RT_NOREF 1(offPort);5364 RT_NOREF(offPort); 5172 5365 5173 5366 Assert((uintptr_t)pvUser < 2); … … 5178 5371 if (cb == 2 || cb == 4) 5179 5372 { 5180 rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_READ);5373 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ); 5181 5374 if (rc == VINF_SUCCESS) 5182 5375 { … … 5217 5410 #ifdef IN_RING3 5218 5411 if (offEndThisXfer >= offEnd) 5219 ataHCPIOTransferFinish(p Ctl, s);5412 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5220 5413 #endif 5221 5414 *pcTransfers = cRequested - cAvailable; … … 5234 5427 } 5235 5428 5236 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);5429 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 5237 5430 } 5238 5431 } … … 5260 5453 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 5261 5454 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 5262 RT_NOREF 1(offPort);5455 RT_NOREF(offPort); 5263 5456 5264 5457 Assert((uintptr_t)pvUser < 2); … … 5269 5462 if (cb == 2 || cb == 4) 5270 5463 { 5271 rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);5464 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE); 5272 5465 if (rc == VINF_SUCCESS) 5273 5466 { … … 5307 5500 #ifdef IN_RING3 5308 5501 if (offEndThisXfer >= offEnd) 5309 ataHCPIOTransferFinish(p Ctl, s);5502 ataHCPIOTransferFinish(pDevIns, pCtl, s); 5310 5503 #endif 5311 5504 *pcTransfers = cRequested - cAvailable; … … 5320 5513 } 5321 5514 5322 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);5515 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 5323 5516 } 5324 5517 } … … 5355 5548 * @param pCtl Controller for which to perform the transfer. 5356 5549 */ 5357 static void ataR3DMATransfer(PATACONTROLLER pCtl) 5358 { 5359 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl); 5360 ATADevState *s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK]; 5550 static void ataR3DMATransfer(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATACONTROLLERR3 pCtlR3) 5551 { 5552 uint8_t const iAIOIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK; 5553 PATADEVSTATE s = &pCtl->aIfs[iAIOIf]; 5554 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iAIOIf]; 5361 5555 bool fRedo; 5362 5556 RTGCPHYS32 GCPhysDesc; … … 5380 5574 * necessary. This avoids long freezes should the guest access the 5381 5575 * ATA registers etc. for some reason. */ 5382 ataR3LockLeave(p Ctl);5576 ataR3LockLeave(pDevIns, pCtl); 5383 5577 5384 5578 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n", … … 5439 5633 cbElementaryTransfer = cbTotalTransfer; 5440 5634 5441 ataR3LockEnter(p Ctl);5635 ataR3LockEnter(pDevIns, pCtl); 5442 5636 5443 5637 /* The RESET handler could have cleared the DMA transfer … … 5454 5648 s->cbTotalTransfer = cbTotalTransfer; 5455 5649 Log2(("%s: calling source/sink function\n", __FUNCTION__)); 5456 fRedo = g_apfnSourceSinkFuncs[iSourceSink]( s);5650 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3); 5457 5651 if (RT_UNLIKELY(fRedo)) 5458 5652 { … … 5481 5675 } 5482 5676 5483 ataR3LockLeave(p Ctl);5677 ataR3LockLeave(pDevIns, pCtl); 5484 5678 if (RT_UNLIKELY(fRedo)) 5485 5679 break; … … 5494 5688 break; 5495 5689 5496 ataR3LockEnter(p Ctl);5690 ataR3LockEnter(pDevIns, pCtl); 5497 5691 5498 5692 if (!(pCtl->BmDma.u8Cmd & BM_CMD_START) || pCtl->fReset) 5499 5693 { 5500 LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", ATACONTROLLER_IDX(pCtl), pCtl->fReset ? " due to RESET" : ""));5694 LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", pCtl->iCtl, pCtl->fReset ? " due to RESET" : "")); 5501 5695 if (!pCtl->fReset) 5502 5696 ataR3DMATransferStop(s); … … 5505 5699 } 5506 5700 5507 ataR3LockLeave(p Ctl);5508 } 5509 5510 ataR3LockEnter(p Ctl);5701 ataR3LockLeave(pDevIns, pCtl); 5702 } 5703 5704 ataR3LockEnter(pDevIns, pCtl); 5511 5705 if (RT_UNLIKELY(fRedo)) 5512 5706 return; … … 5523 5717 * Signal PDM that we're idle (if we actually are). 5524 5718 * 5525 * @param pCtl The controller. 5526 */ 5527 static void ataR3AsyncSignalIdle(PATACONTROLLER pCtl) 5719 * @param pDevIns The device instance. 5720 * @param pCtl The shared controller state. 5721 * @param pCtlR3 The ring-3 controller state. 5722 */ 5723 static void ataR3AsyncSignalIdle(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PATACONTROLLERR3 pCtlR3) 5528 5724 { 5529 5725 /* … … 5531 5727 * unnecessary work and racing ataR3WaitForAsyncIOIsIdle. 5532 5728 */ 5533 int rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock, VINF_SUCCESS);5729 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 5534 5730 AssertRC(rc); 5535 5731 5536 if ( pCtl ->fSignalIdle5537 && ataR3AsyncIOIsIdle(p Ctl, false /*fStrict*/))5538 { 5539 PDMDevHlpAsyncNotificationCompleted(p Ctl->pDevInsR3);5540 RTThreadUserSignal(pCtl ->AsyncIOThread); /* for ataR3Construct/ataR3ResetCommon. */5541 } 5542 5543 rc = PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->AsyncIORequestLock);5732 if ( pCtlR3->fSignalIdle 5733 && ataR3AsyncIOIsIdle(pDevIns, pCtl, false /*fStrict*/)) 5734 { 5735 PDMDevHlpAsyncNotificationCompleted(pDevIns); 5736 RTThreadUserSignal(pCtlR3->hAsyncIOThread); /* for ataR3Construct/ataR3ResetCommon. */ 5737 } 5738 5739 rc = PDMDevHlpCritSectLeave(pDevIns, &pCtl->AsyncIORequestLock); 5544 5740 AssertRC(rc); 5545 5741 } … … 5555 5751 static DECLCALLBACK(int) ataR3AsyncIOThread(RTTHREAD hThreadSelf, void *pvUser) 5556 5752 { 5557 RT_NOREF1(hThreadSelf); 5558 const ATARequest *pReq; 5559 uint64_t u64TS = 0; /* shut up gcc */ 5560 uint64_t uWait; 5561 PATACONTROLLER pCtl = (PATACONTROLLER)pvUser; 5562 PPDMDEVINSR3 pDevIns = pCtl->CTX_SUFF(pDevIns); 5563 int rc = VINF_SUCCESS; 5564 ATADevState *s; 5753 PATACONTROLLERR3 const pCtlR3 = (PATACONTROLLERR3)pvUser; 5754 PPDMDEVINSR3 const pDevIns = pCtlR3->pDevIns; 5755 PATASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 5756 PATASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 5757 uintptr_t const iCtl = pCtlR3 - &pThisCC->aCts[0]; 5758 PATACONTROLLER const pCtl = &pThis->aCts[iCtl % RT_ELEMENTS(pThisCC->aCts)]; 5759 int rc = VINF_SUCCESS; 5760 uint64_t u64TS = 0; /* shut up gcc */ 5761 uint64_t uWait; 5762 const ATARequest *pReq; 5763 RT_NOREF(hThreadSelf); 5764 Assert(pCtl->iCtl == pCtlR3->iCtl); 5565 5765 5566 5766 pReq = NULL; 5567 5767 pCtl->fChainedTransfer = false; 5568 while (!pCtl ->fShutdown)5768 while (!pCtlR3->fShutdown) 5569 5769 { 5570 5770 /* Keep this thread from doing anything as long as EMT is suspended. */ 5571 5771 while (pCtl->fRedoIdle) 5572 5772 { 5573 if (pCtl ->fSignalIdle)5574 ataR3AsyncSignalIdle(p Ctl);5575 rc = RTSemEventWait(pCtl ->SuspendIOSem, RT_INDEFINITE_WAIT);5773 if (pCtlR3->fSignalIdle) 5774 ataR3AsyncSignalIdle(pDevIns, pCtl, pCtlR3); 5775 rc = RTSemEventWait(pCtlR3->hSuspendIOSem, RT_INDEFINITE_WAIT); 5576 5776 /* Continue if we got a signal by RTThreadPoke(). 5577 5777 * We will get notified if there is a request to process. … … 5579 5779 if (RT_UNLIKELY(rc == VERR_INTERRUPTED)) 5580 5780 continue; 5581 if (RT_FAILURE(rc) || pCtl ->fShutdown)5781 if (RT_FAILURE(rc) || pCtlR3->fShutdown) 5582 5782 break; 5583 5783 … … 5588 5788 while (pReq == NULL) 5589 5789 { 5590 if (pCtl ->fSignalIdle)5591 ataR3AsyncSignalIdle(p Ctl);5790 if (pCtlR3->fSignalIdle) 5791 ataR3AsyncSignalIdle(pDevIns, pCtl, pCtlR3); 5592 5792 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pCtl->hAsyncIOSem, RT_INDEFINITE_WAIT); 5593 5793 /* Continue if we got a signal by RTThreadPoke(). … … 5596 5796 if (RT_UNLIKELY(rc == VERR_INTERRUPTED)) 5597 5797 continue; 5598 if (RT_FAILURE(rc) || RT_UNLIKELY(pCtl ->fShutdown))5798 if (RT_FAILURE(rc) || RT_UNLIKELY(pCtlR3->fShutdown)) 5599 5799 break; 5600 5800 5601 pReq = ataR3AsyncIOGetCurrentRequest(p Ctl);5602 } 5603 5604 if (RT_FAILURE(rc) || pCtl ->fShutdown)5801 pReq = ataR3AsyncIOGetCurrentRequest(pDevIns, pCtl); 5802 } 5803 5804 if (RT_FAILURE(rc) || pCtlR3->fShutdown) 5605 5805 break; 5606 5806 … … 5610 5810 ATAAIO ReqType = pReq->ReqType; 5611 5811 5612 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->uAsyncIOState, ReqType));5812 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, pCtl->iCtl, pCtl->uAsyncIOState, ReqType)); 5613 5813 if (pCtl->uAsyncIOState != ReqType) 5614 5814 { … … 5620 5820 { 5621 5821 /* Incorrect sequence of PIO/DMA states. Dump request queue. */ 5622 ataR3AsyncIODumpRequests(p Ctl);5822 ataR3AsyncIODumpRequests(pDevIns, pCtl); 5623 5823 } 5624 5824 AssertReleaseMsg( ReqType == ATA_AIO_RESET_ASSERTED … … 5630 5830 5631 5831 /* Do our work. */ 5632 ataR3LockEnter(p Ctl);5832 ataR3LockEnter(pDevIns, pCtl); 5633 5833 5634 5834 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer) … … 5644 5844 case ATA_AIO_NEW: 5645 5845 { 5646 pCtl->iAIOIf = pReq->u.t.iIf; 5647 s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK]; 5846 uint8_t const iIf = pReq->u.t.iIf & ATA_SELECTED_IF_MASK; 5847 pCtl->iAIOIf = iIf; 5848 PATADEVSTATE s = &pCtl->aIfs[iIf]; 5849 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iIf]; 5850 5648 5851 s->cbTotalTransfer = pReq->u.t.cbTotalTransfer; 5649 5852 s->uTxDir = pReq->u.t.uTxDir; … … 5679 5882 && iBeginTransfer < RT_ELEMENTS(g_apfnBeginTransFuncs)) 5680 5883 { 5681 Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5682 g_apfnBeginTransFuncs[iBeginTransfer]( s);5884 Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, pCtl->iCtl)); 5885 g_apfnBeginTransFuncs[iBeginTransfer](pCtl, s); 5683 5886 s->iBeginTransfer = ATAFN_BT_NULL; 5684 5887 if (s->uTxDir != PDMMEDIATXDIR_FROM_DEVICE) … … 5700 5903 { 5701 5904 bool fRedo; 5702 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5703 fRedo = g_apfnSourceSinkFuncs[iSourceSink]( s);5905 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, pCtl->iCtl)); 5906 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3); 5704 5907 pCtl->fRedo = fRedo; 5705 5908 if (RT_UNLIKELY(fRedo && !pCtl->fReset)) … … 5708 5911 * everything from scratch by resending the current 5709 5912 * request. Occurs very rarely, not worth optimizing. */ 5710 LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5711 ataHCAsyncIOPutRequest(p Ctl, pReq);5913 LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, pCtl->iCtl)); 5914 ataHCAsyncIOPutRequest(pDevIns, pCtl, pReq); 5712 5915 break; 5713 5916 } … … 5716 5919 { 5717 5920 Assert(iSourceSink == ATAFN_SS_NULL); 5718 ataR3CmdOK( s, 0);5921 ataR3CmdOK(pCtl, s, 0); 5719 5922 } 5720 5923 s->iIOBufferEnd = s->cbElementaryTransfer; … … 5733 5936 if (s->cbTotalTransfer) 5734 5937 { 5735 ataSetStatus( s, ATA_STAT_DRQ);5938 ataSetStatus(pCtl, s, ATA_STAT_DRQ); 5736 5939 5737 5940 pCtl->uAsyncIOState = ATA_AIO_DMA; … … 5739 5942 if (pCtl->BmDma.u8Cmd & BM_CMD_START) 5740 5943 { 5741 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", 5742 __FUNCTION__, ATACONTROLLER_IDX(pCtl))); 5743 ataHCAsyncIOPutRequest(pCtl, &g_ataDMARequest); 5944 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", __FUNCTION__, pCtl->iCtl)); 5945 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest); 5744 5946 } 5745 5947 } … … 5749 5951 /* Finish DMA transfer. */ 5750 5952 ataR3DMATransferStop(s); 5751 ataHCSetIRQ( s);5953 ataHCSetIRQ(pDevIns, pCtl, s); 5752 5954 pCtl->uAsyncIOState = ATA_AIO_NEW; 5753 5955 } … … 5757 5959 if (s->cbTotalTransfer) 5758 5960 { 5759 ataHCPIOTransfer(p Ctl);5961 ataHCPIOTransfer(pDevIns, pCtl); 5760 5962 Assert(!pCtl->fRedo); 5761 5963 if (s->fATAPITransfer || s->uTxDir != PDMMEDIATXDIR_TO_DEVICE) 5762 ataHCSetIRQ( s);5964 ataHCSetIRQ(pDevIns, pCtl, s); 5763 5965 5764 5966 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL) … … 5785 5987 Assert(s->uTxDir == PDMMEDIATXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */ 5786 5988 /* Finish PIO transfer. */ 5787 ataHCPIOTransfer(p Ctl);5989 ataHCPIOTransfer(pDevIns, pCtl); 5788 5990 Assert(!pCtl->fRedo); 5789 5991 if (!s->fATAPITransfer) 5790 ataHCSetIRQ( s);5992 ataHCSetIRQ(pDevIns, pCtl, s); 5791 5993 pCtl->uAsyncIOState = ATA_AIO_NEW; 5792 5994 } … … 5797 5999 case ATA_AIO_DMA: 5798 6000 { 5799 BMDMAState *bm = &pCtl->BmDma;5800 s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK]; /* Do not remove or there's an instant crash after loading the saved state */6001 BMDMAState *bm = &pCtl->BmDma; 6002 PATADEVSTATE s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK]; 5801 6003 ATAFNSS iOriginalSourceSink = (ATAFNSS)s->iSourceSink; /* Used by the hack below, but gets reset by then. */ 5802 6004 … … 5813 6015 pCtl->GCPhysLastDMADesc = RT_ALIGN_32(bm->GCPhysAddr + 1, _4K) - sizeof(BMDMADesc); 5814 6016 } 5815 ataR3DMATransfer(p Ctl);6017 ataR3DMATransfer(pDevIns, pCtl, pCtlR3); 5816 6018 5817 6019 if (RT_UNLIKELY(pCtl->fRedo && !pCtl->fReset)) 5818 6020 { 5819 LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", ATACONTROLLER_IDX(pCtl)));5820 ataHCAsyncIOPutRequest(p Ctl, &g_ataDMARequest);6021 LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", pCtl->iCtl)); 6022 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest); 5821 6023 break; 5822 6024 } … … 5832 6034 * solution has been found. */ 5833 6035 Log(("%s: delay IRQ hack\n", __FUNCTION__)); 5834 ataR3LockLeave(p Ctl);6036 ataR3LockLeave(pDevIns, pCtl); 5835 6037 RTThreadSleep(pCtl->msDelayIRQ); 5836 ataR3LockEnter(p Ctl);6038 ataR3LockEnter(pDevIns, pCtl); 5837 6039 } 5838 6040 5839 ataUnsetStatus( s, ATA_STAT_DRQ);6041 ataUnsetStatus(pCtl, s, ATA_STAT_DRQ); 5840 6042 Assert(!pCtl->fChainedTransfer); 5841 6043 Assert(s->iSourceSink == ATAFN_SS_NULL); … … 5843 6045 { 5844 6046 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD; 5845 Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegNSector));6047 Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, pCtl->iCtl, s->uATARegNSector)); 5846 6048 s->fATAPITransfer = false; 5847 6049 } 5848 ataHCSetIRQ( s);6050 ataHCSetIRQ(pDevIns, pCtl, s); 5849 6051 pCtl->uAsyncIOState = ATA_AIO_NEW; 5850 6052 break; … … 5853 6055 case ATA_AIO_PIO: 5854 6056 { 5855 s = &pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK]; /* Do not remove or there's an instant crash after loading the saved state */ 6057 uint8_t const iIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK; 6058 pCtl->iAIOIf = iIf; 6059 PATADEVSTATE s = &pCtl->aIfs[iIf]; 6060 PATADEVSTATER3 pDevR3 = &pCtlR3->aIfs[iIf]; 5856 6061 5857 6062 uint8_t const iSourceSink = s->iSourceSink; … … 5860 6065 { 5861 6066 bool fRedo; 5862 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));5863 fRedo = g_apfnSourceSinkFuncs[iSourceSink]( s);6067 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, pCtl->iCtl)); 6068 fRedo = g_apfnSourceSinkFuncs[iSourceSink](pDevIns, pCtl, s, pDevR3); 5864 6069 pCtl->fRedo = fRedo; 5865 6070 if (RT_UNLIKELY(fRedo && !pCtl->fReset)) 5866 6071 { 5867 LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", ATACONTROLLER_IDX(pCtl)));5868 ataHCAsyncIOPutRequest(p Ctl, &g_ataPIORequest);6072 LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", pCtl->iCtl)); 6073 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataPIORequest); 5869 6074 break; 5870 6075 } … … 5876 6081 /* Continue a previously started transfer. */ 5877 6082 Assert(iSourceSink == ATAFN_SS_NULL); 5878 ataUnsetStatus( s, ATA_STAT_BUSY);5879 ataSetStatus( s, ATA_STAT_READY);6083 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY); 6084 ataSetStatus(pCtl, s, ATA_STAT_READY); 5880 6085 } 5881 6086 … … 5890 6095 if (s->cbTotalTransfer) 5891 6096 { 5892 ataHCPIOTransfer(p Ctl);5893 ataHCSetIRQ( s);6097 ataHCPIOTransfer(pDevIns, pCtl); 6098 ataHCSetIRQ(pDevIns, pCtl, s); 5894 6099 5895 6100 if (s->uTxDir == PDMMEDIATXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL) … … 5915 6120 { 5916 6121 /* Finish PIO transfer. */ 5917 ataHCPIOTransfer(p Ctl);6122 ataHCPIOTransfer(pDevIns, pCtl); 5918 6123 if ( !pCtl->fChainedTransfer 5919 6124 && !s->fATAPITransfer 5920 6125 && s->uTxDir != PDMMEDIATXDIR_FROM_DEVICE) 5921 6126 { 5922 ataHCSetIRQ( s);6127 ataHCSetIRQ(pDevIns, pCtl, s); 5923 6128 } 5924 6129 pCtl->uAsyncIOState = ATA_AIO_NEW; … … 5929 6134 case ATA_AIO_RESET_ASSERTED: 5930 6135 pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED; 5931 ataHCPIOTransferStop( &pCtl->aIfs[0]);5932 ataHCPIOTransferStop( &pCtl->aIfs[1]);6136 ataHCPIOTransferStop(pDevIns, pCtl, &pCtl->aIfs[0]); 6137 ataHCPIOTransferStop(pDevIns, pCtl, &pCtl->aIfs[1]); 5933 6138 /* Do not change the DMA registers, they are not affected by the 5934 6139 * ATA controller reset logic. It should be sufficient to issue a … … 5943 6148 pCtl->fRedo = false; 5944 6149 pCtl->fRedoDMALastDesc = false; 5945 LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n", 5946 ATACONTROLLER_IDX(pCtl))); 6150 LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n", pCtl->iCtl)); 5947 6151 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++) 5948 6152 { 5949 6153 if (pCtl->aIfs[i].fATAPI) 5950 ataSetStatusValue( &pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */6154 ataSetStatusValue(pCtl, &pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */ 5951 6155 else 5952 ataSetStatusValue( &pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK);6156 ataSetStatusValue(pCtl, &pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK); 5953 6157 ataR3SetSignature(&pCtl->aIfs[i]); 5954 6158 } … … 5956 6160 5957 6161 case ATA_AIO_ABORT: 6162 { 5958 6163 /* Abort the current command no matter what. There cannot be 5959 6164 * any command activity on the other drive otherwise using 5960 6165 * one thread per controller wouldn't work at all. */ 5961 s = &pCtl->aIfs[pReq->u.a.iIf & ATA_SELECTED_IF_MASK];6166 PATADEVSTATE s = &pCtl->aIfs[pReq->u.a.iIf & ATA_SELECTED_IF_MASK]; 5962 6167 5963 6168 pCtl->uAsyncIOState = ATA_AIO_NEW; … … 5967 6172 if (pReq->u.a.fResetDrive) 5968 6173 { 5969 ataR3ResetDevice( s);5970 ataR3DeviceDiag( s);6174 ataR3ResetDevice(pDevIns, pCtl, s); 6175 ataR3DeviceDiag(pCtl, s); 5971 6176 } 5972 6177 else … … 5974 6179 /* Stop any pending DMA transfer. */ 5975 6180 s->fDMA = false; 5976 ataHCPIOTransferStop( s);5977 ataUnsetStatus( s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR);5978 ataSetStatus( s, ATA_STAT_READY);5979 ataHCSetIRQ( s);6181 ataHCPIOTransferStop(pDevIns, pCtl, s); 6182 ataUnsetStatus(pCtl, s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR); 6183 ataSetStatus(pCtl, s, ATA_STAT_READY); 6184 ataHCSetIRQ(pDevIns, pCtl, s); 5980 6185 } 5981 6186 break; 6187 } 5982 6188 5983 6189 default: … … 5985 6191 } 5986 6192 5987 ataR3AsyncIORemoveCurrentRequest(p Ctl, ReqType);5988 pReq = ataR3AsyncIOGetCurrentRequest(p Ctl);6193 ataR3AsyncIORemoveCurrentRequest(pDevIns, pCtl, ReqType); 6194 pReq = ataR3AsyncIOGetCurrentRequest(pDevIns, pCtl); 5989 6195 5990 6196 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer) … … 5998 6204 uintptr_t const iAIOIf = pCtl->iAIOIf & ATA_SELECTED_IF_MASK; 5999 6205 Log(("%s: Ctl#%d: LUN#%d finished I/O transaction in %d microseconds\n", 6000 __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->aIfs[iAIOIf].iLUN, (uint32_t)(uWait)));6206 __FUNCTION__, pCtl->iCtl, pCtl->aIfs[iAIOIf].iLUN, (uint32_t)(uWait))); 6001 6207 /* Mark command as finished. */ 6002 6208 pCtl->aIfs[iAIOIf].u64CmdTS = 0; … … 6047 6253 } 6048 6254 6049 ataR3LockLeave(p Ctl);6255 ataR3LockLeave(pDevIns, pCtl); 6050 6256 } 6051 6257 6052 6258 /* Signal the ultimate idleness. */ 6053 RTThreadUserSignal(pCtl ->AsyncIOThread);6054 if (pCtl ->fSignalIdle)6259 RTThreadUserSignal(pCtlR3->hAsyncIOThread); 6260 if (pCtlR3->fSignalIdle) 6055 6261 PDMDevHlpAsyncNotificationCompleted(pDevIns); 6056 6262 6057 6263 /* Cleanup the state. */ 6058 6264 /* Do not destroy request lock yet, still needed for proper shutdown. */ 6059 pCtl ->fShutdown = false;6060 6061 Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), rc));6265 pCtlR3->fShutdown = false; 6266 6267 Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, pCtl->iCtl, rc)); 6062 6268 return rc; 6063 6269 } … … 6068 6274 { 6069 6275 uint32_t val = pCtl->BmDma.u8Cmd; 6070 RT_NOREF 1(addr);6276 RT_NOREF(addr); 6071 6277 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val)); 6072 6278 return val; … … 6074 6280 6075 6281 6076 static void ataBMDMACmdWriteB(P ATACONTROLLER pCtl, uint32_t addr, uint32_t val)6077 { 6078 RT_NOREF 1(addr);6282 static void ataBMDMACmdWriteB(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, uint32_t addr, uint32_t val) 6283 { 6284 RT_NOREF(pDevIns, addr); 6079 6285 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val)); 6080 6286 if (!(val & BM_CMD_START)) … … 6096 6302 if (pCtl->fReset) 6097 6303 { 6098 Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));6304 Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, pCtl->iCtl)); 6099 6305 return; 6100 6306 } … … 6108 6314 if (pCtl->aIfs[pCtl->iAIOIf & ATA_SELECTED_IF_MASK].uATARegStatus & ATA_STAT_DRQ) 6109 6315 { 6110 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));6111 ataHCAsyncIOPutRequest(p Ctl, &g_ataDMARequest);6316 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, pCtl->iCtl)); 6317 ataHCAsyncIOPutRequest(pDevIns, pCtl, &g_ataDMARequest); 6112 6318 } 6113 6319 #else /* !IN_RING3 */ … … 6120 6326 { 6121 6327 uint32_t val = pCtl->BmDma.u8Status; 6122 RT_NOREF 1(addr);6328 RT_NOREF(addr); 6123 6329 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val)); 6124 6330 return val; … … 6127 6333 static void ataBMDMAStatusWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val) 6128 6334 { 6129 RT_NOREF 1(addr);6335 RT_NOREF(addr); 6130 6336 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val)); 6131 6337 pCtl->BmDma.u8Status = (val & (BM_STATUS_D0DMA | BM_STATUS_D1DMA)) … … 6137 6343 { 6138 6344 uint32_t val = (uint32_t)pCtl->BmDma.GCPhysAddr; 6139 RT_NOREF 1(addr);6345 RT_NOREF(addr); 6140 6346 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val)); 6141 6347 return val; … … 6144 6350 static void ataBMDMAAddrWriteL(PATACONTROLLER pCtl, uint32_t addr, uint32_t val) 6145 6351 { 6146 RT_NOREF 1(addr);6352 RT_NOREF(addr); 6147 6353 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val)); 6148 6354 pCtl->BmDma.GCPhysAddr = val & ~3; … … 6151 6357 static void ataBMDMAAddrWriteLowWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val) 6152 6358 { 6153 RT_NOREF 1(addr);6359 RT_NOREF(addr); 6154 6360 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val)); 6155 6361 pCtl->BmDma.GCPhysAddr = (pCtl->BmDma.GCPhysAddr & 0xFFFF0000) | RT_LOWORD(val & ~3); … … 6160 6366 { 6161 6367 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val)); 6162 RT_NOREF 1(addr);6368 RT_NOREF(addr); 6163 6369 pCtl->BmDma.GCPhysAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.GCPhysAddr); 6164 6370 } … … 6178 6384 RT_NOREF(pvUser); 6179 6385 6180 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_READ);6386 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ); 6181 6387 if (rc == VINF_SUCCESS) 6182 6388 { … … 6197 6403 break; 6198 6404 } 6199 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6405 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6200 6406 } 6201 6407 return rc; … … 6213 6419 RT_NOREF(pvUser); 6214 6420 6215 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);6421 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE); 6216 6422 if (rc == VINF_SUCCESS) 6217 6423 { … … 6226 6432 } 6227 6433 #endif 6228 ataBMDMACmdWriteB(p Ctl, offPort, u32);6434 ataBMDMACmdWriteB(pDevIns, pCtl, offPort, u32); 6229 6435 break; 6230 6436 case VAL(2, 1): ataBMDMAStatusWriteB(pCtl, offPort, u32); break; … … 6236 6442 break; 6237 6443 } 6238 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6444 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6239 6445 } 6240 6446 return rc; … … 6252 6458 static DECLCALLBACK(void *) ataR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID) 6253 6459 { 6254 P CIATAState *pThis = RT_FROM_MEMBER(pInterface, PCIATAState, IBase);6255 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis ->IBase);6256 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis ->ILeds);6460 PATASTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ATASTATER3, IBase); 6461 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase); 6462 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds); 6257 6463 return NULL; 6258 6464 } … … 6271 6477 static DECLCALLBACK(int) ataR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed) 6272 6478 { 6273 PCIATAState *pThis = RT_FROM_MEMBER(pInterface, PCIATAState, ILeds);6274 6479 if (iLUN < 4) 6275 6480 { 6481 PATASTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ATASTATER3, ILeds); 6482 PATASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PATASTATE); 6276 6483 switch (iLUN) 6277 6484 { … … 6295 6502 static DECLCALLBACK(void *) ataR3QueryInterface(PPDMIBASE pInterface, const char *pszIID) 6296 6503 { 6297 ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IBase);6298 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIf ->IBase);6299 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pIf ->IPort);6300 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pIf ->IMountNotify);6504 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IBase); 6505 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIfR3->IBase); 6506 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pIfR3->IPort); 6507 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pIfR3->IMountNotify); 6301 6508 return NULL; 6302 6509 } … … 6311 6518 uint32_t *piInstance, uint32_t *piLUN) 6312 6519 { 6313 ATADevState *pIf = RT_FROM_MEMBER(pInterface, ATADevState, IPort);6314 PPDMDEVINS pDevIns = pIf->CTX_SUFF(pDevIns);6520 PATADEVSTATER3 pIfR3 = RT_FROM_MEMBER(pInterface, ATADEVSTATER3, IPort); 6521 PPDMDEVINS pDevIns = pIfR3->pDevIns; 6315 6522 6316 6523 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER); … … 6320 6527 *ppcszController = pDevIns->pReg->szName; 6321 6528 *piInstance = pDevIns->iInstance; 6322 *piLUN = pIf ->iLUN;6529 *piLUN = pIfR3->iLUN; 6323 6530 6324 6531 return VINF_SUCCESS; … … 6344 6551 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 6345 6552 Assert((uintptr_t)pvUser < 2); 6346 Assert(!pCtl->aIfs[0]. pDrvMedia && !pCtl->aIfs[1].pDrvMedia);6553 Assert(!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent); 6347 6554 #endif 6348 6555 … … 6368 6575 Assert((uintptr_t)pvUser < 2); 6369 6576 Assert(cb <= 4); 6370 Assert(!pCtl->aIfs[0]. pDrvMedia && !pCtl->aIfs[1].pDrvMedia);6577 Assert(!pCtl->aIfs[0].fPresent && !pCtl->aIfs[1].fPresent); 6371 6578 #endif 6372 6579 … … 6397 6604 { 6398 6605 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 6399 PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)]; 6606 uintptr_t iCtl = (uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts); 6607 PATACONTROLLER pCtl = &pThis->aCts[iCtl]; 6400 6608 6401 6609 Assert((uintptr_t)pvUser < 2); 6402 6610 6403 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);6611 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE); 6404 6612 if (rc == VINF_SUCCESS) 6405 6613 { … … 6411 6619 Log(("ataIOPortWrite1: suspect write to port %x val=%x size=%d\n", offPort, u32, cb)); 6412 6620 6413 rc = ataIOPortWriteU8(p Ctl, offPort, u32);6414 6415 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6621 rc = ataIOPortWriteU8(pDevIns, pCtl, offPort, u32, iCtl); 6622 6623 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6416 6624 } 6417 6625 return rc; … … 6432 6640 Assert((uintptr_t)pvUser < 2); 6433 6641 6434 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_READ);6642 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ); 6435 6643 if (rc == VINF_SUCCESS) 6436 6644 { … … 6439 6647 * Undocumented, but observed on a real PIIX4 system. 6440 6648 */ 6441 rc = ataIOPortReadU8(p Ctl, offPort, pu32);6649 rc = ataIOPortReadU8(pDevIns, pCtl, offPort, pu32); 6442 6650 if (cb > 1) 6443 6651 { … … 6451 6659 Log(("ataIOPortRead1: suspect read from port %x size=%d\n", offPort, cb)); 6452 6660 } 6453 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6661 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6454 6662 } 6455 6663 return rc; … … 6473 6681 if (cb == 1) 6474 6682 { 6475 rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);6683 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_WRITE); 6476 6684 if (rc == VINF_SUCCESS) 6477 6685 { 6478 rc = ataControlWrite(p Ctl, u32, offPort);6479 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6686 rc = ataControlWrite(pDevIns, pCtl, u32, offPort); 6687 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6480 6688 } 6481 6689 } … … 6505 6713 if (cb == 1) 6506 6714 { 6507 rc = PDMDevHlpCritSectEnter(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock, VINF_IOM_R3_IOPORT_READ);6715 rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_IOM_R3_IOPORT_READ); 6508 6716 if (rc == VINF_SUCCESS) 6509 6717 { 6510 6718 *pu32 = ataStatusRead(pCtl, offPort); 6511 PDMDevHlpCritSectLeave(p Ctl->CTX_SUFF(pDevIns), &pCtl->lock);6719 PDMDevHlpCritSectLeave(pDevIns, &pCtl->lock); 6512 6720 } 6513 6721 } … … 6533 6741 static DECLCALLBACK(void) ataR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags) 6534 6742 { 6535 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 6743 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 6744 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 6536 6745 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG, 6537 6746 ("PIIX3IDE: Device does not support hotplugging\n")); RT_NOREF(fFlags); … … 6542 6751 unsigned iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs); 6543 6752 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN)); 6544 PATACONTROLLER pCtl = &pThis->aCts[iController]; 6753 PATACONTROLLER pCtl = &pThis->aCts[iController]; 6754 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[iController]; 6545 6755 6546 6756 unsigned iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs); 6547 ATADevState *pIf = &pCtl->aIfs[iInterface]; 6757 PATADEVSTATE pIf = &pCtl->aIfs[iInterface]; 6758 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[iInterface]; 6548 6759 6549 6760 /* 6550 6761 * Zero some important members. 6551 6762 */ 6552 pIf->pDrvBase = NULL; 6553 pIf->pDrvMedia = NULL; 6554 pIf->pDrvMount = NULL; 6763 pIfR3->pDrvBase = NULL; 6764 pIfR3->pDrvMedia = NULL; 6765 pIfR3->pDrvMount = NULL; 6766 pIf->fPresent = false; 6555 6767 6556 6768 /* … … 6565 6777 * 6566 6778 * @returns VBox status code. 6567 * @param pIf The ATA unit state. 6568 */ 6569 static int ataR3ConfigLun(ATADevState *pIf) 6779 * @param pIf The ATA unit state, shared bits. 6780 * @param pIfR3 The ATA unit state, ring-3 bits. 6781 */ 6782 static int ataR3ConfigLun(PATADEVSTATE pIf, PATADEVSTATER3 pIfR3) 6570 6783 { 6571 6784 /* 6572 6785 * Query Block, Bios and Mount interfaces. 6573 6786 */ 6574 pIf ->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIMEDIA);6575 if (!pIf ->pDrvMedia)6787 pIfR3->pDrvMedia = PDMIBASE_QUERY_INTERFACE(pIfR3->pDrvBase, PDMIMEDIA); 6788 if (!pIfR3->pDrvMedia) 6576 6789 { 6577 6790 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pIf->iLUN)); … … 6579 6792 } 6580 6793 6581 pIf->pDrvMount = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIMOUNT); 6794 pIfR3->pDrvMount = PDMIBASE_QUERY_INTERFACE(pIfR3->pDrvBase, PDMIMOUNT); 6795 pIf->fPresent = true; 6582 6796 6583 6797 /* 6584 6798 * Validate type. 6585 6799 */ 6586 PDMMEDIATYPE enmType = pIf ->pDrvMedia->pfnGetType(pIf->pDrvMedia);6800 PDMMEDIATYPE enmType = pIfR3->pDrvMedia->pfnGetType(pIfR3->pDrvMedia); 6587 6801 if ( enmType != PDMMEDIATYPE_CDROM 6588 6802 && enmType != PDMMEDIATYPE_DVD … … 6594 6808 if ( ( enmType == PDMMEDIATYPE_DVD 6595 6809 || enmType == PDMMEDIATYPE_CDROM) 6596 && !pIf ->pDrvMount)6810 && !pIfR3->pDrvMount) 6597 6811 { 6598 6812 AssertMsgFailed(("Internal error: cdrom without a mountable interface, WTF???!\n")); … … 6600 6814 } 6601 6815 pIf->fATAPI = enmType == PDMMEDIATYPE_DVD || enmType == PDMMEDIATYPE_CDROM; 6602 pIf->fATAPIPassthrough = pIf->fATAPI && pIf ->pDrvMedia->pfnSendCmd != NULL;6816 pIf->fATAPIPassthrough = pIf->fATAPI && pIfR3->pDrvMedia->pfnSendCmd != NULL; 6603 6817 6604 6818 /* … … 6609 6823 else 6610 6824 { 6611 pIf->cbSector = pIf ->pDrvMedia->pfnGetSectorSize(pIf->pDrvMedia);6825 pIf->cbSector = pIfR3->pDrvMedia->pfnGetSectorSize(pIfR3->pDrvMedia); 6612 6826 AssertLogRelMsgReturn(pIf->cbSector > 0 && pIf->cbSector <= ATA_MAX_SECTOR_SIZE, 6613 6827 ("Unsupported sector size on LUN#%u: %#x (%d)\n", pIf->iLUN, pIf->cbSector, pIf->cbSector), … … 6641 6855 */ 6642 6856 int rc = VINF_SUCCESS; 6643 uint32_t cRegions = pIf ->pDrvMedia->pfnGetRegionCount(pIf->pDrvMedia);6857 uint32_t cRegions = pIfR3->pDrvMedia->pfnGetRegionCount(pIfR3->pDrvMedia); 6644 6858 pIf->cTotalSectors = 0; 6645 6859 for (uint32_t i = 0; i < cRegions; i++) 6646 6860 { 6647 6861 uint64_t cBlocks = 0; 6648 rc = pIf->pDrvMedia->pfnQueryRegionProperties(pIf->pDrvMedia, i, NULL, &cBlocks, 6649 NULL, NULL); 6862 rc = pIfR3->pDrvMedia->pfnQueryRegionProperties(pIfR3->pDrvMedia, i, NULL, &cBlocks, NULL, NULL); 6650 6863 AssertRC(rc); 6651 6864 pIf->cTotalSectors += cBlocks; … … 6662 6875 else 6663 6876 { 6664 rc = pIf ->pDrvMedia->pfnBiosGetPCHSGeometry(pIf->pDrvMedia, &pIf->PCHSGeometry);6877 rc = pIfR3->pDrvMedia->pfnBiosGetPCHSGeometry(pIfR3->pDrvMedia, &pIf->PCHSGeometry); 6665 6878 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED) 6666 6879 { … … 6686 6899 pIf->PCHSGeometry.cSectors = 63; 6687 6900 /* Set the disk geometry information. Ignore errors. */ 6688 pIf ->pDrvMedia->pfnBiosSetPCHSGeometry(pIf->pDrvMedia, &pIf->PCHSGeometry);6901 pIfR3->pDrvMedia->pfnBiosSetPCHSGeometry(pIfR3->pDrvMedia, &pIf->PCHSGeometry); 6689 6902 rc = VINF_SUCCESS; 6690 6903 } … … 6693 6906 pIf->cTotalSectors)); 6694 6907 6695 if (pIf ->pDrvMedia->pfnDiscard)6908 if (pIfR3->pDrvMedia->pfnDiscard) 6696 6909 LogRel(("PIIX3 ATA: LUN#%d: TRIM enabled\n", pIf->iLUN)); 6697 6910 } … … 6744 6957 static DECLCALLBACK(int) ataR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags) 6745 6958 { 6746 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 6747 PATACONTROLLER pCtl; 6748 ATADevState *pIf; 6749 int rc; 6750 unsigned iController; 6751 unsigned iInterface; 6959 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 6960 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 6752 6961 6753 6962 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG, … … 6758 6967 * Locate the controller and stuff. 6759 6968 */ 6760 iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);6969 unsigned const iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs); 6761 6970 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN)); 6762 pCtl = &pThis->aCts[iController]; 6763 6764 iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs); 6765 pIf = &pCtl->aIfs[iInterface]; 6971 PATACONTROLLER pCtl = &pThis->aCts[iController]; 6972 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[iController]; 6973 6974 unsigned const iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs); 6975 PATADEVSTATE pIf = &pCtl->aIfs[iInterface]; 6976 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[iInterface]; 6766 6977 6767 6978 /* the usual paranoia */ 6768 AssertRelease(!pIf->pDrvBase); 6769 AssertRelease(!pIf->pDrvMedia); 6770 Assert(ATADEVSTATE_2_CONTROLLER(pIf) == pCtl); 6979 AssertRelease(!pIfR3->pDrvBase); 6980 AssertRelease(!pIfR3->pDrvMedia); 6771 6981 Assert(pIf->iLUN == iLUN); 6772 6982 … … 6775 6985 * required as well as optional. 6776 6986 */ 6777 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, NULL);6987 int rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIfR3->IBase, &pIfR3->pDrvBase, NULL); 6778 6988 if (RT_SUCCESS(rc)) 6779 6989 { 6780 rc = ataR3ConfigLun(pIf );6990 rc = ataR3ConfigLun(pIf, pIfR3); 6781 6991 /* 6782 6992 * In case there is a medium inserted. … … 6790 7000 if (RT_FAILURE(rc)) 6791 7001 { 6792 pIf->pDrvBase = NULL; 6793 pIf->pDrvMedia = NULL; 7002 pIfR3->pDrvBase = NULL; 7003 pIfR3->pDrvMedia = NULL; 7004 pIfR3->pDrvMount = NULL; 7005 pIf->fPresent = false; 6794 7006 } 6795 7007 return rc; … … 6805 7017 static DECLCALLBACK(void) ataR3Resume(PPDMDEVINS pDevIns) 6806 7018 { 6807 P CIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);6808 int rc;7019 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7020 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 6809 7021 6810 7022 Log(("%s:\n", __FUNCTION__)); … … 6813 7025 if (pThis->aCts[i].fRedo && pThis->aCts[i].fRedoIdle) 6814 7026 { 6815 rc = RTSemEventSignal(pThis->aCts[i].SuspendIOSem);7027 int rc = RTSemEventSignal(pThisCC->aCts[i].hSuspendIOSem); 6816 7028 AssertRC(rc); 6817 7029 } … … 6830 7042 static bool ataR3AllAsyncIOIsIdle(PPDMDEVINS pDevIns) 6831 7043 { 6832 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7044 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7045 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 6833 7046 6834 7047 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 6835 if (pThis ->aCts[i].AsyncIOThread != NIL_RTTHREAD)6836 { 6837 bool fRc = ataR3AsyncIOIsIdle( &pThis->aCts[i], false /*fStrict*/);7048 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD) 7049 { 7050 bool fRc = ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/); 6838 7051 if (!fRc) 6839 7052 { 6840 7053 /* Make it signal PDM & itself when its done */ 6841 7054 PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED); 6842 ASMAtomicWriteBool(&pThis ->aCts[i].fSignalIdle, true);7055 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, true); 6843 7056 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].AsyncIORequestLock); 6844 7057 6845 fRc = ataR3AsyncIOIsIdle( &pThis->aCts[i], false /*fStrict*/);7058 fRc = ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/); 6846 7059 if (!fRc) 6847 7060 { … … 6854 7067 } 6855 7068 } 6856 ASMAtomicWriteBool(&pThis ->aCts[i].fSignalIdle, false);7069 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, false); 6857 7070 } 6858 7071 return true; … … 6868 7081 static DECLCALLBACK(int) ataR3SaveLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 6869 7082 { 6870 RT_NOREF 1(pSSM);7083 RT_NOREF(pSSM); 6871 7084 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 6872 7085 6873 7086 /* sanity - the suspend notification will wait on the async stuff. */ 6874 7087 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 6875 AssertLogRelMsgReturn(ataR3AsyncIOIsIdle( &pThis->aCts[i], false /*fStrict*/),7088 AssertLogRelMsgReturn(ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/), 6876 7089 ("i=%u\n", i), 6877 7090 VERR_SSM_IDE_ASYNC_TIMEOUT); … … 6884 7097 static DECLCALLBACK(int) ataR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass) 6885 7098 { 6886 RT_NOREF1(uPass); 6887 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 6888 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7099 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7100 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 7101 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7102 RT_NOREF(uPass); 6889 7103 6890 7104 pHlp->pfnSSMPutU8(pSSM, pThis->u8Type); … … 6894 7108 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++) 6895 7109 { 6896 pHlp->pfnSSMPutBool(pSSM, pThis ->aCts[i].aIfs[j].pDrvBase != NULL);7110 pHlp->pfnSSMPutBool(pSSM, pThisCC->aCts[i].aIfs[j].pDrvBase != NULL); 6897 7111 pHlp->pfnSSMPutStrZ(pSSM, pThis->aCts[i].aIfs[j].szSerialNumber); 6898 7112 pHlp->pfnSSMPutStrZ(pSSM, pThis->aCts[i].aIfs[j].szFirmwareRevision); … … 6909 7123 static DECLCALLBACK(int) ataR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 6910 7124 { 6911 P CIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);7125 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 6912 7126 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 6913 7127 … … 7004 7218 static DECLCALLBACK(int) ataR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 7005 7219 { 7006 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7007 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7220 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7221 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 7222 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7008 7223 int rc; 7009 7224 uint32_t u32; … … 7040 7255 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++) 7041 7256 { 7042 ATADevState const *pIf = &pThis->aCts[i].aIfs[j]; 7257 ATADEVSTATE const *pIf = &pThis->aCts[i].aIfs[j]; 7258 ATADEVSTATER3 const *pIfR3 = &pThisCC->aCts[i].aIfs[j]; 7043 7259 7044 7260 bool fInUse; 7045 7261 rc = pHlp->pfnSSMGetBool(pSSM, &fInUse); 7046 7262 AssertRCReturn(rc, rc); 7047 if (fInUse != (pIf ->pDrvBase != NULL))7263 if (fInUse != (pIfR3->pDrvBase != NULL)) 7048 7264 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, 7049 7265 N_("The %s VM is missing a %s device. Please make sure the source and target VMs have compatible storage configurations"), … … 7082 7298 { 7083 7299 /* integrity check */ 7084 if (!ataR3AsyncIOIsIdle( &pThis->aCts[i], false))7300 if (!ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false)) 7085 7301 { 7086 7302 AssertMsgFailed(("Async I/O for controller %d is active\n", i)); … … 7291 7507 PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].lock, VERR_INTERNAL_ERROR); 7292 7508 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++) 7293 ataR3ResetDevice( &pThis->aCts[i].aIfs[j]);7509 ataR3ResetDevice(pDevIns, &pThis->aCts[i], &pThis->aCts[i].aIfs[j]); 7294 7510 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].lock); 7295 7511 } … … 7307 7523 static int ataR3ResetCommon(PPDMDEVINS pDevIns, bool fConstruct) 7308 7524 { 7309 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7525 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7526 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 7310 7527 7311 7528 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) … … 7319 7536 * pretends that there is a BIOS that has set it up. Normal reset 7320 7537 * default is 0x00. */ 7321 pThis->aCts[i].BmDma.u8Status = (pThis->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)7322 | (pThis->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);7538 pThis->aCts[i].BmDma.u8Status = (pThisCC->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0) 7539 | (pThisCC->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0); 7323 7540 pThis->aCts[i].BmDma.GCPhysAddr = 0; 7324 7541 … … 7326 7543 pThis->aCts[i].fRedo = false; 7327 7544 pThis->aCts[i].fRedoIdle = false; 7328 ataR3AsyncIOClearRequests( &pThis->aCts[i]);7545 ataR3AsyncIOClearRequests(pDevIns, &pThis->aCts[i]); 7329 7546 Log2(("%s: Ctl#%d: message to async I/O thread, reset controller\n", __FUNCTION__, i)); 7330 ataHCAsyncIOPutRequest( &pThis->aCts[i], &g_ataResetARequest);7331 ataHCAsyncIOPutRequest( &pThis->aCts[i], &g_ataResetCRequest);7547 ataHCAsyncIOPutRequest(pDevIns, &pThis->aCts[i], &g_ataResetARequest); 7548 ataHCAsyncIOPutRequest(pDevIns, &pThis->aCts[i], &g_ataResetCRequest); 7332 7549 7333 7550 PDMDevHlpCritSectLeave(pDevIns, &pThis->aCts[i].lock); … … 7355 7572 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7356 7573 { 7357 if (pThis ->aCts[i].AsyncIOThread != NIL_RTTHREAD)7574 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD) 7358 7575 { 7359 7576 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED); 7360 7577 AssertRC(rc); 7361 7578 7362 ASMAtomicWriteBool(&pThis ->aCts[i].fSignalIdle, true);7363 rc = RTThreadUserReset(pThis ->aCts[i].AsyncIOThread);7579 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, true); 7580 rc = RTThreadUserReset(pThisCC->aCts[i].hAsyncIOThread); 7364 7581 AssertRC(rc); 7365 7582 … … 7367 7584 AssertRC(rc); 7368 7585 7369 if (!ataR3AsyncIOIsIdle( &pThis->aCts[i], false /*fStrict*/))7586 if (!ataR3AsyncIOIsIdle(pDevIns, &pThis->aCts[i], false /*fStrict*/)) 7370 7587 { 7371 rc = RTThreadUserWait(pThis ->aCts[i].AsyncIOThread, 30*1000 /*ms*/);7588 rc = RTThreadUserWait(pThisCC->aCts[i].hAsyncIOThread, 30*1000 /*ms*/); 7372 7589 if (RT_FAILURE(rc)) 7373 rc = RTThreadUserWait(pThis ->aCts[i].AsyncIOThread, 1000 /*ms*/);7590 rc = RTThreadUserWait(pThisCC->aCts[i].hAsyncIOThread, 1000 /*ms*/); 7374 7591 if (RT_FAILURE(rc)) 7375 7592 { … … 7379 7596 } 7380 7597 } 7381 ASMAtomicWriteBool(&pThis ->aCts[i].fSignalIdle, false);7598 ASMAtomicWriteBool(&pThisCC->aCts[i].fSignalIdle, false); 7382 7599 } 7383 7600 if (RT_SUCCESS(rcRet)) … … 7398 7615 { 7399 7616 ataR3ResetCommon(pDevIns, false /*fConstruct*/); 7400 }7401 7402 /**7403 * @copydoc FNPDMDEVRELOCATE7404 */7405 static DECLCALLBACK(void) ataR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)7406 {7407 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);7408 7409 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)7410 {7411 pThis->aCts[i].pDevInsRC += offDelta;7412 pThis->aCts[i].aIfs[0].pDevInsRC += offDelta;7413 pThis->aCts[i].aIfs[0].pControllerRC += offDelta;7414 pThis->aCts[i].aIfs[1].pDevInsRC += offDelta;7415 pThis->aCts[i].aIfs[1].pControllerRC += offDelta;7416 }7417 7617 } 7418 7618 … … 7428 7628 { 7429 7629 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); 7430 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7630 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7631 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATECC); 7431 7632 int rc; 7432 7633 … … 7438 7639 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7439 7640 { 7440 if (pThis ->aCts[i].AsyncIOThread != NIL_RTTHREAD)7441 { 7442 ASMAtomicWriteU32(&pThis ->aCts[i].fShutdown, true);7641 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD) 7642 { 7643 ASMAtomicWriteU32(&pThisCC->aCts[i].fShutdown, true); 7443 7644 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->aCts[i].hAsyncIOSem); 7444 7645 AssertRC(rc); 7445 rc = RTSemEventSignal(pThis ->aCts[i].SuspendIOSem);7646 rc = RTSemEventSignal(pThisCC->aCts[i].hSuspendIOSem); 7446 7647 AssertRC(rc); 7447 7648 } … … 7453 7654 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7454 7655 { 7455 if (pThis ->aCts[i].AsyncIOThread != NIL_RTTHREAD)7456 { 7457 rc = RTThreadWait(pThis ->aCts[i].AsyncIOThread, 30000 /* 30 s*/, NULL);7656 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD) 7657 { 7658 rc = RTThreadWait(pThisCC->aCts[i].hAsyncIOThread, 30000 /* 30 s*/, NULL); 7458 7659 if (RT_SUCCESS(rc)) 7459 pThis ->aCts[i].AsyncIOThread = NIL_RTTHREAD;7660 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD; 7460 7661 else 7461 7662 LogRel(("PIIX3 ATA Dtor: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x rc=%Rrc\n", … … 7477 7678 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT; 7478 7679 } 7479 if (pThis ->aCts[i].SuspendIOSem != NIL_RTSEMEVENT)7480 { 7481 RTSemEventDestroy(pThis ->aCts[i].SuspendIOSem);7482 pThis ->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;7680 if (pThisCC->aCts[i].hSuspendIOSem != NIL_RTSEMEVENT) 7681 { 7682 RTSemEventDestroy(pThisCC->aCts[i].hSuspendIOSem); 7683 pThisCC->aCts[i].hSuspendIOSem = NIL_RTSEMEVENT; 7483 7684 } 7484 7685 7485 7686 /* try one final time */ 7486 if (pThis ->aCts[i].AsyncIOThread != NIL_RTTHREAD)7487 { 7488 rc = RTThreadWait(pThis ->aCts[i].AsyncIOThread, 1 /*ms*/, NULL);7687 if (pThisCC->aCts[i].hAsyncIOThread != NIL_RTTHREAD) 7688 { 7689 rc = RTThreadWait(pThisCC->aCts[i].hAsyncIOThread, 1 /*ms*/, NULL); 7489 7690 if (RT_SUCCESS(rc)) 7490 7691 { 7491 pThis ->aCts[i].AsyncIOThread = NIL_RTTHREAD;7692 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD; 7492 7693 LogRel(("PIIX3 ATA Dtor: Ctl#%u actually completed.\n", i)); 7493 7694 } … … 7496 7697 for (uint32_t iIf = 0; iIf < RT_ELEMENTS(pThis->aCts[i].aIfs); iIf++) 7497 7698 { 7498 if (pThis ->aCts[i].aIfs[iIf].pTrackList)7699 if (pThisCC->aCts[i].aIfs[iIf].pTrackList) 7499 7700 { 7500 ATAPIPassthroughTrackListDestroy(pThis ->aCts[i].aIfs[iIf].pTrackList);7501 pThis ->aCts[i].aIfs[iIf].pTrackList = NULL;7701 ATAPIPassthroughTrackListDestroy(pThisCC->aCts[i].aIfs[iIf].pTrackList); 7702 pThisCC->aCts[i].aIfs[iIf].pTrackList = NULL; 7502 7703 } 7503 7704 } … … 7545 7746 { 7546 7747 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 7547 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7548 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7748 PATASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PATASTATE); 7749 PATASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PATASTATER3); 7750 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7549 7751 PPDMIBASE pBase; 7550 7752 int rc; … … 7558 7760 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7559 7761 { 7762 pThis->aCts[i].iCtl = i; 7560 7763 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT; 7561 pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;7562 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;7563 7764 pThis->aCts[i].hIoPorts1First = NIL_IOMIOPORTHANDLE; 7564 7765 pThis->aCts[i].hIoPorts1Other = NIL_IOMIOPORTHANDLE; … … 7566 7767 pThis->aCts[i].hIoPortsEmpty1 = NIL_IOMIOPORTHANDLE; 7567 7768 pThis->aCts[i].hIoPortsEmpty2 = NIL_IOMIOPORTHANDLE; 7769 7770 pThisCC->aCts[i].iCtl = i; 7771 pThisCC->aCts[i].hSuspendIOSem = NIL_RTSEMEVENT; 7772 pThisCC->aCts[i].hAsyncIOThread = NIL_RTTHREAD; 7568 7773 } 7569 7774 … … 7589 7794 */ 7590 7795 /* Status LUN. */ 7591 pThis ->IBase.pfnQueryInterface = ataR3Status_QueryInterface;7592 pThis ->ILeds.pfnQueryStatusLed = ataR3Status_QueryStatusLed;7796 pThisCC->IBase.pfnQueryInterface = ataR3Status_QueryInterface; 7797 pThisCC->ILeds.pfnQueryStatusLed = ataR3Status_QueryStatusLed; 7593 7798 7594 7799 /* PCI configuration space. */ … … 7654 7859 PDMPciDevSetHeaderType(pPciDev, 0x00); 7655 7860 7656 pThis->pDevIns = pDevIns; 7657 pThis->fRCEnabled = pDevIns->fRCEnabled; 7658 pThis->fR0Enabled = pDevIns->fR0Enabled; 7861 pThisCC->pDevIns = pDevIns; 7659 7862 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7660 7863 { 7661 pThis ->aCts[i].pDevInsR3= pDevIns;7662 pThis ->aCts[i].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);7663 pThis->aCts[i]. pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);7664 pThis->aCts[i].msDelayIRQ = msDelayIRQ;7864 pThisCC->aCts[i].pDevIns = pDevIns; 7865 pThisCC->aCts[i].iCtl = i; 7866 pThis->aCts[i].iCtl = i; 7867 pThis->aCts[i].msDelayIRQ = msDelayIRQ; 7665 7868 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++) 7666 7869 { 7667 ATADevState *pIf = &pThis->aCts[i].aIfs[j]; 7668 7669 pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j; 7670 pIf->pDevInsR3 = pDevIns; 7671 pIf->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 7672 pIf->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 7673 pIf->pControllerR3 = &pThis->aCts[i]; 7674 pIf->pControllerR0 = PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, &pThis->aCts[i]); 7675 pIf->pControllerRC = PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, &pThis->aCts[i]); 7676 pIf->IBase.pfnQueryInterface = ataR3QueryInterface; 7677 pIf->IMountNotify.pfnMountNotify = ataR3MountNotify; 7678 pIf->IMountNotify.pfnUnmountNotify = ataR3UnmountNotify; 7679 pIf->IPort.pfnQueryDeviceLocation = ataR3QueryDeviceLocation; 7680 pIf->Led.u32Magic = PDMLED_MAGIC; 7870 PATADEVSTATE pIf = &pThis->aCts[i].aIfs[j]; 7871 PATADEVSTATER3 pIfR3 = &pThisCC->aCts[i].aIfs[j]; 7872 7873 pIfR3->iLUN = pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j; 7874 pIfR3->iCtl = pIf->iCtl = i; 7875 pIfR3->iDev = pIf->iDev = j; 7876 pIfR3->pDevIns = pDevIns; 7877 pIfR3->IBase.pfnQueryInterface = ataR3QueryInterface; 7878 pIfR3->IMountNotify.pfnMountNotify = ataR3MountNotify; 7879 pIfR3->IMountNotify.pfnUnmountNotify = ataR3UnmountNotify; 7880 pIfR3->IPort.pfnQueryDeviceLocation = ataR3QueryDeviceLocation; 7881 pIf->Led.u32Magic = PDMLED_MAGIC; 7681 7882 } 7682 7883 } … … 7776 7977 * Attach status driver (optional). 7777 7978 */ 7778 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis ->IBase, &pBase, "Status Port");7979 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port"); 7779 7980 if (RT_SUCCESS(rc)) 7780 7981 { 7781 pThis ->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);7782 pThis ->pMediaNotify= PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);7982 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS); 7983 pThisCC->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY); 7783 7984 } 7784 7985 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER) … … 7794 7995 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7795 7996 { 7796 PATACONTROLLER pCtl = &pThis->aCts[i]; 7997 PATACONTROLLER pCtl = &pThis->aCts[i]; 7998 PATACONTROLLERR3 pCtlR3 = &pThisCC->aCts[i]; 7797 7999 7798 8000 /* … … 7802 8004 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pCtl->hAsyncIOSem); 7803 8005 AssertLogRelRCReturn(rc, rc); 7804 rc = RTSemEventCreate(&pCtl ->SuspendIOSem);8006 rc = RTSemEventCreate(&pCtlR3->hSuspendIOSem); 7805 8007 AssertLogRelRCReturn(rc, rc); 7806 8008 7807 ataR3AsyncIOClearRequests(p Ctl);7808 rc = RTThreadCreateF(&pCtl ->AsyncIOThread, ataR3AsyncIOThread, (void *)pCtl, 128*1024 /*cbStack*/,8009 ataR3AsyncIOClearRequests(pDevIns, pCtl); 8010 rc = RTThreadCreateF(&pCtlR3->hAsyncIOThread, ataR3AsyncIOThread, pCtlR3, 0, 7809 8011 RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ATA-%u", i); 7810 8012 AssertLogRelRCReturn(rc, rc); 7811 Assert( pCtl ->AsyncIOThread != NIL_RTTHREAD&& pCtl->hAsyncIOSem != NIL_SUPSEMEVENT7812 && pCtl ->SuspendIOSem != NIL_RTSEMEVENT && PDMDevHlpCritSectIsInitialized(pDevIns, &pCtl->AsyncIORequestLock));7813 Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p\n", __FUNCTION__, i, pCtl ->AsyncIOThread, pCtl->hAsyncIOSem, pCtl->SuspendIOSem));8013 Assert( pCtlR3->hAsyncIOThread != NIL_RTTHREAD && pCtl->hAsyncIOSem != NIL_SUPSEMEVENT 8014 && pCtlR3->hSuspendIOSem != NIL_RTSEMEVENT && PDMDevHlpCritSectIsInitialized(pDevIns, &pCtl->AsyncIORequestLock)); 8015 Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p\n", __FUNCTION__, i, pCtlR3->hAsyncIOThread, pCtl->hAsyncIOSem, pCtlR3->hSuspendIOSem)); 7814 8016 7815 8017 for (uint32_t j = 0; j < RT_ELEMENTS(pCtl->aIfs); j++) … … 7825 8027 * required as well as optional. 7826 8028 */ 7827 ATADevState *pIf = &pCtl->aIfs[j]; 7828 7829 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, s_apszDescs[i][j]); 8029 PATADEVSTATE pIf = &pCtl->aIfs[j]; 8030 PATADEVSTATER3 pIfR3 = &pCtlR3->aIfs[j]; 8031 8032 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIfR3->IBase, &pIfR3->pDrvBase, s_apszDescs[i][j]); 7830 8033 if (RT_SUCCESS(rc)) 7831 8034 { 7832 rc = ataR3ConfigLun(pIf );8035 rc = ataR3ConfigLun(pIf, pIfR3); 7833 8036 if (RT_SUCCESS(rc)) 7834 8037 { … … 7845 8048 char szSerial[ATA_SERIAL_NUMBER_LENGTH+1]; 7846 8049 RTUUID Uuid; 7847 if (pIf ->pDrvMedia)7848 rc = pIf ->pDrvMedia->pfnGetUuid(pIf->pDrvMedia, &Uuid);8050 if (pIfR3->pDrvMedia) 8051 rc = pIfR3->pDrvMedia->pfnGetUuid(pIfR3->pDrvMedia, &Uuid); 7849 8052 else 7850 8053 RTUuidClear(&Uuid); … … 7937 8140 } 7938 8141 } 7939 7940 8142 } 7941 8143 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER) 7942 8144 { 7943 pIf->pDrvBase = NULL; 7944 pIf->pDrvMedia = NULL; 7945 pIf->cbIOBuffer = 0; 8145 pIfR3->pDrvBase = NULL; 8146 pIfR3->pDrvMedia = NULL; 8147 pIf->cbIOBuffer = 0; 8148 pIf->fPresent = false; 7946 8149 LogRel(("PIIX3 ATA: LUN#%d: no unit\n", pIf->iLUN)); 7947 8150 } … … 7969 8172 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7970 8173 { 7971 if (!pThis->aCts[i].aIfs[0].pDrvMedia && !pThis->aCts[i].aIfs[1].pDrvMedia) 8174 Assert(pThis->aCts[i].aIfs[0].fPresent == (pThisCC->aCts[i].aIfs[0].pDrvMedia != NULL)); 8175 Assert(pThis->aCts[i].aIfs[1].fPresent == (pThisCC->aCts[i].aIfs[1].pDrvMedia != NULL)); 8176 8177 if (!pThisCC->aCts[i].aIfs[0].pDrvMedia && !pThisCC->aCts[i].aIfs[1].pDrvMedia) 7972 8178 { 7973 8179 /* No device present on this ATA bus; requires special handling. */ … … 8025 8231 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 8026 8232 8027 int rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsBmDma, ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL /*pvUser*/); 8233 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns)); 8234 AssertRCReturn(rc, rc); 8235 8236 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsBmDma, ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL /*pvUser*/); 8028 8237 AssertRCReturn(rc, rc); 8029 8238 … … 8069 8278 /* .uReserved0 = */ 0, 8070 8279 /* .szName = */ "piix3ide", 8071 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | 8072 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |8073 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,8280 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE 8281 | PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION 8282 | PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION, 8074 8283 /* .fClass = */ PDM_DEVREG_CLASS_STORAGE, 8075 8284 /* .cMaxInstances = */ 1, 8076 8285 /* .uSharedVersion = */ 42, 8077 /* .cbInstanceShared = */ sizeof( PCIATAState),8078 /* .cbInstanceCC = */ 0,8079 /* .cbInstanceRC = */ 0,8286 /* .cbInstanceShared = */ sizeof(ATASTATE), 8287 /* .cbInstanceCC = */ sizeof(ATASTATECC), 8288 /* .cbInstanceRC = */ sizeof(ATASTATERC), 8080 8289 /* .cMaxPciDevices = */ 1, 8081 8290 /* .cMaxMsixVectors = */ 0, … … 8091 8300 /* .pfnConstruct = */ ataR3Construct, 8092 8301 /* .pfnDestruct = */ ataR3Destruct, 8093 /* .pfnRelocate = */ ataR3Relocate,8302 /* .pfnRelocate = */ NULL, 8094 8303 /* .pfnMemSetup = */ NULL, 8095 8304 /* .pfnPowerOn = */ NULL,
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