VirtualBox

Changeset 81986 in vbox for trunk/src/VBox/Devices


Ignore:
Timestamp:
Nov 19, 2019 11:15:22 AM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134785
Message:

DevDMA: Brushed up the logging and added 'R3' to the ring-3 functions. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/PC/DevDMA.cpp

    r81985 r81986  
    260260static DECLCALLBACK(VBOXSTRICTRC) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    261261{
     262    PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
    262263    RT_NOREF(pDevIns);
    263264    if (cb == 1)
    264265    {
    265         PDMACONTROLLER dc       = (PDMACONTROLLER)pvUser;
    266266        unsigned const reg      = (offPort >> dc->is16bit) & 0x0f;
    267267        unsigned const chidx    = reg >> 1;
    … …  
    289289                ch->u16BaseAddr  = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
    290290        }
    291         Log2(("dmaWriteAddr: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
     291        Log2(("dmaWriteAddr/%u: offPort %#06x, chidx %d, data %#02x\n", dc->is16bit, offPort, chidx, u32));
    292292    }
    293293    else
    294294    {
    295295        /* Likely a guest bug. */
    296         Log(("Bad size write to count register %#x (size %d, data %#x)\n", offPort, cb, u32));
     296        Log(("dmaWriteAddr/%u: Bad size write to count register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
    297297    }
    298298    return VINF_SUCCESS;
    … …  
    324324        *pu32 = RT_LOBYTE(val >> (bptr * 8));
    325325
    326         Log(("Count read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
     326        Log(("dmaReadAddr/%u: Count read: offPort %#06x, reg %#04x, data %#x\n", dc->is16bit, offPort, reg, val));
    327327        return VINF_SUCCESS;
    328328    }
    … …  
    337337static DECLCALLBACK(VBOXSTRICTRC) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    338338{
     339    PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
    339340    RT_NOREF(pDevIns);
    340341    if (cb == 1)
    341342    {
    342         PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
    343343        unsigned       chidx = 0;
    344 
    345344        unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
    346345        Assert((int)reg >= CTL_W_CMD && reg <= CTL_W_MASK);
    … …  
    352351            if (u32 & CMD_UNSUPPORTED)
    353352            {
    354                 Log(("DMA command %#x is not supported, ignoring!\n", u32));
     353                Log(("dmaWriteCtl/%u: DMA command %#x is not supported, ignoring!\n", dc->is16bit, u32));
    355354                break;
    356355            }
    … …  
    375374            chidx = u32 & 3;
    376375            dc->ChState[chidx].u8Mode = u32;
    377             Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
     376            Log2(("dmaWriteCtl/%u: chidx %d, op %d, %sauto-init, %screment, opmode %d\n", dc->is16bit,
    378377                  chidx, (u32 >> 2) & 3, IS_MODE_AI(u32) ? "" : "no ", IS_MODE_DEC(u32) ? "de" : "in", (u32 >> 6) & 3));
    379378            break;
    … …  
    394393            break;
    395394        }
    396         Log(("dmaWriteCtl: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
     395        Log(("dmaWriteCtl/%u: offPort %#06x, chidx %d, data %#02x\n", dc->is16bit, offPort, chidx, u32));
    397396    }
    398397    else
    399398    {
    400399        /* Likely a guest bug. */
    401         Log(("Bad size write to controller register %#x (size %d, data %#x)\n", offPort, cb, u32));
     400        Log(("dmaWriteCtl/%u: Bad size write to controller register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
    402401    }
    403402    return VINF_SUCCESS;
    … …  
    452451        }
    453452
    454         Log(("Ctrl read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
     453        Log(("dmaReadCtl/%u: Ctrl read: offPort %#06x, reg %#04x, data %#x\n", dc->is16bit, offPort, reg, val));
    455454        *pu32 = val;
    456455
    … …  
    481480        reg   = offPort & 7;
    482481        *pu32 = dc->au8Page[reg];
    483         Log2(("Read %#x (byte) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
     482        Log2(("dmaReadPage/%u: Read %#x (byte) from page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
    484483        return VINF_SUCCESS;
    485484    }
    … …  
    489488        reg   = offPort & 7;
    490489        *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
    491         Log2(("Read %#x (word) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
     490        Log2(("dmaReadPage/%u: Read %#x (word) from page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
    492491        return VINF_SUCCESS;
    493492    }
    … …  
    513512        dc->au8Page[reg]   = u32;
    514513        dc->au8PageHi[reg] = 0;  /* Corresponding high page cleared. */
    515         Log2(("Wrote %#x to page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
     514        Log2(("dmaWritePage/%u: Wrote %#x to page register %#x (channel %d)\n", dc->is16bit, u32, offPort, DMAPG2CX(reg)));
    516515    }
    517516    else if (cb == 2)
    … …  
    528527    {
    529528        /* Likely a guest bug. */
    530         Log(("Bad size write to page register %#x (size %d, data %#x)\n", offPort, cb, u32));
     529        Log(("dmaWritePage/%u: Bad size write to page register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
    531530    }
    532531    return VINF_SUCCESS;
    … …  
    548547
    549548        *pu32 = dc->au8PageHi[reg];
    550         Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
     549        Log2(("dmaReadHiPage/%u: Read %#x to from high page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
    551550        return VINF_SUCCESS;
    552551    }
    … …  
    561560{
    562561    RT_NOREF(pDevIns);
     562    PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
    563563    if (cb == 1)
    564564    {
    565         PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
    566565        unsigned const reg = offPort & 7;
    567566
    568567        Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
    569568        dc->au8PageHi[reg] = u32;
    570         Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
     569        Log2(("dmaWriteHiPage/%u: Wrote %#x to high page register %#x (channel %d)\n", dc->is16bit, u32, offPort, DMAPG2CX(reg)));
    571570    }
    572571    else
    573572    {
    574573        /* Likely a guest bug. */
    575         Log(("Bad size write to high page register %#x (size %d, data %#x)\n", offPort, cb, u32));
     574        Log(("Bad size write to high page register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
    576575    }
    577576    return VINF_SUCCESS;
    … …  
    620619 * @interface_method_impl{PDMDMAREG,pfnRun}
    621620 */
    622 static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
     621static DECLCALLBACK(bool) dmaR3Run(PPDMDEVINS pDevIns)
    623622{
    624623    DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    … …  
    653652 * @interface_method_impl{PDMDMAREG,pfnRegister}
    654653 */
    655 static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
    656                                       PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
     654static DECLCALLBACK(void) dmaR3Register(PPDMDEVINS pDevIns, unsigned uChannel,
     655                                        PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
    657656{
    658657    DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    659658    DMAChannel  *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
    660659
    661     LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
     660    LogFlow(("dmaR3Register: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
    662661
    663662    PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
    … …  
    704703 * @interface_method_impl{PDMDMAREG,pfnReadMemory}
    705704 */
    706 static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
    707                                             void *pvBuffer, uint32_t off, uint32_t cbBlock)
     705static DECLCALLBACK(uint32_t) dmaR3ReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
     706                                              void *pvBuffer, uint32_t off, uint32_t cbBlock)
    708707{
    709708    DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    … …  
    713712    uint32_t    addr;
    714713
    715     LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
     714    LogFlow(("dmaR3ReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
    716715
    717716    PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
    … …  
    740739 * @interface_method_impl{PDMDMAREG,pfnWriteMemory}
    741740 */
    742 static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
    743                                              const void *pvBuffer, uint32_t off, uint32_t cbBlock)
     741static DECLCALLBACK(uint32_t) dmaR3WriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
     742                                               const void *pvBuffer, uint32_t off, uint32_t cbBlock)
    744743{
    745744    DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    … …  
    749748    uint32_t    addr;
    750749
    751     LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
     750    LogFlow(("dmaR3WriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
    752751    if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
    753752    {
    … …  
    785784 * @interface_method_impl{PDMDMAREG,pfnSetDREQ}
    786785 */
    787 static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
     786static DECLCALLBACK(void) dmaR3SetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
    788787{
    789788    DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    … …  
    791790    int         chidx;
    792791
    793     LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
     792    LogFlow(("dmaR3SetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
    794793
    795794    PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
    … …  
    805804 * @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
    806805 */
    807 static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
     806static DECLCALLBACK(uint8_t) dmaR3GetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
    808807{
    809808    PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    810809
    811     LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
     810    LogFlow(("dmaR3GetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
    812811
    813812    PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
    … …  
    818817
    819818
    820 /**
    821  * @interface_method_impl{PDMDEVREG,pfnReset}
    822  */
    823 static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
    824 {
    825     PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    826 
    827     LogFlow(("dmaReset: pThis=%p\n", pThis));
    828 
    829     /* NB: The page and address registers are unaffected by a reset
    830      * and in an undefined state after power-up.
    831      */
    832     dmaClear(&pThis->DMAC[0]);
    833     dmaClear(&pThis->DMAC[1]);
    834 }
    835 
    836 static void dmaSaveController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc)
    837 {
    838     int         chidx;
    839 
     819static void dmaR3SaveController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc)
     820{
    840821    /* Save controller state... */
    841822    pHlp->pfnSSMPutU8(pSSM, dc->u8Command);
    … …  
    850831
    851832    /* ...and all four of its channels. */
    852     for (chidx = 0; chidx < 4; ++chidx)
     833    for (unsigned chidx = 0; chidx < RT_ELEMENTS(dc->ChState); ++chidx)
    853834    {
    854835        DMAChannel  *ch = &dc->ChState[chidx];
    … …  
    862843}
    863844
    864 static int dmaLoadController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc, int version)
     845static int dmaR3LoadController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc, int version)
    865846{
    866847    uint8_t     u8val;
    867848    uint32_t    u32val;
    868     int         chidx;
    869849
    870850    pHlp->pfnSSMGetU8(pSSM, &dc->u8Command);
    … …  
    882862    }
    883863
    884     for (chidx = 0; chidx < 4; ++chidx)
     864    for (unsigned chidx = 0; chidx < RT_ELEMENTS(dc->ChState); ++chidx)
    885865    {
    886866        DMAChannel  *ch = &dc->ChState[chidx];
    … …  
    919899
    920900/** @callback_method_impl{FNSSMDEVSAVEEXEC}  */
    921 static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
     901static DECLCALLBACK(int) dmaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    922902{
    923903    PDMASTATE       pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    924904    PCPDMDEVHLPR3   pHlp  = pDevIns->pHlpR3;
    925905
    926     dmaSaveController(pHlp, pSSM, &pThis->DMAC[0]);
    927     dmaSaveController(pHlp, pSSM, &pThis->DMAC[1]);
     906    dmaR3SaveController(pHlp, pSSM, &pThis->DMAC[0]);
     907    dmaR3SaveController(pHlp, pSSM, &pThis->DMAC[1]);
    928908    return VINF_SUCCESS;
    929909}
    930910
    931911/** @callback_method_impl{FNSSMDEVLOADEXEC}  */
    932 static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     912static DECLCALLBACK(int) dmaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    933913{
    934914    PDMASTATE       pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    … …  
    938918    Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
    939919
    940     dmaLoadController(pHlp, pSSM, &pThis->DMAC[0], uVersion);
    941     return dmaLoadController(pHlp, pSSM, &pThis->DMAC[1], uVersion);
     920    dmaR3LoadController(pHlp, pSSM, &pThis->DMAC[0], uVersion);
     921    return dmaR3LoadController(pHlp, pSSM, &pThis->DMAC[1], uVersion);
     922}
     923
     924/**
     925 * @interface_method_impl{PDMDEVREG,pfnReset}
     926 */
     927static DECLCALLBACK(void) dmaR3Reset(PPDMDEVINS pDevIns)
     928{
     929    PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
     930
     931    LogFlow(("dmaR3Reset: pThis=%p\n", pThis));
     932
     933    /* NB: The page and address registers are unaffected by a reset
     934     * and in an undefined state after power-up.
     935     */
     936    dmaClear(&pThis->DMAC[0]);
     937    dmaClear(&pThis->DMAC[1]);
    942938}
    943939
    … …  
    945941 * @interface_method_impl{PDMDEVREG,pfnConstruct}
    946942 */
    947 static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
     943static DECLCALLBACK(int) dmaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    948944{
    949945    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    … …  
    10091005     * Reset controller state.
    10101006     */
    1011     dmaReset(pDevIns);
     1007    dmaR3Reset(pDevIns);
    10121008
    10131009    /*
    … …  
    10161012    PDMDMACREG Reg;
    10171013    Reg.u32Version        = PDM_DMACREG_VERSION;
    1018     Reg.pfnRun            = dmaRun;
    1019     Reg.pfnRegister       = dmaRegister;
    1020     Reg.pfnReadMemory     = dmaReadMemory;
    1021     Reg.pfnWriteMemory    = dmaWriteMemory;
    1022     Reg.pfnSetDREQ        = dmaSetDREQ;
    1023     Reg.pfnGetChannelMode = dmaGetChannelMode;
     1014    Reg.pfnRun            = dmaR3Run;
     1015    Reg.pfnRegister       = dmaR3Register;
     1016    Reg.pfnReadMemory     = dmaR3ReadMemory;
     1017    Reg.pfnWriteMemory    = dmaR3WriteMemory;
     1018    Reg.pfnSetDREQ        = dmaR3SetDREQ;
     1019    Reg.pfnGetChannelMode = dmaR3GetChannelMode;
    10241020
    10251021    rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
    … …  
    10291025     * Register the saved state.
    10301026     */
    1031     rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
     1027    rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaR3SaveExec, dmaR3LoadExec);
    10321028    AssertRCReturn(rc, rc);
    10331029
    … …  
    10351031     * Statistics.
    10361032     */
    1037     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaRun().");
     1033    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaR3Run().");
    10381034
    10391035    return VINF_SUCCESS;
    … …  
    10971093    /* .pszRCMod = */               "VBoxDDRC.rc",
    10981094    /* .pszR0Mod = */               "VBoxDDR0.r0",
    1099     /* .pfnConstruct = */           dmaConstruct,
     1095    /* .pfnConstruct = */           dmaR3Construct,
    11001096    /* .pfnDestruct = */            NULL,
    11011097    /* .pfnRelocate = */            NULL,
    11021098    /* .pfnMemSetup = */            NULL,
    11031099    /* .pfnPowerOn = */             NULL,
    1104     /* .pfnReset = */               dmaReset,
     1100    /* .pfnReset = */               dmaR3Reset,
    11051101    /* .pfnSuspend = */             NULL,
    11061102    /* .pfnResume = */              NULL,
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