Changeset 81996 in vbox for trunk/src/VBox
- Timestamp:
- Nov 19, 2019 2:41:07 PM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevACPI.cpp
r81994 r81996 293 293 /** Number of logical CPUs in guest */ 294 294 uint16_t cCpus; 295 295 296 uint64_t u64PmTimerInitial; 296 PTMTIMERR3 pPmTimerR3; 297 PTMTIMERR0 pPmTimerR0; 298 PTMTIMERRC pPmTimerRC; 299 297 /** The PM timer. */ 298 TMTIMERHANDLE hPmTimer; 300 299 /* PM Timer last calculated value */ 301 300 uint32_t uPmTimerVal; … … 422 421 PPDMDEVINSR3 pDevIns; 423 422 424 /** Pointer to the device instance. */425 PPDMDEVINSR3 pDevInsR3;426 PPDMDEVINSR0 pDevInsR0;427 PPDMDEVINSRC pDevInsRC;428 429 uint32_t Alignment3;430 423 /** Pointer to the driver base interface. */ 431 424 R3PTRTYPE(PPDMIBASE) pDrvBase; … … 777 770 RT_C_DECLS_END 778 771 #ifdef IN_RING3 779 static int acpiR3PlantTables( ACPIState *pThis);772 static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis); 780 773 #endif 781 774 782 775 /* SCI, usually IRQ9 */ 783 DECLINLINE(void) acpiSetIrq( ACPIState *pThis, int level)784 { 785 PDMDevHlpPCISetIrq(p This->CTX_SUFF(pDevIns), 0, level);776 DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level) 777 { 778 PDMDevHlpPCISetIrq(pDevIns, 0, level); 786 779 } 787 780 … … 836 829 837 830 if (new_level != old_level) 838 acpiSetIrq(p This, new_level);831 acpiSetIrq(pDevIns, new_level); 839 832 } 840 833 … … 864 857 865 858 if (new_level != old_level) 866 acpiSetIrq(p This, new_level);859 acpiSetIrq(pDevIns, new_level); 867 860 } 868 861 … … 870 863 * Used by acpiR3PM1aCtlWrite to power off the VM. 871 864 * 865 * @param pDevIns The device instance. 866 * @returns Strict VBox status code. 867 */ 868 static int acpiR3DoPowerOff(PPDMDEVINS pDevIns) 869 { 870 int rc = PDMDevHlpVMPowerOff(pDevIns); 871 AssertRC(rc); 872 return rc; 873 } 874 875 /** 876 * Used by acpiR3PM1aCtlWrite to put the VM to sleep. 877 * 878 * @param pDevIns The device instance. 872 879 * @param pThis The ACPI shared instance data. 873 880 * @returns Strict VBox status code. 874 881 */ 875 static int acpiR3DoPowerOff(ACPIState *pThis) 876 { 877 int rc = PDMDevHlpVMPowerOff(pThis->pDevInsR3); 878 if (RT_FAILURE(rc)) 879 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc)); 880 return rc; 881 } 882 883 /** 884 * Used by acpiR3PM1aCtlWrite to put the VM to sleep. 885 * 886 * @param pThis The ACPI shared instance data. 887 * @returns Strict VBox status code. 888 */ 889 static int acpiR3DoSleep(ACPIState *pThis) 882 static int acpiR3DoSleep(PPDMDEVINS pDevIns, ACPIState *pThis) 890 883 { 891 884 /* We must set WAK_STS on resume (includes restore) so the guest knows that … … 896 889 if (pThis->fSuspendToSavedState) 897 890 { 898 rc = PDMDevHlpVMSuspendSaveAndPowerOff(p This->pDevInsR3);891 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns); 899 892 if (rc != VERR_NOT_SUPPORTED) 900 893 AssertRC(rc); … … 902 895 { 903 896 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n")); 904 rc = PDMDevHlpVMSuspend(p This->pDevInsR3);897 rc = PDMDevHlpVMSuspend(pDevIns); 905 898 AssertRC(rc); 906 899 } … … 908 901 else 909 902 { 910 rc = PDMDevHlpVMSuspend(p This->pDevInsR3);903 rc = PDMDevHlpVMSuspend(pDevIns); 911 904 AssertRC(rc); 912 905 } … … 1040 1033 * the VM is resetting or loading state. 1041 1034 * 1042 * @param pThis The ACPI shared instance data. 1043 * @param uNow The current time. 1044 */ 1045 static void acpiR3PmTimerReset(ACPIState *pThis, uint64_t uNow) 1046 { 1047 uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer)); 1035 * @param pDevIns The device instance. 1036 * @param pThis The ACPI shared instance data. 1037 * @param uNow The current time. 1038 */ 1039 static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, ACPIState *pThis, uint64_t uNow) 1040 { 1041 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer); 1048 1042 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1)); 1049 1043 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ); 1050 TMTimerSet(pThis->pPmTimerR3, uNow + uInterval + 1);1044 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1); 1051 1045 Log(("acpi: uInterval = %RU64\n", uInterval)); 1052 1046 } … … 1068 1062 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB; 1069 1063 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial; 1070 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPmTimer))); 1071 1072 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer))) & TMR_VAL_MASK; 1064 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer)); 1065 1066 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, 1067 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer)) 1068 & TMR_VAL_MASK; 1073 1069 1074 1070 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb) … … 1084 1080 { 1085 1081 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1086 Assert( TMTimerIsLockOwner(pTimer));1087 RT_NOREF(p vUser);1082 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer)); 1083 RT_NOREF(pTimer, pvUser); 1088 1084 1089 1085 DEVACPI_LOCK_R3(pDevIns, pThis); … … 1091 1087 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0, 1092 1088 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0)); 1093 uint64_t u64Now = TMTimerGet(pTimer);1089 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer); 1094 1090 acpiPmTimerUpdate(pDevIns, pThis, u64Now); 1095 1091 DEVACPI_UNLOCK(pDevIns, pThis); 1096 1092 1097 acpiR3PmTimerReset(p This, u64Now);1093 acpiR3PmTimerReset(pDevIns, pThis, u64Now); 1098 1094 } 1099 1095 … … 1693 1689 { 1694 1690 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n")); 1695 rc = acpiR3DoSleep(p This);1691 rc = acpiR3DoSleep(pDevIns, pThis); 1696 1692 break; 1697 1693 } … … 1703 1699 { 1704 1700 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n")); 1705 rc = acpiR3DoPowerOff(p This);/* Same behavior as S5 */1701 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */ 1706 1702 break; 1707 1703 } … … 1711 1707 case 0x05: /* S5 */ 1712 1708 LogRel(("ACPI: Entering S5 power state (power down)\n")); 1713 rc = acpiR3DoPowerOff(p This);1709 rc = acpiR3DoPowerOff(pDevIns); 1714 1710 break; 1715 1711 … … 1745 1741 */ 1746 1742 1747 int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_R3_IOPORT_READ); 1748 if (rc != VINF_SUCCESS) 1749 return rc; 1750 1751 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ); 1752 if (rc != VINF_SUCCESS) 1753 { 1754 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer)); 1755 return rc; 1756 } 1757 1758 uint64_t u64Now = TMTimerGet(pThis->CTX_SUFF(pPmTimer)); 1759 acpiPmTimerUpdate(pDevIns, pThis, u64Now); 1760 *pu32 = pThis->uPmTimerVal; 1761 1762 DEVACPI_UNLOCK(pDevIns, pThis); 1763 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer)); 1764 1765 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi"); 1766 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32)); 1743 int rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ); 1744 if (rc == VINF_SUCCESS) 1745 { 1746 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ); 1747 if (rc == VINF_SUCCESS) 1748 { 1749 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer); 1750 acpiPmTimerUpdate(pDevIns, pThis, u64Now); 1751 *pu32 = pThis->uPmTimerVal; 1752 1753 DEVACPI_UNLOCK(pDevIns, pThis); 1754 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 1755 1756 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi"); 1757 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32)); 1767 1758 1768 1759 #if 0 1769 /** @todo temporary: sanity check against running backwards */1770 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);1771 if (*pu32 - uOld >= 0x10000000)1772 {1760 /** @todo temporary: sanity check against running backwards */ 1761 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32); 1762 if (*pu32 - uOld >= 0x10000000) 1763 { 1773 1764 # if defined(IN_RING0) 1774 pThis->uPmTimeA = uOld;1775 pThis->uPmTimeB = *pu32;1776 return VERR_TM_TIMER_BAD_CLOCK;1765 pThis->uPmTimeA = uOld; 1766 pThis->uPmTimeB = *pu32; 1767 return VERR_TM_TIMER_BAD_CLOCK; 1777 1768 # elif defined(IN_RING3) 1778 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));1769 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32)); 1779 1770 # endif 1780 }1771 } 1781 1772 #endif 1782 1773 } 1774 else 1775 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 1776 } 1783 1777 NOREF(pvUser); NOREF(Port); 1784 1778 return rc; … … 2011 2005 #define R(offset, cnt, writer, reader, description) \ 2012 2006 do { \ 2013 int rc = PDMDevHlpIOPortRegister(p This->pDevInsR3, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \2007 int rc = PDMDevHlpIOPortRegister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \ 2014 2008 NULL, NULL, description); \ 2015 2009 if (RT_FAILURE(rc)) \ … … 2030 2024 if (pDevIns->fRCEnabled) 2031 2025 { 2032 int rc = PDMDevHlpIOPortRegisterRC(p This->pDevInsR3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),2026 int rc = PDMDevHlpIOPortRegisterRC(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET), 2033 2027 1, 0, NULL, "acpiPMTmrRead", 2034 2028 NULL, NULL, "ACPI PM Timer"); … … 2039 2033 if (pDevIns->fR0Enabled) 2040 2034 { 2041 int rc = PDMDevHlpIOPortRegisterR0(p This->pDevInsR3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),2035 int rc = PDMDevHlpIOPortRegisterR0(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET), 2042 2036 1, 0, NULL, "acpiPMTmrRead", 2043 2037 NULL, NULL, "ACPI PM Timer"); … … 2053 2047 * 2054 2048 * @returns VBox status code. 2055 * @param pThis The ACPI shared instance data. 2056 */ 2057 static int acpiR3UnregisterPmHandlers(ACPIState *pThis) 2049 * @param pDevIns The device instance. 2050 * @param pThis The ACPI shared instance data. 2051 */ 2052 static int acpiR3UnregisterPmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis) 2058 2053 { 2059 2054 if (pThis->uPmIoPortBase == 0) … … 2062 2057 #define U(offset, cnt) \ 2063 2058 do { \ 2064 int rc = PDMDevHlpIOPortDeregister(p This->pDevInsR3, acpiR3CalcPmPort(pThis, offset), cnt); \2059 int rc = PDMDevHlpIOPortDeregister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt); \ 2065 2060 AssertRCReturn(rc, rc); \ 2066 2061 } while (0) … … 2094 2089 if (NewIoPortBase != pThis->uPmIoPortBase) 2095 2090 { 2096 int rc = acpiR3UnregisterPmHandlers(p This);2091 int rc = acpiR3UnregisterPmHandlers(pDevIns, pThis); 2097 2092 if (RT_FAILURE(rc)) 2098 2093 return rc; … … 2105 2100 2106 2101 /* We have to update FADT table acccording to the new base */ 2107 rc = acpiR3PlantTables(p This);2102 rc = acpiR3PlantTables(pDevIns, pThis); 2108 2103 AssertRC(rc); 2109 2104 if (RT_FAILURE(rc)) … … 2161 2156 * needs to be implemented later if it ever becomes relevant. */ 2162 2157 if (new_level != old_level) 2163 acpiSetIrq(p This, new_level);2158 acpiSetIrq(pDevIns, new_level); 2164 2159 break; 2165 2160 } … … 2315 2310 * 2316 2311 * @returns VBox status code. 2317 * @param pThis The ACPI shared instance data. 2318 */ 2319 static int acpiR3RegisterSMBusHandlers(ACPIState *pThis) 2320 { 2321 int rc = VINF_SUCCESS; 2322 2312 * @param pDevIns The device instance. 2313 * @param pThis The ACPI shared instance data. 2314 */ 2315 static int acpiR3RegisterSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis) 2316 { 2323 2317 if (pThis->uSMBusIoPortBase == 0) 2324 2318 return VINF_SUCCESS; 2325 2319 2326 rc = PDMDevHlpIOPortRegister(pThis->pDevInsR3, pThis->uSMBusIoPortBase, 16, pThis, acpiR3SMBusWrite, acpiR3SMBusRead, NULL, NULL, "SMBus");2320 int rc = PDMDevHlpIOPortRegister(pDevIns, pThis->uSMBusIoPortBase, 16, pThis, acpiR3SMBusWrite, acpiR3SMBusRead, NULL, NULL, "SMBus"); 2327 2321 if (RT_FAILURE(rc)) 2328 2322 return rc; … … 2335 2329 * 2336 2330 * @returns VBox status code. 2337 * @param pThis The ACPI shared instance data. 2338 */ 2339 static int acpiR3UnregisterSMBusHandlers(ACPIState *pThis) 2331 * @param pDevIns The device instance. 2332 * @param pThis The ACPI shared instance data. 2333 */ 2334 static int acpiR3UnregisterSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis) 2340 2335 { 2341 2336 if (pThis->uSMBusIoPortBase == 0) 2342 2337 return VINF_SUCCESS; 2343 2338 2344 int rc = PDMDevHlpIOPortDeregister(p This->pDevInsR3, pThis->uSMBusIoPortBase, 16);2339 int rc = PDMDevHlpIOPortDeregister(pDevIns, pThis->uSMBusIoPortBase, 16); 2345 2340 AssertRCReturn(rc, rc); 2346 2341 … … 2354 2349 * @returns VBox status code. 2355 2350 * 2351 * @param pDevIns The device instance. 2356 2352 * @param pThis The ACPI shared instance data. 2357 2353 * @param NewIoPortBase The new base address of the I/O ports. 2358 2354 */ 2359 static int acpiR3UpdateSMBusHandlers( ACPIState *pThis, RTIOPORT NewIoPortBase)2355 static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis, RTIOPORT NewIoPortBase) 2360 2356 { 2361 2357 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase)); 2362 2358 if (NewIoPortBase != pThis->uSMBusIoPortBase) 2363 2359 { 2364 int rc = acpiR3UnregisterSMBusHandlers(p This);2360 int rc = acpiR3UnregisterSMBusHandlers(pDevIns, pThis); 2365 2361 if (RT_FAILURE(rc)) 2366 2362 return rc; … … 2368 2364 pThis->uSMBusIoPortBase = NewIoPortBase; 2369 2365 2370 rc = acpiR3RegisterSMBusHandlers(p This);2366 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis); 2371 2367 if (RT_FAILURE(rc)) 2372 2368 return rc; … … 2523 2519 * successfully loaded. 2524 2520 */ 2525 int rc = acpiR3UnregisterPmHandlers(p This);2521 int rc = acpiR3UnregisterPmHandlers(pDevIns, pThis); 2526 2522 if (RT_FAILURE(rc)) 2527 2523 return rc; … … 2531 2527 * successfully loaded. 2532 2528 */ 2533 rc = acpiR3UnregisterSMBusHandlers(p This);2529 rc = acpiR3UnregisterSMBusHandlers(pDevIns, pThis); 2534 2530 if (RT_FAILURE(rc)) 2535 2531 return rc; … … 2564 2560 if (RT_FAILURE(rc)) 2565 2561 return rc; 2566 rc = acpiR3RegisterSMBusHandlers(p This);2562 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis); 2567 2563 if (RT_FAILURE(rc)) 2568 2564 return rc; … … 2573 2569 if (RT_FAILURE(rc)) 2574 2570 return rc; 2575 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);2571 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED); 2576 2572 DEVACPI_LOCK_R3(pDevIns, pThis); 2577 uint64_t u64Now = TMTimerGet(pThis->pPmTimerR3);2573 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer); 2578 2574 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */ 2579 2575 acpiPmTimerUpdate(pDevIns, pThis, u64Now); 2580 acpiR3PmTimerReset(p This, u64Now);2576 acpiR3PmTimerReset(pDevIns, pThis, u64Now); 2581 2577 DEVACPI_UNLOCK(pDevIns, pThis); 2582 TMTimerUnlock(pThis->pPmTimerR3);2578 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 2583 2579 } 2584 2580 return rc; … … 2649 2645 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables. 2650 2646 */ 2651 DECLINLINE(void) acpiR3PhysCopy( ACPIState *pThis, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)2652 { 2653 PDMDevHlpPhysWrite(p This->pDevInsR3, GCPhys32Dst, pvSrc, cbToCopy);2647 DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy) 2648 { 2649 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy); 2654 2650 } 2655 2651 … … 2657 2653 * Plant the Differentiated System Description Table (DSDT). 2658 2654 */ 2659 static void acpiR3SetupDsdt(ACPIState *pThis, RTGCPHYS32 GCPhys32, void *pvPtr, size_t cbDsdt) 2660 { 2661 acpiR3PhysCopy(pThis, GCPhys32, pvPtr, cbDsdt); 2662 } 2663 2664 /** 2665 * Plan the Secondary System Description Table (SSDT). 2666 */ 2667 static void acpiR3SetupSsdt(ACPIState *pThis, RTGCPHYS32 addr, 2668 void* pPtr, size_t uSsdtLen) 2669 { 2670 acpiR3PhysCopy(pThis, addr, pPtr, uSsdtLen); 2655 static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt) 2656 { 2657 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt); 2658 } 2659 2660 /** 2661 * Plant the Secondary System Description Table (SSDT). 2662 */ 2663 static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen) 2664 { 2665 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen); 2671 2666 } 2672 2667 … … 2674 2669 * Plant the Firmware ACPI Control Structure (FACS). 2675 2670 */ 2676 static void acpiR3SetupFacs( ACPIState *pThis, RTGCPHYS32 addr)2671 static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr) 2677 2672 { 2678 2673 ACPITBLFACS facs; … … 2688 2683 facs.u8Version = 1; 2689 2684 2690 acpiR3PhysCopy(p This, addr, (const uint8_t *)&facs, sizeof(facs));2685 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs)); 2691 2686 } 2692 2687 … … 2694 2689 * Plant the Fixed ACPI Description Table (FADT aka FACP). 2695 2690 */ 2696 static void acpiR3SetupFadt( ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,2691 static void acpiR3SetupFadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2, 2697 2692 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt) 2698 2693 { … … 2761 2756 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET)); 2762 2757 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt)); 2763 acpiR3PhysCopy(p This, GCPhysAcpi2, &fadt, sizeof(fadt));2758 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt)); 2764 2759 2765 2760 /* Now the ACPI 1.0 version. */ … … 2768 2763 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */ 2769 2764 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE); 2770 acpiR3PhysCopy(p This, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);2765 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE); 2771 2766 } 2772 2767 … … 2778 2773 * ACPI 2.0 and up. 2779 2774 */ 2780 static int acpiR3SetupRsdt( ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)2775 static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs) 2781 2776 { 2782 2777 ACPITBLRSDT *rsdt; … … 2785 2780 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size); 2786 2781 if (!rsdt) 2787 return PDMDEV_SET_ERROR(p This->pDevInsR3, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));2782 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT")); 2788 2783 2789 2784 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1); … … 2794 2789 } 2795 2790 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size); 2796 acpiR3PhysCopy(p This, addr, rsdt, size);2791 acpiR3PhysCopy(pDevIns, addr, rsdt, size); 2797 2792 RTMemFree(rsdt); 2798 2793 return VINF_SUCCESS; … … 2802 2797 * Plant the Extended System Description Table. 2803 2798 */ 2804 static int acpiR3SetupXsdt( ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)2799 static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs) 2805 2800 { 2806 2801 ACPITBLXSDT *xsdt; … … 2822 2817 } 2823 2818 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size); 2824 acpiR3PhysCopy(p This, addr, xsdt, size);2819 acpiR3PhysCopy(pDevIns, addr, xsdt, size); 2825 2820 RTMemFree(xsdt); 2826 2821 return VINF_SUCCESS; … … 2971 2966 * @todo All hardcoded, should set this up based on the actual VM config!!!!! 2972 2967 */ 2973 static void acpiR3SetupMadt( ACPIState *pThis, RTGCPHYS32 addr)2968 static void acpiR3SetupMadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr) 2974 2969 { 2975 2970 uint16_t cpus = pThis->cCpus; … … 3036 3031 3037 3032 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size()); 3038 acpiR3PhysCopy(p This, addr, madt.data(), madt.size());3033 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size()); 3039 3034 } 3040 3035 … … 3042 3037 * Plant the High Performance Event Timer (HPET) descriptor. 3043 3038 */ 3044 static void acpiR3SetupHpet( ACPIState *pThis, RTGCPHYS32 addr)3039 static void acpiR3SetupHpet(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr) 3045 3040 { 3046 3041 ACPITBLHPET hpet; … … 3064 3059 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet)); 3065 3060 3066 acpiR3PhysCopy(p This, addr, (const uint8_t *)&hpet, sizeof(hpet));3061 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet)); 3067 3062 } 3068 3063 … … 3075 3070 * @param GCPhysDst Where to plant it. 3076 3071 */ 3077 static void acpiR3SetupMcfg( ACPIState *pThis, RTGCPHYS32 GCPhysDst)3072 static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysDst) 3078 3073 { 3079 3074 struct … … 3095 3090 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl)); 3096 3091 3097 acpiR3PhysCopy(p This, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));3092 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl)); 3098 3093 } 3099 3094 … … 3161 3156 * Create the ACPI tables in guest memory. 3162 3157 */ 3163 static int acpiR3PlantTables( ACPIState *pThis)3158 static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis) 3164 3159 { 3165 3160 int rc; … … 3210 3205 * The latter starts never below 4G. 3211 3206 */ 3212 PVM pVM = PDMDevHlpGetVM(p This->pDevInsR3);3207 PVM pVM = PDMDevHlpGetVM(pDevIns); 3213 3208 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM); 3214 3209 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM); … … 3278 3273 void *pvSsdtCode = NULL; 3279 3274 size_t cbSsdt = 0; 3280 rc = acpiPrepareSsdt(p This->pDevInsR3, &pvSsdtCode, &cbSsdt);3275 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt); 3281 3276 if (RT_FAILURE(rc)) 3282 3277 return rc; … … 3289 3284 void *pvDsdtCode = NULL; 3290 3285 size_t cbDsdt = 0; 3291 rc = acpiPrepareDsdt(p This->pDevInsR3, &pvDsdtCode, &cbDsdt);3286 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt); 3292 3287 if (RT_FAILURE(rc)) 3293 3288 return rc; … … 3296 3291 3297 3292 if (GCPhysCur > 0x10000) 3298 return PDMDEV_SET_ERROR(p This->pDevInsR3, VERR_TOO_MUCH_DATA,3293 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA, 3299 3294 N_("Error: ACPI tables bigger than 64KB")); 3300 3295 … … 3316 3311 3317 3312 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend); 3318 acpiR3SetupDsdt(p This, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);3319 acpiCleanupDsdt(p This->pDevInsR3, pvDsdtCode);3320 acpiR3SetupFacs(p This, GCPhysFacs + addend);3321 acpiR3SetupFadt(p This, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);3313 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt); 3314 acpiCleanupDsdt(pDevIns, pvDsdtCode); 3315 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend); 3316 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend); 3322 3317 3323 3318 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend; … … 3325 3320 if (pThis->u8UseIOApic) 3326 3321 { 3327 acpiR3SetupMadt(p This, GCPhysApic + addend);3322 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend); 3328 3323 aGCPhysRsdt[iMadt] = GCPhysApic + addend; 3329 3324 aGCPhysXsdt[iMadt] = GCPhysApic + addend; … … 3331 3326 if (pThis->fUseHpet) 3332 3327 { 3333 acpiR3SetupHpet(p This, GCPhysHpet + addend);3328 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend); 3334 3329 aGCPhysRsdt[iHpet] = GCPhysHpet + addend; 3335 3330 aGCPhysXsdt[iHpet] = GCPhysHpet + addend; … … 3337 3332 if (pThis->fUseMcfg) 3338 3333 { 3339 acpiR3SetupMcfg(p This, GCPhysMcfg + addend);3334 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend); 3340 3335 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend; 3341 3336 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend; … … 3344 3339 { 3345 3340 Assert(i < MAX_CUST_TABLES); 3346 acpiR3PhysCopy(p This, aGCPhysCust[i] + addend, pThis->apu8CustBin[i], pThis->acbCustBin[i]);3341 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThis->apu8CustBin[i], pThis->acbCustBin[i]); 3347 3342 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend; 3348 3343 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend; … … 3352 3347 } 3353 3348 3354 acpiR3SetupSsdt(p This, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);3355 acpiCleanupSsdt(p This->pDevInsR3, pvSsdtCode);3349 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt); 3350 acpiCleanupSsdt(pDevIns, pvSsdtCode); 3356 3351 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend; 3357 3352 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend; 3358 3353 3359 rc = acpiR3SetupRsdt(p This, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);3354 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt); 3360 3355 if (RT_FAILURE(rc)) 3361 3356 return rc; 3362 return acpiR3SetupXsdt(p This, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);3357 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt); 3363 3358 } 3364 3359 … … 3421 3416 } 3422 3417 3423 int rc = acpiR3UpdateSMBusHandlers(p This, NewIoPortBase);3418 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase); 3424 3419 AssertRC(rc); 3425 3420 } … … 3534 3529 RT_NOREF1(enmCtx); 3535 3530 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 3536 acpiR3PlantTables(p This);3531 acpiR3PlantTables(pDevIns, pThis); 3537 3532 } 3538 3533 … … 3545 3540 3546 3541 /* Play safe: make sure that the IRQ isn't stuck after a reset. */ 3547 acpiSetIrq(p This, 0);3548 3549 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);3542 acpiSetIrq(pDevIns, 0); 3543 3544 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED); 3550 3545 pThis->pm1a_en = 0; 3551 3546 pThis->pm1a_sts = 0; 3552 3547 pThis->pm1a_ctl = 0; 3553 pThis->u64PmTimerInitial = TMTimerGet(pThis->pPmTimerR3);3548 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer); 3554 3549 pThis->uPmTimerVal = 0; 3555 acpiR3PmTimerReset(p This, pThis->u64PmTimerInitial);3550 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial); 3556 3551 pThis->uPmTimeOld = pThis->uPmTimerVal; 3557 3552 pThis->uBatteryIndex = 0; … … 3560 3555 pThis->gpe0_sts = 0; 3561 3556 pThis->uSleepState = 0; 3562 TMTimerUnlock(pThis->pPmTimerR3);3557 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 3563 3558 3564 3559 /* Real device behavior is resetting only the PM controller state, … … 3570 3565 * state. Real device behavior is only the SMBus controller state reset, 3571 3566 * but we're additionally doing the job of the BIOS. */ 3572 acpiR3UpdateSMBusHandlers(p This, SMB_PORT_BASE);3567 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE); 3573 3568 acpiR3SMBusPCIBIOSFake(pDevIns, pThis); 3574 3569 acpiR3SMBusResetDevice(pThis); 3575 }3576 3577 /**3578 * @interface_method_impl{PDMDEVREG,pfnRelocate}3579 */3580 static DECLCALLBACK(void) acpiR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)3581 {3582 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);3583 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);3584 pThis->pPmTimerRC = TMTimerRCPtr(pThis->pPmTimerR3);3585 NOREF(offDelta);3586 3570 } 3587 3571 … … 3618 3602 /** @todo move more of the code up! */ 3619 3603 3620 pThis->pDevIns = pDevIns; 3621 pThis->pDevInsR3 = pDevIns; 3622 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 3623 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 3604 pThis->pDevIns = pDevIns; 3624 3605 VMCPUSET_EMPTY(&pThis->CpuSetAttached); 3625 3606 VMCPUSET_EMPTY(&pThis->CpuSetLocked); … … 3987 3968 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace(); 3988 3969 if (!GCPhysRsdp) 3989 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, 3990 N_("Can not find space for RSDP. ACPI is disabled")); 3991 3992 rc = acpiR3PlantTables(pThis); 3970 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled")); 3971 3972 rc = acpiR3PlantTables(pDevIns, pThis); 3993 3973 AssertRCReturn(rc, rc); 3994 3974 … … 4003 3983 AssertRCReturn(rc, rc); 4004 3984 4005 rc = acpiR3RegisterSMBusHandlers(p This);3985 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis); 4006 3986 AssertRCReturn(rc, rc); 4007 3987 … … 4026 4006 * Create the PM timer. 4027 4007 */ 4028 PTMTIMER pTimer; 4029 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/, 4030 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pTimer); 4008 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/, 4009 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer); 4031 4010 AssertRCReturn(rc, rc); 4032 pThis->pPmTimerR3 = pTimer; 4033 pThis->pPmTimerR0 = TMTimerR0Ptr(pTimer); 4034 pThis->pPmTimerRC = TMTimerRCPtr(pTimer); 4035 4036 rc = TMTimerLock(pTimer, VERR_IGNORED); 4011 4012 rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED); 4037 4013 AssertRCReturn(rc, rc); 4038 pThis->u64PmTimerInitial = TMTimerGet(pTimer);4039 acpiR3PmTimerReset(p This, pThis->u64PmTimerInitial);4040 TMTimerUnlock(pTimer);4014 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer); 4015 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial); 4016 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 4041 4017 4042 4018 /* … … 4153 4129 /* .pfnConstruct = */ acpiR3Construct, 4154 4130 /* .pfnDestruct = */ acpiR3Destruct, 4155 /* .pfnRelocate = */ acpiR3Relocate,4131 /* .pfnRelocate = */ NULL, 4156 4132 /* .pfnMemSetup = */ acpiR3MemSetup, 4157 4133 /* .pfnPowerOn = */ NULL,
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