Changeset 82050 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Nov 20, 2019 8:43:09 PM (5 years ago)
- Location:
- trunk/src/VBox/Devices/Graphics
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r82048 r82050 764 764 * 765 765 * @returns VBox status code. 766 * @param pDevIns The device instance. 766 767 * @param pThis VMSVGA State 767 768 * @param pu32 Where to store the read value 768 769 */ 769 PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)770 static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32) 770 771 { 771 772 int rc = VINF_SUCCESS; … … 1070 1071 /* Go to ring-3 and halt the CPU. */ 1071 1072 rc = VINF_IOM_R3_IOPORT_READ; 1073 RT_NOREF(pDevIns); 1072 1074 break; 1073 1075 #else … … 1083 1085 if (pThis->svga.fBusy) 1084 1086 { 1085 PDM CritSectLeave(&pThis->CritSect); /* hack around lock order issue. */1087 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */ 1086 1088 rc = VMR3WaitForDeviceReady(pVM, idCpu); 1087 PDM CritSectEnter(&pThis->CritSect, VERR_IGNORED);1089 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED); 1088 1090 } 1089 1091 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts); … … 1996 1998 1997 1999 case SVGA_VALUE_PORT: 1998 return vmsvgaReadPort(p This, pu32);2000 return vmsvgaReadPort(pDevIns, pThis, pu32); 1999 2001 2000 2002 case SVGA_BIOS_PORT: … … 4755 4757 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)) 4756 4758 { 4757 int rc2 = PDM CritSectEnter(&pThis->CritSect, VERR_IGNORED);4759 int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED); 4758 4760 AssertRC(rc2); 4759 4761 … … 4773 4775 } 4774 4776 4775 PDM CritSectLeave(&pThis->CritSect);4777 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4776 4778 } 4777 4779 } -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r82048 r82050 2880 2880 { 2881 2881 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 2882 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));2882 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 2883 2883 2884 2884 NOREF(pvUser); … … 2900 2900 { 2901 2901 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 2902 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));2902 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 2903 2903 NOREF(pvUser); 2904 2904 … … 2921 2921 { 2922 2922 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 2923 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));2923 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 2924 2924 2925 2925 NOREF(pvUser); … … 2987 2987 { 2988 2988 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser); 2989 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));2989 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 2990 2990 2991 2991 #ifdef VBE_BYTEWISE_IO … … 3018 3018 { 3019 3019 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser); 3020 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3020 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3021 3021 3022 3022 #ifdef VBE_BYTEWISE_IO … … 3059 3059 NOREF(pvUser); 3060 3060 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3061 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3061 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3062 3062 3063 3063 #ifdef VBE_BYTEWISE_IO … … 3092 3092 { 3093 3093 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3094 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3094 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3095 3095 LogFlowFunc(("Port 0x%x, u32 0x%x, cb %d\n", Port, u32, cb)); 3096 3096 … … 3107 3107 if (u32 == HGSMIOFFSET_VOID) 3108 3108 { 3109 PDM CritSectEnter(&pThis->CritSectIRQ, VERR_SEM_BUSY);3109 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSectIRQ, VERR_SEM_BUSY); 3110 3110 3111 3111 if (pThis->fu32PendingGuestFlags == 0) … … 3126 3126 } 3127 3127 3128 PDM CritSectLeave(&pThis->CritSectIRQ);3128 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSectIRQ); 3129 3129 } 3130 3130 else … … 3164 3164 { 3165 3165 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3166 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3166 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3167 3167 LogFlowFunc(("Port 0x%x, cb %d\n", Port, cb)); 3168 3168 … … 3424 3424 { 3425 3425 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3426 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3426 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3427 3427 3428 3428 return vgaInternalMMIOFill(pThis, pvUser, GCPhysAddr, u32Item, cbItem, cItems); … … 3439 3439 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3440 3440 STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryRead), a); 3441 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3441 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3442 3442 NOREF(pvUser); 3443 3443 … … 3496 3496 NOREF(pvUser); 3497 3497 STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryWrite), a); 3498 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3498 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3499 3499 3500 3500 int rc; … … 3569 3569 static int vgaLFBAccess(PVMCC pVM, PVGASTATE pThis, RTGCPHYS GCPhys, RTGCPTR GCPtr) 3570 3570 { 3571 int rc = PDM CritSectEnter(&pThis->CritSect, VINF_EM_RAW_EMULATE_INSTR);3571 int rc = PDMDevHlpCritSectEnter(pThis->CTX_SUFF(pDevIns), &pThis->CritSect, VINF_EM_RAW_EMULATE_INSTR); 3572 3572 if (rc != VINF_SUCCESS) 3573 3573 return rc; … … 3590 3590 rc = PGMShwMakePageWritable(PDMDevHlpGetVMCPU(pThis->CTX_SUFF(pDevIns)), GCPtr, 3591 3591 PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT); 3592 PDM CritSectLeave(&pThis->CritSect);3592 PDMDevHlpCritSectLeave(pThis->CTX_SUFF(pDevIns), &pThis->CritSect); 3593 3593 AssertMsgReturn( rc == VINF_SUCCESS 3594 3594 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */ … … 3598 3598 rc); 3599 3599 #else /* IN_RING3 : We don't have any virtual page address of the access here. */ 3600 PDM CritSectLeave(&pThis->CritSect);3600 PDMDevHlpCritSectLeave(pThis->CTX_SUFF(pDevIns), &pThis->CritSect); 3601 3601 Assert(GCPtr == 0); 3602 3602 RT_NOREF1(GCPtr); … … 3605 3605 } 3606 3606 3607 PDM CritSectLeave(&pThis->CritSect);3607 PDMDevHlpCritSectLeave(pThis->CTX_SUFF(pDevIns), &pThis->CritSect); 3608 3608 AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", rc)); 3609 3609 return rc; … … 3674 3674 static int lastWasNotNewline = 0; /* We are only called in a single-threaded way */ 3675 3675 RT_NOREF2(pDevIns, pvUser); 3676 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3676 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3677 3677 3678 3678 /* … … 3720 3720 { 3721 3721 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3722 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3722 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3723 3723 NOREF(pvUser); NOREF(Port); 3724 3724 … … 3743 3743 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); 3744 3744 NOREF(pvUser); NOREF(Port); 3745 Assert(PDM CritSectIsOwner(pDevIns->CTX_SUFF(pCritSectRo)));3745 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); 3746 3746 3747 3747 int rc = VINF_SUCCESS; … … 4723 4723 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 4724 4724 4725 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);4725 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 4726 4726 AssertRC(rc); 4727 4727 … … 4731 4731 { 4732 4732 /* Nothing to do as the guest will explicitely update us about frame buffer changes. */ 4733 PDM CritSectLeave(&pThis->CritSect);4733 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4734 4734 return VINF_SUCCESS; 4735 4735 } … … 4741 4741 if (VBVAUpdateDisplay (pThis) == VINF_SUCCESS) 4742 4742 { 4743 PDM CritSectLeave(&pThis->CritSect);4743 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4744 4744 return VINF_SUCCESS; 4745 4745 } … … 4760 4760 rc = vga_update_display(pThis, false /*fUpdateAll*/, false /*fFailOnResize*/, true /*reset_dirty*/, 4761 4761 pThis->pDrv, &pThis->graphic_mode); 4762 PDM CritSectLeave(&pThis->CritSect);4762 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4763 4763 return rc; 4764 4764 } … … 4797 4797 DECLCALLBACK(int) vgaUpdateDisplayAll(PVGASTATE pThis, bool fFailOnResize) 4798 4798 { 4799 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 4799 4800 #ifdef DEBUG_sunlover 4800 4801 LogFlow(("vgaPortUpdateDisplayAll\n")); 4801 4802 #endif /* DEBUG_sunlover */ 4802 4803 4803 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);4804 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 4804 4805 AssertRC(rc); 4805 4806 4806 4807 rc = updateDisplayAll(pThis, fFailOnResize); 4807 4808 4808 PDM CritSectLeave(&pThis->CritSect);4809 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4809 4810 return rc; 4810 4811 } … … 4887 4888 uint32_t *pcx, uint32_t *pcy) 4888 4889 { 4889 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 4890 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 4891 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 4890 4892 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pThis)); 4891 4893 … … 4898 4900 return VERR_INVALID_PARAMETER; 4899 4901 4900 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);4902 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 4901 4903 AssertRCReturn(rc, rc); 4902 4904 … … 4979 4981 rc = VERR_NOT_SUPPORTED; 4980 4982 4981 PDM CritSectLeave(&pThis->CritSect);4983 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 4982 4984 4983 4985 LogFlow(("vgaPortTakeScreenshot: returns %Rrc (cbData=%d cx=%d cy=%d)\n", rc, *pcbData, *pcx, *pcy)); … … 5015 5017 uint32_t cx, uint32_t cy) 5016 5018 { 5017 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5018 int rc = VINF_SUCCESS; 5019 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5020 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 5021 int rc; 5019 5022 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pThis)); 5020 5023 LogFlow(("vgaPortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy)); 5021 5024 5022 rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);5025 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 5023 5026 AssertRC(rc); 5024 5027 … … 5085 5088 rc = VERR_INVALID_PARAMETER; 5086 5089 5087 PDM CritSectLeave(&pThis->CritSect);5090 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5088 5091 5089 5092 LogFlow(("vgaPortDisplayBlt: returns %Rrc\n", rc)); … … 5093 5096 static DECLCALLBACK(void) vgaPortUpdateDisplayRect(PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t w, uint32_t h) 5094 5097 { 5098 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5099 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 5095 5100 uint32_t v; 5096 5101 vga_draw_line_func *vga_draw_line; … … 5104 5109 uint8_t *pbSrc; 5105 5110 5106 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface);5107 5111 5108 5112 #ifdef DEBUG_sunlover … … 5112 5116 Assert(pInterface); 5113 5117 5114 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);5118 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 5115 5119 AssertRC(rc); 5116 5120 … … 5122 5126 LogFlow(("vgaPortUpdateDisplayRect: nothing to do fRender is false.\n")); 5123 5127 #endif /* DEBUG_sunlover */ 5124 PDM CritSectLeave(&pThis->CritSect);5128 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5125 5129 return; 5126 5130 } … … 5168 5172 LogFlow(("vgaPortUpdateDisplayRect: nothing to do: %dx%d\n", w, h)); 5169 5173 #endif /* DEBUG_sunlover */ 5170 PDM CritSectLeave(&pThis->CritSect);5174 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5171 5175 return; 5172 5176 } … … 5186 5190 * Nothing to do, just return. 5187 5191 */ 5188 PDM CritSectLeave(&pThis->CritSect);5192 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5189 5193 return; 5190 5194 case 8: … … 5235 5239 } 5236 5240 5237 PDM CritSectLeave(&pThis->CritSect);5241 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5238 5242 #ifdef DEBUG_sunlover 5239 5243 LogFlow(("vgaPortUpdateDisplayRect: completed.\n")); … … 5251 5255 uint32_t cbDstLine, uint32_t cDstBitsPerPixel) 5252 5256 { 5257 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5258 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 5253 5259 uint32_t v; 5254 5260 vga_draw_line_func *vga_draw_line; … … 5257 5263 LogFlow(("vgaPortCopyRect: %d,%d %dx%d -> %d,%d\n", xSrc, ySrc, cx, cy, xDst, yDst)); 5258 5264 #endif /* DEBUG_sunlover */ 5259 5260 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface);5261 5265 5262 5266 Assert(pInterface); … … 5321 5325 } 5322 5326 5323 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);5327 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 5324 5328 AssertRC(rc); 5325 5329 … … 5342 5346 ) 5343 5347 { 5344 PDM CritSectLeave(&pThis->CritSect);5348 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5345 5349 return VERR_INVALID_STATE; 5346 5350 } … … 5352 5356 case 0: 5353 5357 /* Nothing to do, just return. */ 5354 PDM CritSectLeave(&pThis->CritSect);5358 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5355 5359 return VINF_SUCCESS; 5356 5360 case 8: … … 5393 5397 } 5394 5398 5395 PDM CritSectLeave(&pThis->CritSect);5399 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5396 5400 #ifdef DEBUG_sunlover 5397 5401 LogFlow(("vgaPortCopyRect: completed.\n")); … … 5403 5407 static DECLCALLBACK(void) vgaPortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender) 5404 5408 { 5405 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5409 PVGASTATE pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 5410 PPDMDEVINS pDevIns = pThis->CTX_SUFF(pDevIns); 5406 5411 5407 5412 LogFlow(("vgaPortSetRenderVRAM: fRender = %d\n", fRender)); 5408 5413 5409 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);5414 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 5410 5415 AssertRC(rc); 5411 5416 5412 5417 pThis->fRenderVRAM = fRender; 5413 5418 5414 PDM CritSectLeave(&pThis->CritSect);5419 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5415 5420 } 5416 5421 … … 5502 5507 Assert(pPciDev == pDevIns->apPciDevs[0]); 5503 5508 5504 int rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);5509 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY); 5505 5510 AssertRC(rc); 5506 5511 … … 5551 5556 /* NB: VBE_DISPI_INDEX_FB_BASE_HI is left unchanged here. */ 5552 5557 } 5553 PDM CritSectLeave(&pThis->CritSect);5558 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); 5554 5559 return rc; 5555 5560 } … … 5975 5980 if (pThis->pDrv) 5976 5981 { 5977 PDM CritSectLeave(&pThis->CritSect); /* hack around lock order issue. */5982 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */ 5978 5983 pThis->pDrv->pfnReset(pThis->pDrv); 5979 5984 pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, false, false, 0, 0, 0, 0, NULL); 5980 PDM CritSectEnter(&pThis->CritSect, VERR_IGNORED);5985 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED); 5981 5986 } 5982 5987 … … 6181 6186 } 6182 6187 6183 PDM R3CritSectDelete(&pThis->CritSectIRQ);6184 PDM R3CritSectDelete(&pThis->CritSect);6188 PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSectIRQ); 6189 PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect); 6185 6190 return VINF_SUCCESS; 6186 6191 } -
trunk/src/VBox/Devices/Graphics/DevVGA_VBVA.cpp
r82048 r82050 907 907 return; 908 908 909 PDM CritSectEnter(&pVGAState->CritSect, VERR_SEM_BUSY);909 PDMDevHlpCritSectEnter(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect, VERR_SEM_BUSY); 910 910 911 911 VBOX_VHWA_PENDINGCMD *pIter, *pNext; … … 921 921 } 922 922 923 PDM CritSectLeave(&pVGAState->CritSect);923 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 924 924 } 925 925 … … 929 929 return; 930 930 931 PDM CritSectEnter(&pVGAState->CritSect, VERR_SEM_BUSY);931 PDMDevHlpCritSectEnter(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect, VERR_SEM_BUSY); 932 932 933 933 VBOX_VHWA_PENDINGCMD *pIter, *pNext; … … 939 939 } 940 940 941 PDM CritSectLeave(&pVGAState->CritSect);941 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 942 942 } 943 943 … … 953 953 pCommand->Flags |= VBOXVHWACMD_FLAG_HG_ASYNCH; 954 954 pPend->pCommand = pCommand; 955 PDM CritSectEnter(&pVGAState->CritSect, VERR_SEM_BUSY);955 PDMDevHlpCritSectEnter(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect, VERR_SEM_BUSY); 956 956 if (ASMAtomicUoReadU32(&pVGAState->pendingVhwaCommands.cPending) < VBOX_VHWA_MAX_PENDING_COMMANDS) 957 957 { 958 958 RTListAppend(&pVGAState->pendingVhwaCommands.PendingList, &pPend->Node); 959 959 ASMAtomicIncU32(&pVGAState->pendingVhwaCommands.cPending); 960 PDM CritSectLeave(&pVGAState->CritSect);960 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 961 961 return; 962 962 } 963 PDM CritSectLeave(&pVGAState->CritSect);963 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 964 964 LogRel(("VBVA: Pending command count has reached its threshold.. completing them all..")); 965 965 RTMemFree(pPend); … … 1107 1107 return true; 1108 1108 1109 PDM CritSectEnter(&pVGAState->CritSect, VERR_SEM_BUSY);1109 PDMDevHlpCritSectEnter(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect, VERR_SEM_BUSY); 1110 1110 1111 1111 VBOX_VHWA_PENDINGCMD *pIter, *pNext; … … 1114 1114 if (!vbvaVHWACommandSubmit(pVGAState, pIter->pCommand, true)) 1115 1115 { 1116 PDM CritSectLeave(&pVGAState->CritSect);1116 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 1117 1117 return false; /* the command should be still pending */ 1118 1118 } … … 1124 1124 } 1125 1125 1126 PDM CritSectLeave(&pVGAState->CritSect);1126 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSect); 1127 1127 1128 1128 return true; … … 2084 2084 PPDMDEVINS pDevIns = pVGAState->pDevInsR3; 2085 2085 2086 PDM CritSectEnter(&pVGAState->CritSectIRQ, VERR_SEM_BUSY);2086 PDMDevHlpCritSectEnter(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSectIRQ, VERR_SEM_BUSY); 2087 2087 2088 2088 const uint32_t fu32CurrentGuestFlags = HGSMIGetHostGuestFlags(pVGAState->pHGSMI); … … 2106 2106 } 2107 2107 2108 PDM CritSectLeave(&pVGAState->CritSectIRQ);2108 PDMDevHlpCritSectLeave(pVGAState->CTX_SUFF(pDevIns), &pVGAState->CritSectIRQ); 2109 2109 } 2110 2110 … … 2113 2113 PPDMDEVINS pDevIns = pThis->pDevInsR3; 2114 2114 2115 PDM CritSectEnter(&pThis->CritSectIRQ, VERR_SEM_BUSY);2115 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSectIRQ, VERR_SEM_BUSY); 2116 2116 2117 2117 if (HGSMIGetHostGuestFlags(pThis->pHGSMI) & HGSMIHOSTFLAGS_IRQ) 2118 2118 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, PDM_IRQ_LEVEL_HIGH); 2119 2119 2120 PDM CritSectLeave(&pThis->CritSectIRQ);2120 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSectIRQ); 2121 2121 } 2122 2122 … … 2797 2797 2798 2798 pThis = IDISPLAYPORT_2_VGASTATE(pInterface); 2799 rc = PDM CritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);2799 rc = PDMDevHlpCritSectEnter(pThis->pDevInsR3, &pThis->CritSect, VERR_SEM_BUSY); 2800 2800 AssertRC(rc); 2801 2801 rc = vbvaSendModeHintWorker(pThis, cx, cy, cBPP, iDisplay, dx, dy, fEnabled, 2802 2802 fNotifyGuest); 2803 PDM CritSectLeave(&pThis->CritSect);2803 PDMDevHlpCritSectLeave(pThis->pDevInsR3, &pThis->CritSect); 2804 2804 return rc; 2805 2805 }
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