VirtualBox

Changeset 82406 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Dec 5, 2019 12:47:02 AM (5 years ago)
Author:
vboxsync
Message:

DevHDA: Cleanups. bugref:9218

Location:
trunk/src/VBox/Devices/Audio
Files:
11 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Audio/AudioMixer.cpp

    r82255 r82406  
    522522        && !(pSink->fStatus & AUDMIXSINK_STS_PENDING_DISABLE))
    523523    {
    524         rc = audioMixerStreamCtlInternal(pStream, PDMAUDIOSTREAMCMD_ENABLE, AUDMIXSTRMCTL_FLAG_NONE);
     524        rc = audioMixerStreamCtlInternal(pStream, PDMAUDIOSTREAMCMD_ENABLE, AUDMIXSTRMCTL_F_NONE);
    525525    }
    526526
    … …  
    729729            if (pStream == pSink->In.pStreamRecSource)
    730730            {
    731                 int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_FLAG_NONE);
     731                int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_F_NONE);
    732732                if (rc2 == VERR_NOT_SUPPORTED)
    733733                    rc2 = VINF_SUCCESS;
    … …  
    743743        RTListForEach(&pSink->lstStreams, pStream, AUDMIXSTREAM, Node)
    744744        {
    745             int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_FLAG_NONE);
     745            int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_F_NONE);
    746746            if (rc2 == VERR_NOT_SUPPORTED)
    747747                rc2 = VINF_SUCCESS;

  • trunk/src/VBox/Devices/Audio/AudioMixer.h

    r77602 r82406  
    3030#include <VBox/vmm/pdmaudioifs.h>
    3131
    32 /**
    33  * Structure for maintaining an audio mixer instance.
     32
     33/** Pointer to an audio mixer sink. */
     34typedef struct AUDMIXSINK *PAUDMIXSINK;
     35
     36
     37/**
     38 * Audio mixer instance.
    3439 */
    3540typedef struct AUDIOMIXER
    … …  
    4550    /** Number of used audio sinks. */
    4651    uint8_t                 cSinks;
    47 } AUDIOMIXER, *PAUDIOMIXER;
     52} AUDIOMIXER;
     53/** Pointer to an audio mixer instance. */
     54typedef AUDIOMIXER *PAUDIOMIXER;
    4855
    4956/** Defines an audio mixer stream's flags. */
    … …  
    5158
    5259/** No flags specified. */
    53 #define AUDMIXSTREAM_FLAG_NONE                  0
     60#define AUDMIXSTREAM_F_NONE                     0
    5461/** The mixing stream is flagged as being enabled (active). */
    55 #define AUDMIXSTREAM_FLAG_ENABLED               RT_BIT(0)
     62#define AUDMIXSTREAM_F_ENABLED                  RT_BIT(0)
    5663
    5764/** Defines an audio mixer stream's internal status. */
    … …  
    6875
    6976
    70 /** Prototype needed for AUDMIXSTREAM struct definition. */
    71 typedef struct AUDMIXSINK *PAUDMIXSINK;
    72 
    73 /**
    74  * Structure for maintaining an audio mixer stream.
     77/**
     78 * Audio mixer stream.
    7579 */
    7680typedef struct AUDMIXSTREAM
    … …  
    8488    /** Sink this stream is attached to. */
    8589    PAUDMIXSINK             pSink;
    86     /** Stream flags of type AUDMIXSTREAM_FLAG_. */
     90    /** Stream flags of type AUDMIXSTREAM_F_. */
    8791    uint32_t                fFlags;
    8892    /** Stream status of type AUDMIXSTREAM_STATUS_. */
    … …  
    153157
    154158/**
    155  * Structure for keeping audio input sink specifics.
     159 * Audio input sink specifics.
     160 *
    156161 * Do not use directly. Instead, use AUDMIXSINK.
    157162 */
    … …  
    163168
    164169/**
    165  * Structure for keeping audio output sink specifics.
     170 * Audio output sink specifics.
     171 *
    166172 * Do not use directly. Instead, use AUDMIXSINK.
    167173 */
    … …  
    171177
    172178/**
    173  * Structure for maintaining an audio mixer sink.
     179 * Audio mixer sink.
    174180 */
    175181typedef struct AUDMIXSINK
    … …  
    220226    } Dbg;
    221227#endif
    222 } AUDMIXSINK, *PAUDMIXSINK;
     228} AUDMIXSINK;
    223229
    224230/**
    … …  
    238244
    239245/** No flags specified. */
    240 #define AUDMIXSTRMCTL_FLAG_NONE         0
     246#define AUDMIXSTRMCTL_F_NONE            0
    241247
    242248int AudioMixerCreate(const char *pszName, uint32_t uFlags, PAUDIOMIXER *ppMixer);

  • trunk/src/VBox/Devices/Audio/DevHDA.cpp

    r82405 r82406  
    346346
    347347/** No register description (RD) flags defined. */
    348 #define HDA_RD_FLAG_NONE           0
     348#define HDA_RD_F_NONE           0
    349349/** Writes to SD are allowed while RUN bit is set. */
    350 #define HDA_RD_FLAG_SD_WRITE_RUN   RT_BIT(0)
     350#define HDA_RD_F_SD_WRITE_RUN   RT_BIT(0)
    351351
    352352/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
    … …  
    355355    /* -------       -------  ----------  ----------  ------------------------- --------------  -----------------  -----------------------------  ----------- */ \
    356356    /* Offset 0x80 (SD0) */ \
    357     { offset,        0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL  , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
     357    { offset,        0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL  , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
    358358    /* Offset 0x83 (SD0) */ \
    359     { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8  , hdaRegWriteSDSTS  , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
     359    { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU8  , hdaRegWriteSDSTS  , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
    360360    /* Offset 0x84 (SD0) */ \
    361     { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE,         hdaRegReadLPIB, hdaRegWriteU32    , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
     361    { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE,         hdaRegReadLPIB, hdaRegWriteU32    , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
    362362    /* Offset 0x88 (SD0) */ \
    363     { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
     363    { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
    364364    /* Offset 0x8C (SD0) -- upper 8 bits are reserved */ \
    365     { offset + 0xC,  0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
     365    { offset + 0xC,  0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
    366366    /* Reserved: FIFO Watermark. ** @todo Document this! */ \
    367     { offset + 0xE,  0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
     367    { offset + 0xE,  0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
    368368    /* Offset 0x90 (SD0) */ \
    369     { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
     369    { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
    370370    /* Offset 0x92 (SD0) */ \
    371     { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
     371    { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
    372372    /* Reserved: 0x94 - 0x98. */ \
    373373    /* Offset 0x98 (SD0) */ \
    374     { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
     374    { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
    375375    /* Offset 0x9C (SD0) */ \
    376     { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
     376    { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
    377377
    378378/** Defines a single audio stream register set (e.g. OSD0). */
    … …  
    385385    /* offset  size     read mask   write mask  flags             read callback     write callback       index + abbrev              */
    386386    /*-------  -------  ----------  ----------  ----------------- ----------------  -------------------     ------------------------ */
    387     { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
    388     { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMIN)         }, /* Minor Version */
    389     { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMAJ)         }, /* Major Version */
    390     { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
    391     { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
    392     { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteGCTL    , HDA_REG_IDX(GCTL)         }, /* Global Control */
    393     { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
    394     { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS)     }, /* State Change Status */
    395     { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl  , HDA_REG_IDX(GSTS)         }, /* Global Status */
    396     { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
    397     { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
    398     { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
    399     { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
    400     { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
    401     { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
    402     { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
    403     { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
    404     { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBWP  , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
    405     { 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBRP  , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
    406     { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
    407     { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
    408     { 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
    409     { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
    410     { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
    411     { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBWP  , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
    412     { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
    413     { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteU8      , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
    414     { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
    415     { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
    416     { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(IC)           }, /* Immediate Command */
    417     { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(IR)           }, /* Immediate Response */
    418     { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS   , hdaRegWriteIRS     , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
    419     { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
    420     { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
     387    { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
     388    { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMIN)         }, /* Minor Version */
     389    { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMAJ)         }, /* Major Version */
     390    { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
     391    { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
     392    { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteGCTL    , HDA_REG_IDX(GCTL)         }, /* Global Control */
     393    { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
     394    { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS)     }, /* State Change Status */
     395    { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl  , HDA_REG_IDX(GSTS)         }, /* Global Status */
     396    { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
     397    { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
     398    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
     399    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
     400    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
     401    { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
     402    { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
     403    { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
     404    { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteCORBWP  , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
     405    { 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteCORBRP  , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
     406    { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
     407    { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
     408    { 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
     409    { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
     410    { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
     411    { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteRIRBWP  , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
     412    { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
     413    { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteU8      , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
     414    { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
     415    { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
     416    { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(IC)           }, /* Immediate Command */
     417    { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(IR)           }, /* Immediate Response */
     418    { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_F_NONE, hdaRegReadIRS   , hdaRegWriteIRS     , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
     419    { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
     420    { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
    421421    /* 4 Serial Data In (SDI). */
    422422    HDA_REG_MAP_DEF_STREAM(0, SD0),
    … …  
    31763176        if (   RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
    31773177            /* Are writes to the register denied if RUN bit is set? */
    3178             && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
     3178            && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_F_SD_WRITE_RUN))
    31793179        {
    31803180            Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
    … …  
    33943394    {
    33953395        PHDABDLEDESC pDesc = (PHDABDLEDESC)pvStruct;
    3396         pDesc->fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
     3396        pDesc->fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
    33973397    }
    33983398    return rc;
    … …  
    34163416    {
    34173417        PHDABDLE pState = (PHDABDLE)pvStruct;
    3418         pState->Desc.fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
     3418        pState->Desc.fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
    34193419    }
    34203420    return rc;
    … …  
    40404040                       "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
    40414041                       pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
    4042                        pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
     4042                       pBDLE->Desc.fFlags & HDA_BDLE_F_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
    40434043}
    40444044
    … …  
    41964196
    41974197        pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
    4198                         pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
     4198                        pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC);
    41994199
    42004200        cbBDLE += bd.u32BufSize;

  • trunk/src/VBox/Devices/Audio/DevHDA.h

    r82401 r82406  
    5454
    5555/**
    56  * Structure for mapping a stream tag to an HDA stream.
     56 * Mapping a stream tag to an HDA stream.
    5757 */
    5858typedef struct HDATAG
    … …  
    6363    /** Pointer to associated stream. */
    6464    R3PTRTYPE(PHDASTREAM) pStream;
    65 } HDATAG, *PHDATAG;
     65} HDATAG;
     66/** Pointer to a HDA stream tag mapping. */
     67typedef HDATAG *PHDATAG;
    6668
    6769/** @todo Make STAM values out of this? */

  • trunk/src/VBox/Devices/Audio/DevHDACommon.cpp

    r82332 r82406  
    567567
    568568        LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
    569                  i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
     569                 i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC));
    570570
    571571        cbBDLE += bd.u32BufSize;
    … …  
    657657bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE)
    658658{
    659     return (pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC);
     659    return (pBDLE->Desc.fFlags & HDA_BDLE_F_IOC);
    660660}
    661661

  • trunk/src/VBox/Devices/Audio/DevHDACommon.h

    r82399 r82406  
    4545    /** Writable bits. */
    4646    uint32_t        writable;
    47     /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
    48      *  These are used to specify the handling (read/write)
    49      *  policy of the register. */
     47    /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
     48     *  specify the handling (read/write) policy of the register. */
    5049    uint32_t        fFlags;
    5150    /** Read callback. */
    … …  
    532531
    533532/** Interrupt on completion (IOC) flag. */
    534 #define HDA_BDLE_FLAG_IOC           RT_BIT(0)
     533#define HDA_BDLE_F_IOC              RT_BIT(0)
    535534
    536535

  • trunk/src/VBox/Devices/Audio/HDACodec.h

    r82399 r82406  
    6262
    6363/**
    64  * Structure for keeping a HDA codec state.
     64 * HDA codec state.
    6565 */
    6666typedef struct HDACODEC

  • trunk/src/VBox/Devices/Audio/HDAStream.h

    r82345 r82406  
    249249#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
    250250/**
    251  * Structure for keeping a HDA stream thread context.
     251 * HDA stream thread context (arguments).
    252252 */
    253253typedef struct HDASTREAMTHREADCTX

  • trunk/src/VBox/Devices/Audio/HDAStreamMap.h

    r76565 r82406  
    2323
    2424/**
    25  * Structure for keeping an audio stream data mapping.
     25 * Audio stream data mapping.
    2626 */
    2727typedef struct HDASTREAMMAP
    2828{
    2929    /** The stream's layout. */
    30     PDMAUDIOSTREAMLAYOUT               enmLayout;
    31     uint8_t                            cbFrameSize;
     30    PDMAUDIOSTREAMLAYOUT            enmLayout;
     31    uint8_t                         cbFrameSize;
    3232    /** Number of mappings in paMappings. */
    33     uint8_t                            cMappings;
    34     uint8_t                            aPadding[2];
     33    uint8_t                         cMappings;
     34    uint8_t                         aPadding[2];
    3535    /** Array of stream mappings.
    3636     *  Note: The mappings *must* be layed out in an increasing order, e.g.
    3737     *        how the data appears in the given data block. */
    38     R3PTRTYPE(PPDMAUDIOSTREAMMAP)      paMappings;
     38    R3PTRTYPE(PPDMAUDIOSTREAMMAP)   paMappings;
    3939#if HC_ARCH_BITS == 32
    40     RTR3PTR                            Padding1;
     40    RTR3PTR                         Padding1;
    4141#endif
    4242#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
    4343    /** Circular buffer holding for holding audio data for this mapping. */
    44     R3PTRTYPE(PRTCIRCBUF)              pCircBuf;
     44    R3PTRTYPE(PRTCIRCBUF)           pCircBuf;
    4545#endif
    4646} HDASTREAMMAP;
    4747AssertCompileSizeAlignment(HDASTREAMMAP, 8);
     48/** Pointer to an audio stream data mapping. */
    4849typedef HDASTREAMMAP *PHDASTREAMMAP;
    4950
    … …  
    5556void hdaR3StreamMapDestroy(PHDASTREAMMAP pMapping);
    5657void hdaR3StreamMapReset(PHDASTREAMMAP pMapping);
    57 #endif /* IN_RING3 */
     58#endif
    5859/** @} */
    5960

  • trunk/src/VBox/Devices/Audio/HDAStreamPeriod.cpp

    r76553 r82406  
    5050int hdaR3StreamPeriodCreate(PHDASTREAMPERIOD pPeriod)
    5151{
    52     Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_VALID));
     52    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_F_VALID));
    5353
    5454    int rc = RTCritSectInit(&pPeriod->CritSect);
    5555    AssertRCReturnStmt(rc, pPeriod->fStatus = 0, rc);
    56     pPeriod->fStatus = HDASTREAMPERIOD_FLAG_VALID;
     56    pPeriod->fStatus = HDASTREAMPERIOD_F_VALID;
    5757
    5858    return VINF_SUCCESS;
    … …  
    6666void hdaR3StreamPeriodDestroy(PHDASTREAMPERIOD pPeriod)
    6767{
    68     if (pPeriod->fStatus & HDASTREAMPERIOD_FLAG_VALID)
     68    if (pPeriod->fStatus & HDASTREAMPERIOD_F_VALID)
    6969    {
    7070        RTCritSectDelete(&pPeriod->CritSect);
    7171
    72         pPeriod->fStatus = HDASTREAMPERIOD_FLAG_NONE;
     72        pPeriod->fStatus = HDASTREAMPERIOD_F_NONE;
    7373    }
    7474}
    … …  
    138138                 pPeriod->cIntPending, pPeriod->u8SD));
    139139
    140     pPeriod->fStatus          &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
     140    pPeriod->fStatus          &= ~HDASTREAMPERIOD_F_ACTIVE;
    141141    pPeriod->u64StartWalClk    = 0;
    142142    pPeriod->u64ElapsedWalClk  = 0;
    … …  
    157157int hdaR3StreamPeriodBegin(PHDASTREAMPERIOD pPeriod, uint64_t u64WalClk)
    158158{
    159     Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE)); /* No nested calls. */
    160 
    161     pPeriod->fStatus          |= HDASTREAMPERIOD_FLAG_ACTIVE;
     159    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE)); /* No nested calls. */
     160
     161    pPeriod->fStatus          |= HDASTREAMPERIOD_F_ACTIVE;
    162162    pPeriod->u64StartWalClk    = u64WalClk;
    163163    pPeriod->u64ElapsedWalClk  = 0;
    … …  
    181181    Log3Func(("[SD%RU8] Took %zuus\n", pPeriod->u8SD, (RTTimeNanoTS() - pPeriod->Dbg.tsStartNs) / 1000));
    182182
    183     if (!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE))
     183    if (!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE))
    184184        return;
    185185
    … …  
    190190    Assert(hdaR3StreamPeriodIsComplete(pPeriod));
    191191
    192     pPeriod->fStatus &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
     192    pPeriod->fStatus &= ~HDASTREAMPERIOD_F_ACTIVE;
    193193}
    194194
    … …  
    200200void hdaR3StreamPeriodPause(PHDASTREAMPERIOD pPeriod)
    201201{
    202     AssertMsg((pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE), ("Period %p already in inactive state\n", pPeriod));
    203 
    204     pPeriod->fStatus &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
     202    AssertMsg((pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE), ("Period %p already in inactive state\n", pPeriod));
     203
     204    pPeriod->fStatus &= ~HDASTREAMPERIOD_F_ACTIVE;
    205205
    206206    Log3Func(("[SD%RU8]\n", pPeriod->u8SD));
    … …  
    214214void hdaR3StreamPeriodResume(PHDASTREAMPERIOD pPeriod)
    215215{
    216     AssertMsg(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE), ("Period %p already in active state\n", pPeriod));
    217 
    218     pPeriod->fStatus |= HDASTREAMPERIOD_FLAG_ACTIVE;
     216    AssertMsg(!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE), ("Period %p already in active state\n", pPeriod));
     217
     218    pPeriod->fStatus |= HDASTREAMPERIOD_F_ACTIVE;
    219219
    220220    Log3Func(("[SD%RU8]\n", pPeriod->u8SD));
    … …  
    321321{
    322322    /* Period not in use? */
    323     if (!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE))
     323    if (!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE))
    324324        return true; /* ... implies that it has passed. */
    325325

  • trunk/src/VBox/Devices/Audio/HDAStreamPeriod.h

    r76565 r82406  
    2929
    3030struct HDASTREAM;
    31 typedef HDASTREAM *PHDASTREAM;
     31typedef struct HDASTREAM *PHDASTREAM;
    3232
    3333#ifdef LOG_ENABLED
    3434/**
    35  * Structure for debug information of an HDA stream's period.
     35 * Debug stuff for a HDA stream's period.
    3636 */
    37 typedef struct HDASTREAMPERIODDBGINFO
     37typedef struct HDASTREAMPERIODDDEBUG
    3838{
    3939    /** Host start time (in ns) of the period. */
    4040    uint64_t                tsStartNs;
    41 } HDASTREAMPERIODDBGINFO, *PHDASTREAMPERIODDBGINFO;
     41} HDASTREAMPERIODDDEBUG;
    4242#endif
    4343
    4444/** No flags set. */
    45 #define HDASTREAMPERIOD_FLAG_NONE    0
     45#define HDASTREAMPERIOD_F_NONE      0
    4646/** The stream period has been initialized and is in a valid state. */
    47 #define HDASTREAMPERIOD_FLAG_VALID   RT_BIT(0)
     47#define HDASTREAMPERIOD_F_VALID     RT_BIT(0)
    4848/** The stream period is active. */
    49 #define HDASTREAMPERIOD_FLAG_ACTIVE  RT_BIT(1)
     49#define HDASTREAMPERIOD_F_ACTIVE    RT_BIT(1)
    5050
    5151/**
    52  * Structure for keeping an HDA stream's (time) period.
     52 * HDA stream's time period.
     53 *
    5354 * This is needed in order to keep track of stream timing and interrupt delivery.
    5455 */
    … …  
    7980    uint32_t                framesTransferred;
    8081#ifdef LOG_ENABLED
    81     /** Debugging information. */
    82     HDASTREAMPERIODDBGINFO  Dbg;
     82    /** Debugging state. */
     83    HDASTREAMPERIODDDEBUG   Dbg;
    8384#endif
    8485} HDASTREAMPERIOD;
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