Changeset 83263 in vbox for trunk/src/VBox/VMM

Timestamp:

Mar 11, 2020 4:34:33 PM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

136414

Message:

AMD IOMMU: bugref:9654 Skeletal bits.

Location:

trunk/src/VBox/VMM

Files:

• VMMR3/PDMDevHlp.cpp (modified) (3 diffs)
• VMMR3/PDMDevMiscHlp.cpp (modified) (1 diff)
• include/PDMInternal.h (modified) (5 diffs)

trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

@@ -3245 +3245 @@
     return VINF_SUCCESS;
 }
+
+
+/** @interface_method_impl{PDMDEVHLPR3,pfnIommuRegister} */
+static DECLCALLBACK(int) pdmR3DevHlp_IommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp)
+{
+    PDMDEV_ASSERT_DEVINS(pDevIns);
+    VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
+    LogFlow(("pdmR3DevHlp_IommuRegister: caller='%s'/%d: pIommuReg=%p:{.u32Version=%#x, .u32TheEnd=%#x } ppIommuHlp=%p\n",
+             pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
+    PVM pVM = pDevIns->Internal.s.pVMR3;
+
+    /*
+     * Validate input.
+     */
+    AssertMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGR3_VERSION,
+                    ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg->u32Version, PDM_IOMMUREGR3_VERSION),
+                    VERR_INVALID_PARAMETER);
+    /** @todo IOMMU: Validate other parameters, see also tstDevicePdmDevHlp.cpp. */
+    AssertMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGR3_VERSION,
+                    ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIommuReg->u32TheEnd, PDM_IOMMUREGR3_VERSION),
+                    VERR_INVALID_PARAMETER);
+    AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
+
+    VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
+    VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
+
+    /*
+     * Find free IOMMU slot.
+     */
+    unsigned idxIommu = 0;
+    for (idxIommu = 0; idxIommu < RT_ELEMENTS(pVM->pdm.s.aIommus); idxIommu++)
+        if (!pVM->pdm.s.aIommus[idxIommu].pDevInsR3)
+            break;
+    AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pVM->pdm.s.aIommus),
+                          ("Too many IOMMUs. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aIommus)),
+                          VERR_OUT_OF_RESOURCES);
+    PPDMIOMMU pIommu = &pVM->pdm.s.aIommus[idxIommu];
+
+    /*
+     * Init the R3 bits.
+     */
+    pIommu->idxIommu = idxIommu;
+    pIommu->pDevInsR3 = pDevIns;
+    Log(("PDM: Registered IOMMU device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
+
+    /* Set the helper pointer and return. */
+    *ppIommuHlp = &g_pdmR3DevIommuHlp;
+    LogFlow(("pdmR3DevHlp_IommuRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
+    return VINF_SUCCESS;
+}
+
 
 
@@ -4118 +4169 @@
     pdmR3DevHlp_RTCRegister,
     pdmR3DevHlp_PCIBusRegister,
+    pdmR3DevHlp_IommuRegister,
     pdmR3DevHlp_PICRegister,
     pdmR3DevHlp_ApicRegister,
@@ -4602 +4654 @@
     pdmR3DevHlp_RTCRegister,
     pdmR3DevHlp_PCIBusRegister,
+    pdmR3DevHlp_IommuRegister,
     pdmR3DevHlp_PICRegister,
     pdmR3DevHlp_ApicRegister,

trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

@@ -236 +236 @@
 
 
+/**
+ * IOMMU Device Helpers.
+ */
+const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
+{
+    PDM_IOMMUHLPR3_VERSION,
+    PDM_IOMMUHLPR3_VERSION /* the end */
+};
 
 

trunk/src/VBox/VMM/include/PDMInternal.h

@@ -107 +107 @@
 /** Pointer to a PDM PCI Bus instance. */
 typedef struct PDMPCIBUS *PPDMPCIBUS;
+/** Pointer to a PDM IOMMU instance. */
+typedef struct PDMIOMMU *PPDMIOMMU;
 /** Pointer to a DMAC instance. */
 typedef struct PDMDMAC *PPDMDMAC;
@@ -617 +619 @@
 
 /**
+ * PDM registered IOMMU device.
+ */
+typedef struct PDMIOMMU
+{
+    /** IOMMU index. */
+    uint32_t                        idxIommu;
+    uint32_t                        uPadding0; /**< Alignment padding.*/
+
+    /** Pointer to the IOMMU device instance - R3. */
+    PPDMDEVINSR3                    pDevInsR3;
+
+    /** Pointer to the IOMMU device instance - R0. */
+    PPDMDEVINSR0                    pDevInsR0;
+
+    /** Pointer to the IOMMU device instance - RC. */
+    PPDMDEVINSRC                    pDevInsRC;
+    RTRCPTR                         RCPtrPadding;
+} PDMIOMMU;
+
+
+/**
  * PDM registered PIC device.
  */
@@ -695 +718 @@
 
 /** Maximum number of PCI busses for a VM. */
-#define PDM_PCI_BUSSES_MAX 8
+#define PDM_PCI_BUSSES_MAX  8
+/** Maximum number of IOMMUs (at most one per PCI bus). */
+#define PDM_IOMMUS_MAX      PDM_PCI_BUSSES_MAX
 
 
@@ -1225 +1250 @@
     /** PCI Buses. */
     PDMPCIBUS                       aPciBuses[PDM_PCI_BUSSES_MAX];
+    /** IOMMU devices. */
+    PDMIOMMU                        aIommus[PDM_IOMMUS_MAX];
     /** The register PIC device. */
     PDMPIC                          Pic;
@@ -1394 +1421 @@
 extern const PDMFWHLPR3     g_pdmR3DevFirmwareHlp;
 extern const PDMPCIHLPR3    g_pdmR3DevPciHlp;
+extern const PDMIOMMUHLPR3  g_pdmR3DevIommuHlp;
 extern const PDMDMACHLP     g_pdmR3DevDmacHlp;
 extern const PDMRTCHLP      g_pdmR3DevRtcHlp;