Changeset 83542 in vbox for trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
- Timestamp:
- Apr 3, 2020 5:51:10 PM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (14 diffs)
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- Added
- Removed
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trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r83519 r83542 25 25 26 26 #include "VBoxDD.h" 27 #include <iprt/x86.h> 27 28 28 29 … … 1082 1083 /** The 64-bit unsigned integer view. */ 1083 1084 uint64_t u64; 1084 } IOMMU_EXCL_ BASE_T;1085 AssertCompileSize(IOMMU_EXCL_ BASE_T, 8);1085 } IOMMU_EXCL_RANGE_BAR_T; 1086 AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8); 1086 1087 1087 1088 /** … … 1130 1131 uint32_t u2DualEvtLogSup : 2; /**< Bits 29:28 - DualEventLogSup: Dual Event Log Support. */ 1131 1132 uint32_t u2Rsvd1 : 2; /**< Bits 31:30 - Reserved. */ 1132 1133 1133 uint32_t u5MaxPasidSup : 5; /**< Bits 36:32 - PASMax: Maximum PASID Supported. */ 1134 1134 uint32_t u1UserSupervisorSup : 1; /**< Bit 37 - USSup: User/Supervisor Page Protection Support. */ … … 1155 1155 /** The 64-bit unsigned integer view. */ 1156 1156 uint64_t u64; 1157 } IOMMU_E FR_T;1158 AssertCompileSize(IOMMU_E FR_T, 8);1157 } IOMMU_EXT_FEAT_T; 1158 AssertCompileSize(IOMMU_EXT_FEAT_T, 8); 1159 1159 1160 1160 /** … … 1207 1207 struct 1208 1208 { 1209 uint32_t u1 HwEventValid : 1;/**< Bit 0 - HEV: Hardware Event Valid. */1210 uint32_t u1 HwEventOverflow : 1;/**< Bit 1 - HEO: Hardware Event Overflow. */1211 uint32_t u30Rsvd0 : 30; 1212 uint32_t u32Rsvd0; 1209 uint32_t u1Valid : 1; /**< Bit 0 - HEV: Hardware Event Valid. */ 1210 uint32_t u1Overflow : 1; /**< Bit 1 - HEO: Hardware Event Overflow. */ 1211 uint32_t u30Rsvd0 : 30; /**< Bits 31:2 - Reserved. */ 1212 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */ 1213 1213 } n; 1214 1214 /** The 64-bit unsigned integer view. */ … … 1293 1293 struct 1294 1294 { 1295 uint32_t u24DevSpecFeat Sup: 24; /**< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. */1296 uint32_t u4RevMinor : 4; 1297 uint32_t u4RevMajor : 4; 1298 uint32_t u32Rsvd0; 1295 uint32_t u24DevSpecFeat : 24; /**< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. */ 1296 uint32_t u4RevMinor : 4; /**< Bits 27:24 - RevMinor: Minor revision identifier. */ 1297 uint32_t u4RevMajor : 4; /**< Bits 31:28 - RevMajor: Major revision identifier. */ 1298 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/ 1299 1299 } n; 1300 1300 /** The 64-bit unsigned integer view. */ … … 1311 1311 struct 1312 1312 { 1313 uint32_t u24DevSpec FeatSup: 24; /**< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. */1314 uint32_t u4RevMinor : 4; 1315 uint32_t u4RevMajor : 4; 1316 uint32_t u32Rsvd0; 1313 uint32_t u24DevSpecCtrl : 24; /**< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. */ 1314 uint32_t u4RevMinor : 4; /**< Bits 27:24 - RevMinor: Minor revision identifier. */ 1315 uint32_t u4RevMajor : 4; /**< Bits 31:28 - RevMajor: Major revision identifier. */ 1316 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/ 1317 1317 } n; 1318 1318 /** The 64-bit unsigned integer view. */ … … 1347 1347 struct 1348 1348 { 1349 uint32_t u5MsiNum : 5; /**< Bits 4:0 - MsiNum: MSI Vector used for interrupt messages generated by the IOMMU. */1349 uint32_t u5MsiNumEvtLog : 5; /**< Bits 4:0 - MsiNum: Event Log MSI message number. */ 1350 1350 uint32_t u3GstVirtAddrSize: 3; /**< Bits 7:5 - GVAsize: Guest Virtual Address Size. */ 1351 1351 uint32_t u7PhysAddrSize : 7; /**< Bits 14:8 - PAsize: Physical Address Size. */ … … 1395 1395 struct 1396 1396 { 1397 uint32_t u2Rsvd : 2; /**< Bits 1:0 - Reserved. */ 1398 uint32_t u30MsiAddrLo : 30; /**< Bits 31:2 - MsiAddr: MSI Address (Lo). */ 1399 uint32_t u32MsiAddrHi; /**< Bits 63:32 - MsiAddr: MSI Address (Hi). */ 1397 RT_GCC_EXTENSION uint64_t u2Rsvd : 2; /**< Bits 1:0 - Reserved. */ 1398 RT_GCC_EXTENSION uint64_t u62MsiAddr : 62; /**< Bits 31:2 - MsiAddr: MSI Address. */ 1400 1399 } n; 1401 1400 /** The 32-bit unsigned integer view. */ … … 1742 1741 struct 1743 1742 { 1744 uint32_t u 3AutoRespCode : 4; /**< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. */1743 uint32_t u4AutoRespCode : 4; /**< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. */ 1745 1744 uint32_t u1AutoRespMaskGen : 1; /**< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. */ 1746 1745 uint32_t u27Rsvd0 : 27; /**< Bits 31:5 - Reserved. */ … … 1801 1800 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */ 1802 1801 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */ 1803 IOMMU_EXCL_ BASE_T ExclBase; /**< IOMMU exclusionbase register. */1802 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */ 1804 1803 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */ 1805 IOMMU_E FR_TExtFeat; /**< IOMMU extended feature register. */1804 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */ 1806 1805 /** @} */ 1807 1806 … … 1978 1977 case IOMMU_MMIO_OFF_EVT_LOG_BAR: *puResult = pThis->EvtLogBaseAddr.u64; break; 1979 1978 case IOMMU_MMIO_OFF_CTRL: *puResult = pThis->Ctrl.u64; break; 1980 case IOMMU_MMIO_OFF_EXCL_BAR: *puResult = pThis->Excl Base.u64;break;1979 case IOMMU_MMIO_OFF_EXCL_BAR: *puResult = pThis->ExclRangeBaseAddr.u64; break; 1981 1980 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: *puResult = pThis->ExclRangeLimit.u64; break; 1982 1981 case IOMMU_MMIO_OFF_EXT_FEAT: *puResult = pThis->ExtFeat.u64; break; … … 2109 2108 2110 2109 # ifdef IN_RING3 2110 static void iommuAmdR3DecodeBufferLength(uint8_t uEncodedLen, uint32_t *pcEntries, uint32_t *pcbBuffer) 2111 { 2112 if (uEncodedLen >= 8) 2113 { 2114 *pcEntries = 2 << (uEncodedLen - 1); 2115 *pcbBuffer = *pcEntries << 4; 2116 } 2117 else 2118 { 2119 *pcEntries = 0; 2120 *pcbBuffer = 0; 2121 } 2122 } 2123 2124 2125 /** 2126 * @callback_method_impl{FNDBGFHANDLERDEV} 2127 */ 2128 static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 2129 { 2130 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 2131 Assert(pThis); 2132 2133 LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs)); 2134 #if 0 2135 bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose") ? true : false; 2136 #else 2137 NOREF(pszArgs); 2138 #endif 2139 2140 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n"); 2141 /* Device Table Base Address. */ 2142 { 2143 DEV_TAB_BAR_T const DevTabBar = pThis->DevTabBaseAddr; 2144 pHlp->pfnPrintf(pHlp, " Device Table BAR = %#RX64\n", DevTabBar.u64); 2145 pHlp->pfnPrintf(pHlp, " Size = %u (%u bytes)\n", DevTabBar.n.u9Size, 2146 (DevTabBar.n.u9Size + 1) * _4K); 2147 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40DevTabBase); 2148 } 2149 /* Command Buffer Base Address Register. */ 2150 { 2151 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr; 2152 uint32_t cEntries; 2153 uint32_t cbBuffer; 2154 uint8_t const uEncodedLen = CmdBufBar.n.u4CmdLen; 2155 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2156 pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64); 2157 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40CmdBase); 2158 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2159 cbBuffer); 2160 } 2161 /* Event Log Base Address Register. */ 2162 { 2163 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr; 2164 uint32_t cEntries; 2165 uint32_t cbBuffer; 2166 uint8_t const uEncodedLen = EvtLogBar.n.u4EvtLen; 2167 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2168 pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64); 2169 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40EvtBase); 2170 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2171 cbBuffer); 2172 } 2173 /* IOMMU Control Register. */ 2174 { 2175 IOMMU_CTRL_T const Ctrl = pThis->Ctrl; 2176 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64); 2177 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn); 2178 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn); 2179 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn); 2180 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn); 2181 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn); 2182 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut); 2183 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW); 2184 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW); 2185 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent); 2186 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc); 2187 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn); 2188 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn); 2189 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn); 2190 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn); 2191 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn); 2192 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn); 2193 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw); 2194 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn); 2195 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis); 2196 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn); 2197 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn); 2198 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn); 2199 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn); 2200 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn); 2201 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn); 2202 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn); 2203 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn); 2204 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn); 2205 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn); 2206 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn); 2207 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn); 2208 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE); 2209 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr); 2210 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate); 2211 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis); 2212 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn); 2213 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn); 2214 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis); 2215 } 2216 /* Exclusion Base Address Register. */ 2217 { 2218 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr; 2219 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64); 2220 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable); 2221 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll); 2222 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", ExclRangeBar.n.u40ExclRangeBase); 2223 } 2224 /* Exclusion Range Limit Register. */ 2225 { 2226 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit; 2227 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64); 2228 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u40ExclLimit); 2229 } 2230 /* Extended Feature Register. */ 2231 { 2232 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat; 2233 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64); 2234 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup); 2235 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup); 2236 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup); 2237 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup); 2238 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup); 2239 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup); 2240 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup); 2241 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup); 2242 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup); 2243 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize); 2244 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize); 2245 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel); 2246 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup); 2247 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount); 2248 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup); 2249 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup); 2250 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup); 2251 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup); 2252 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup); 2253 pHlp->pfnPrintf(pHlp, " Device table segments supported = %u\n", (ExtFeat.n.u2DevTabSegSup << 1)); 2254 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn); 2255 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup); 2256 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup); 2257 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup); 2258 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup); 2259 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup); 2260 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup); 2261 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup); 2262 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup); 2263 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup); 2264 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup); 2265 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup); 2266 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup); 2267 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup); 2268 } 2269 /* PPR Log Base Address Register. */ 2270 { 2271 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr; 2272 uint32_t cEntries; 2273 uint32_t cbBuffer; 2274 uint8_t const uEncodedLen = PprLogBar.n.u4PprLogLen; 2275 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2276 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64); 2277 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40PprLogBase); 2278 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2279 cbBuffer); 2280 } 2281 /* Hardware Event (Hi) Register. */ 2282 { 2283 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi; 2284 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64); 2285 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand); 2286 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode); 2287 } 2288 /* Hardware Event (Lo) Register. */ 2289 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo); 2290 /* Hardware Event Status. */ 2291 { 2292 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus; 2293 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64); 2294 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid); 2295 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow); 2296 } 2297 /* Guest Virtual-APIC Log Base Address Register. */ 2298 { 2299 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr; 2300 uint32_t cEntries; 2301 uint32_t cbBuffer; 2302 uint8_t const uEncodedLen = GALogBar.n.u4GALogLen; 2303 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2304 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64); 2305 pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40GALogBase); 2306 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2307 cbBuffer); 2308 } 2309 /* Guest Virtual-APIC Log Tail Address Register. */ 2310 { 2311 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr; 2312 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64); 2313 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr); 2314 } 2315 /* PPR Log B Base Address Register. */ 2316 { 2317 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr; 2318 uint32_t cEntries; 2319 uint32_t cbBuffer; 2320 uint8_t const uEncodedLen = PprLogBBar.n.u4PprLogLen; 2321 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2322 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64); 2323 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40PprLogBase); 2324 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2325 cbBuffer); 2326 } 2327 /* Event Log B Base Address Register. */ 2328 { 2329 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr; 2330 uint32_t cEntries; 2331 uint32_t cbBuffer; 2332 uint8_t const uEncodedLen = EvtLogBBar.n.u4EvtLen; 2333 iommuAmdR3DecodeBufferLength(uEncodedLen, &cEntries, &cbBuffer); 2334 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64); 2335 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40EvtBase); 2336 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen, cEntries, 2337 cbBuffer); 2338 } 2339 /* Device Table Segment Registers. */ 2340 for (unsigned i = 0; i < RT_ELEMENTS(pThis->DevTabSeg); i++) 2341 { 2342 DEV_TAB_SEG_BAR_T const DevTabSeg = pThis->DevTabSeg[i]; 2343 pHlp->pfnPrintf(pHlp, " Device Table Segment BAR [%u] = %#RX64\n", DevTabSeg.u64); 2344 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabSeg.n.u40DevTabBase); 2345 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabSeg.n.u8Size, 2346 (DevTabSeg.n.u8Size + 1) << X86_PAGE_4K_SHIFT); 2347 } 2348 /* Device-Specific Feature Extension Register. */ 2349 { 2350 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat; 2351 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64); 2352 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat); 2353 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor); 2354 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor); 2355 } 2356 /* Device-Specific Control Extension Register. */ 2357 { 2358 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl; 2359 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64); 2360 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl); 2361 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor); 2362 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor); 2363 } 2364 /* Device-Specific Status Extension Register. */ 2365 { 2366 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus; 2367 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64); 2368 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus); 2369 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor); 2370 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor); 2371 } 2372 /* MSI Miscellaneous Information Register (Lo and Hi). */ 2373 { 2374 MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo; 2375 pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64); 2376 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog); 2377 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize); 2378 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize); 2379 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize); 2380 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv); 2381 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr); 2382 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa); 2383 } 2384 /* MSI Capability Header. */ 2385 { 2386 MSI_CAP_HDR_T const MsiCapHdr = pThis->MsiCapHdr; 2387 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32); 2388 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId); 2389 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr); 2390 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable); 2391 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap); 2392 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn); 2393 } 2394 /* MSI Address Register (Lo and Hi). */ 2395 { 2396 MSI_ADDR_T const MsiAddr = pThis->MsiAddr; 2397 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64); 2398 pHlp->pfnPrintf(pHlp, " Address = %#RX64\n", MsiAddr.n.u62MsiAddr); 2399 } 2400 /* MSI Data. */ 2401 { 2402 MSI_DATA_T const MsiData = pThis->MsiData; 2403 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32); 2404 pHlp->pfnPrintf(pHlp, " Data = %#x\n", MsiData.n.u16MsiData); 2405 } 2406 /* MSI Mapping Capability Header. */ 2407 { 2408 MSI_MAP_CAP_HDR_T const MsiMapCapHdr = pThis->MsiMapCapHdr; 2409 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32); 2410 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId); 2411 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn); 2412 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed); 2413 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType); 2414 } 2415 /* Performance Optimization Control Register. */ 2416 { 2417 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl; 2418 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32); 2419 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn); 2420 } 2421 /* XT (x2APIC) General Interrupt Control Register. */ 2422 { 2423 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl; 2424 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64); 2425 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n", 2426 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical"); 2427 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n", 2428 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi)); 2429 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector); 2430 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n", 2431 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated"); 2432 } 2433 /* XT (x2APIC) PPR Interrupt Control Register. */ 2434 { 2435 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl; 2436 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64); 2437 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n", 2438 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical"); 2439 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n", 2440 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi)); 2441 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector); 2442 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n", 2443 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated"); 2444 } 2445 /* XT (X2APIC) GA Log Interrupt Control Register. */ 2446 { 2447 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl; 2448 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64); 2449 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n", 2450 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical"); 2451 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n", 2452 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi)); 2453 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector); 2454 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n", 2455 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated"); 2456 } 2457 /* MARC Registers. */ 2458 { 2459 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++) 2460 { 2461 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i); 2462 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base; 2463 pHlp->pfnPrintf(pHlp, " Base = %#RX64 (addr: %#RX64)\n", MarcAperBar.u64, MarcAperBar.n.u40MarcBaseAddr); 2464 2465 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc; 2466 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n", 2467 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr, MarcAperReloc.n.u1ReadOnly, 2468 MarcAperReloc.n.u1RelocEn); 2469 2470 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length; 2471 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength); 2472 } 2473 } 2474 /* Reserved Register. */ 2475 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg); 2476 /* Command Buffer Head Pointer Register. */ 2477 { 2478 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr; 2479 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64); 2480 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.u15Ptr); 2481 } 2482 /* Command Buffer Tail Pointer Register. */ 2483 { 2484 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr; 2485 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64); 2486 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.u15Ptr); 2487 } 2488 /* Event Log Head Pointer Register. */ 2489 { 2490 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr; 2491 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64); 2492 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.u15Ptr); 2493 } 2494 /* Event Log Tail Pointer Register. */ 2495 { 2496 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr; 2497 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64); 2498 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.u15Ptr); 2499 } 2500 /* Status Register. */ 2501 { 2502 IOMMU_STATUS_T const Status = pThis->Status; 2503 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64); 2504 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow); 2505 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr); 2506 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr); 2507 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning); 2508 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning); 2509 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow); 2510 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr); 2511 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning); 2512 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning); 2513 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr); 2514 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB); 2515 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive); 2516 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB); 2517 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive); 2518 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB); 2519 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly); 2520 } 2521 /* PPR Log Head Pointer. */ 2522 { 2523 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr; 2524 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64); 2525 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.u15Ptr); 2526 } 2527 /* PPR Log Tail Pointer. */ 2528 { 2529 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr; 2530 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64); 2531 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.u15Ptr); 2532 } 2533 /* Guest Virtual-APIC Log Head Pointer. */ 2534 { 2535 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr; 2536 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64); 2537 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr); 2538 } 2539 /* Guest Virtual-APIC Log Tail Pointer. */ 2540 { 2541 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr; 2542 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64); 2543 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr); 2544 } 2545 /* PPR Log B Head Pointer. */ 2546 { 2547 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr; 2548 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64); 2549 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.u15Ptr); 2550 } 2551 /* PPR Log B Tail Pointer. */ 2552 { 2553 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr; 2554 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64); 2555 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.u15Ptr); 2556 } 2557 /* Event Log B Head Pointer. */ 2558 { 2559 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr; 2560 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64); 2561 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.u15Ptr); 2562 } 2563 /* Event Log B Tail Pointer. */ 2564 { 2565 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr; 2566 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64); 2567 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.u15Ptr); 2568 } 2569 /* PPR Log Auto Response Register. */ 2570 { 2571 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp; 2572 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64); 2573 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode); 2574 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen); 2575 } 2576 /* PPR Log Overflow Early Warning Indicator Register. */ 2577 { 2578 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly; 2579 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64); 2580 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold); 2581 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn); 2582 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable); 2583 } 2584 /* PPR Log Overflow Early Warning Indicator Register. */ 2585 { 2586 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly; 2587 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64); 2588 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold); 2589 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn); 2590 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable); 2591 } 2592 } 2593 2594 2111 2595 /** 2112 2596 * @callback_method_impl{FNSSMDEVSAVEEXEC} … … 2305 2789 NULL, iommuAmdR3SaveExec, NULL, 2306 2790 NULL, iommuAmdR3LoadExec, NULL); 2791 AssertRCReturn(rc, rc); 2792 2793 /* 2794 * Register debugger info item. 2795 */ 2796 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo); 2307 2797 AssertRCReturn(rc, rc); 2308 2798
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