VirtualBox

Changeset 84652 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 3, 2020 9:08:30 AM (5 years ago)
Author:
vboxsync
Message:

APIC: Move generic defs from VBox/vmm/apic.h and APICInternal.h to VBox/apic.h.

Location:
trunk/src/VBox/VMM
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r82968 r84652  
    2222#define LOG_GROUP LOG_GROUP_DEV_APIC
    2323#include "APICInternal.h"
     24#include <VBox/vmm/apic.h>
    2425#include <VBox/vmm/pdmdev.h>
    2526#include <VBox/vmm/pdmapi.h>

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r82968 r84652  
    2323#include <VBox/log.h>
    2424#include "APICInternal.h"
     25#include <VBox/vmm/apic.h>
    2526#include <VBox/vmm/cpum.h>
    2627#include <VBox/vmm/hm.h>

  • trunk/src/VBox/VMM/include/APICInternal.h

    r82968 r84652  
    2222#endif
    2323
     24#include <VBox/apic.h>
    2425#include <VBox/sup.h>
    25 #include <VBox/vmm/pdmdev.h> /* before apic.h! */
    26 #include <VBox/vmm/apic.h>
     26#include <VBox/vmm/pdmdev.h>
    2727
    2828/** @defgroup grp_apic_int       Internal
    … …  
    3232 */
    3333
    34 /** The APIC hardware version number for Pentium 4. */
    35 #define XAPIC_HARDWARE_VERSION_P4            UINT8_C(0x14)
    36 /** Maximum number of LVT entries for Pentium 4. */
    37 #define XAPIC_MAX_LVT_ENTRIES_P4             UINT8_C(6)
    38 /** Size of the APIC ID bits for Pentium 4. */
    39 #define XAPIC_APIC_ID_BIT_COUNT_P4           UINT8_C(8)
    40 
    41 /** The APIC hardware version number for Pentium 6. */
    42 #define XAPIC_HARDWARE_VERSION_P6            UINT8_C(0x10)
    43 /** Maximum number of LVT entries for Pentium 6. */
    44 #define XAPIC_MAX_LVT_ENTRIES_P6             UINT8_C(4)
    45 /** Size of the APIC ID bits for Pentium 6. */
    46 #define XAPIC_APIC_ID_BIT_COUNT_P6           UINT8_C(4)
    47 
    4834/** The APIC hardware version we are emulating. */
    4935#define XAPIC_HARDWARE_VERSION               XAPIC_HARDWARE_VERSION_P4
     36
     37#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
     38#define XAPIC_SVR_VALID                      XAPIC_SVR_VALID_P4
     39#define XAPIC_ID_BROADCAST_MASK              XAPIC_ID_BROADCAST_MASK_P4
     40#else
     41# error "Implement Pentium and P6 family APIC architectures"
     42#endif
    5043
    5144#define VMCPU_TO_XAPICPAGE(a_pVCpu)          ((PXAPICPAGE)(CTX_SUFF((a_pVCpu)->apic.s.pvApicPage)))
    … …  
    6760#define APICCPU_TO_CXAPICPAGE(a_ApicCpu)     ((PCXAPICPAGE)(CTX_SUFF((a_ApicCpu)->pvApicPage)))
    6861
     62/** Vector offset in an APIC 256-bit sparse register. */
     63#define XAPIC_REG256_VECTOR_OFF(a_Vector)    (((a_Vector) & UINT32_C(0xe0)) >> 1)
     64/** Bit position at offset in an APIC 256-bit sparse register. */
     65#define XAPIC_REG256_VECTOR_BIT(a_Vector)    ((a_Vector) & UINT32_C(0x1f))
     66
     67/** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */
     68#define XAPIC_OFF_MAX_VALID                  (sizeof(XAPICPAGE) - 4 * sizeof(uint32_t))
     69
    6970/** Whether the APIC is in X2APIC mode or not. */
    7071#define XAPIC_IN_X2APIC_MODE(a_pVCpu)        (   (  ((a_pVCpu)->apic.s.uApicBaseMsr) \
    7172                                                  & (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD)) \
    7273                                              ==    (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD) )
    73 
    74 /** Get an xAPIC page offset for an x2APIC MSR value. */
    75 #define X2APIC_GET_XAPIC_OFF(a_uMsr)         ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))
    76 /** Get an x2APIC MSR for an xAPIC page offset. */
    77 #define XAPIC_GET_X2APIC_MSR(a_offReg)       ((((a_offReg) & UINT32_C(0xff0)) >> 4) | MSR_IA32_X2APIC_START)
    78 
    79 /** Illegal APIC vector value start. */
    80 #define XAPIC_ILLEGAL_VECTOR_START           UINT8_C(0)
    81 /** Illegal APIC vector value end (inclusive). */
    82 #define XAPIC_ILLEGAL_VECTOR_END             UINT8_C(15)
    83 /** Reserved APIC vector value start. */
    84 #define XAPIC_RSVD_VECTOR_START              UINT8_C(16)
    85 /** Reserved APIC vector value end (inclusive). */
    86 #define XAPIC_RSVD_VECTOR_END                UINT8_C(31)
    87 
    88 /** Vector offset in an APIC 256-bit sparse register. */
    89 #define XAPIC_REG256_VECTOR_OFF(a_Vector)    (((a_Vector) & UINT32_C(0xe0)) >> 1)
    90 /** Bit position at offset in an APIC 256-bit sparse register. */
    91 #define XAPIC_REG256_VECTOR_BIT(a_Vector)    ((a_Vector) & UINT32_C(0x1f))
    92 
    93 /** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */
    94 #define XAPIC_OFF_MAX_VALID                  (sizeof(XAPICPAGE) - 4 * sizeof(uint32_t))
    95 
    96 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P6
    97 /** ESR - Send checksum error. */
    98 # define XAPIC_ESR_SEND_CHKSUM_ERROR         RT_BIT(0)
    99 /** ESR - Send accept error. */
    100 # define XAPIC_ESR_RECV_CHKSUM_ERROR         RT_BIT(1)
    101 /** ESR - Send accept error. */
    102 # define XAPIC_ESR_SEND_ACCEPT_ERROR         RT_BIT(2)
    103 /** ESR - Receive accept error. */
    104 # define XAPIC_ESR_RECV_ACCEPT_ERROR         RT_BIT(3)
    105 #endif
    106 /** ESR - Redirectable IPI. */
    107 #define XAPIC_ESR_REDIRECTABLE_IPI           RT_BIT(4)
    108 /** ESR - Send accept error. */
    109 #define XAPIC_ESR_SEND_ILLEGAL_VECTOR        RT_BIT(5)
    110 /** ESR - Send accept error. */
    111 #define XAPIC_ESR_RECV_ILLEGAL_VECTOR        RT_BIT(6)
    112 /** ESR - Send accept error. */
    113 #define XAPIC_ESR_ILLEGAL_REG_ADDRESS        RT_BIT(7)
    114 /** ESR - Valid write-only bits. */
    115 #define XAPIC_ESR_WO_VALID                   UINT32_C(0x0)
    116 
    117 /** TPR - Valid bits. */
    118 #define XAPIC_TPR_VALID                      UINT32_C(0xff)
    119 /** TPR - Task-priority class. */
    120 #define XAPIC_TPR_TP                         UINT32_C(0xf0)
    121 /** TPR - Task-priority subclass. */
    122 #define XAPIC_TPR_TP_SUBCLASS                UINT32_C(0x0f)
    123 /** TPR - Gets the task-priority class. */
    124 #define XAPIC_TPR_GET_TP(a_Tpr)              ((a_Tpr) & XAPIC_TPR_TP)
    125 /** TPR - Gets the task-priority subclass. */
    126 #define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr)     ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)
    127 
    128 /** PPR - Valid bits. */
    129 #define XAPIC_PPR_VALID                      UINT32_C(0xff)
    130 /** PPR - Processor-priority class. */
    131 #define XAPIC_PPR_PP                         UINT32_C(0xf0)
    132 /** PPR - Processor-priority subclass. */
    133 #define XAPIC_PPR_PP_SUBCLASS                UINT32_C(0x0f)
    134 /** PPR - Get the processor-priority class. */
    135 #define XAPIC_PPR_GET_PP(a_Ppr)              ((a_Ppr) & XAPIC_PPR_PP)
    136 /** PPR - Get the processor-priority subclass. */
    137 #define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr)     ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS)
    138 
    139 /** Timer mode - One-shot. */
    140 #define XAPIC_TIMER_MODE_ONESHOT             UINT32_C(0)
    141 /** Timer mode - Periodic. */
    142 #define XAPIC_TIMER_MODE_PERIODIC            UINT32_C(1)
    143 /** Timer mode - TSC deadline. */
    144 #define XAPIC_TIMER_MODE_TSC_DEADLINE        UINT32_C(2)
    145 
    146 /** LVT - The vector. */
    147 #define XAPIC_LVT_VECTOR                     UINT32_C(0xff)
    148 /** LVT - Gets the vector from an LVT entry. */
    149 #define XAPIC_LVT_GET_VECTOR(a_Lvt)          ((a_Lvt) & XAPIC_LVT_VECTOR)
    150 /** LVT - The mask. */
    151 #define XAPIC_LVT_MASK                       RT_BIT(16)
    152 /** LVT - Is the LVT masked? */
    153 #define XAPIC_LVT_IS_MASKED(a_Lvt)           RT_BOOL((a_Lvt) & XAPIC_LVT_MASK)
    154 /** LVT - Timer mode. */
    155 #define XAPIC_LVT_TIMER_MODE                 RT_BIT(17)
    156 /** LVT - Timer TSC-deadline timer mode. */
    157 #define XAPIC_LVT_TIMER_TSCDEADLINE          RT_BIT(18)
    158 /** LVT - Gets the timer mode. */
    159 #define XAPIC_LVT_GET_TIMER_MODE(a_Lvt)      (XAPICTIMERMODE)(((a_Lvt) >> 17) & UINT32_C(3))
    160 /** LVT - Delivery mode. */
    161 #define XAPIC_LVT_DELIVERY_MODE              (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
    162 /** LVT - Gets the delivery mode. */
    163 #define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt)   (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & UINT32_C(7))
    164 /** LVT - Delivery status. */
    165 #define XAPIC_LVT_DELIVERY_STATUS            RT_BIT(12)
    166 /** LVT - Trigger mode. */
    167 #define XAPIC_LVT_TRIGGER_MODE               RT_BIT(15)
    168 /** LVT - Gets the trigger mode. */
    169 #define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt)    (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & UINT32_C(1))
    170 /** LVT - Remote IRR. */
    171 #define XAPIC_LVT_REMOTE_IRR                 RT_BIT(14)
    172 /** LVT - Gets the Remote IRR. */
    173 #define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt)      (((a_Lvt) >> 14) & 1)
    174 /** LVT - Interrupt Input Pin Polarity. */
    175 #define XAPIC_LVT_POLARITY                   RT_BIT(13)
    176 /** LVT - Gets the Interrupt Input Pin Polarity. */
    177 #define XAPIC_LVT_GET_POLARITY(a_Lvt)        (((a_Lvt) >> 13) & 1)
    178 /** LVT - Valid bits common to all LVTs. */
    179 #define XAPIC_LVT_COMMON_VALID               (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
    180 /** LVT CMCI - Valid bits. */
    181 #define XAPIC_LVT_CMCI_VALID                 (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
    182 /** LVT Timer - Valid bits. */
    183 #define XAPIC_LVT_TIMER_VALID                (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
    184 /** LVT Thermal - Valid bits. */
    185 #define XAPIC_LVT_THERMAL_VALID              (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
    186 /** LVT Perf - Valid bits. */
    187 #define XAPIC_LVT_PERF_VALID                 (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
    188 /** LVT LINTx - Valid bits. */
    189 #define XAPIC_LVT_LINT_VALID                 (  XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
    190                                               | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)
    191 /** LVT Error - Valid bits. */
    192 #define XAPIC_LVT_ERROR_VALID                (XAPIC_LVT_COMMON_VALID)
    193 
    194 /** SVR - The vector. */
    195 #define XAPIC_SVR_VECTOR                     UINT32_C(0xff)
    196 /** SVR - APIC Software enable. */
    197 #define XAPIC_SVR_SOFTWARE_ENABLE            RT_BIT(8)
    198 /** SVR - Supress EOI broadcast. */
    199 #define XAPIC_SVR_SUPRESS_EOI_BROADCAST      RT_BIT(12)
    200 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
    201 /** SVR - Valid bits. */
    202 # define XAPIC_SVR_VALID                     (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
    203 #else
    204 # error "Implement Pentium and P6 family APIC architectures"
    205 #endif
    206 
    207 /** DFR - Valid bits. */
    208 #define XAPIC_DFR_VALID                      UINT32_C(0xf0000000)
    209 /** DFR - Reserved bits that must always remain set. */
    210 #define XAPIC_DFR_RSVD_MB1                   UINT32_C(0x0fffffff)
    211 /** DFR - The model. */
    212 #define XAPIC_DFR_MODEL                      UINT32_C(0xf)
    213 /** DFR - Gets the destination model. */
    214 #define XAPIC_DFR_GET_MODEL(a_uReg)          (((a_uReg) >> 28) & XAPIC_DFR_MODEL)
    215 
    216 /** LDR - Valid bits. */
    217 #define XAPIC_LDR_VALID                      UINT32_C(0xff000000)
    218 /** LDR - Cluster ID mask (x2APIC). */
    219 #define X2APIC_LDR_CLUSTER_ID                UINT32_C(0xffff0000)
    220 /** LDR - Mask of the LDR cluster ID (x2APIC). */
    221 #define X2APIC_LDR_GET_CLUSTER_ID(a_uReg)    ((a_uReg) & X2APIC_LDR_CLUSTER_ID)
    222 /** LDR - Mask of the LDR logical ID (x2APIC). */
    223 #define X2APIC_LDR_LOGICAL_ID                UINT32_C(0x0000ffff)
    224 
    225 /** LDR - Flat mode logical ID mask. */
    226 #define XAPIC_LDR_FLAT_LOGICAL_ID            UINT32_C(0xff)
    227 /** LDR - Clustered mode cluster ID mask. */
    228 #define XAPIC_LDR_CLUSTERED_CLUSTER_ID       UINT32_C(0xf0)
    229 /** LDR - Clustered mode logical ID mask. */
    230 #define XAPIC_LDR_CLUSTERED_LOGICAL_ID       UINT32_C(0x0f)
    231 /** LDR - Gets the clustered mode cluster ID. */
    232 #define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg)   ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID)
    233 
    234 
    235 /** EOI - Valid write-only bits. */
    236 #define XAPIC_EOI_WO_VALID                   UINT32_C(0x0)
    237 /** Timer ICR - Valid bits. */
    238 #define XAPIC_TIMER_ICR_VALID                UINT32_C(0xffffffff)
    239 /** Timer DCR - Valid bits. */
    240 #define XAPIC_TIMER_DCR_VALID                (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
    241 
    242 /** Self IPI - Valid bits. */
    243 #define XAPIC_SELF_IPI_VALID                 UINT32_C(0xff)
    244 /** Self IPI - The vector. */
    245 #define XAPIC_SELF_IPI_VECTOR                UINT32_C(0xff)
    246 /** Self IPI - Gets the vector. */
    247 #define XAPIC_SELF_IPI_GET_VECTOR(a_uReg)    ((a_uReg) & XAPIC_SELF_IPI_VECTOR)
    248 
    249 /** ICR Low - The Vector. */
    250 #define XAPIC_ICR_LO_VECTOR                  UINT32_C(0xff)
    251 /** ICR Low - Gets the vector. */
    252 #define XAPIC_ICR_LO_GET_VECTOR(a_uIcr)      ((a_uIcr) & XAPIC_ICR_LO_VECTOR)
    253 /** ICR Low - The delivery mode. */
    254 #define XAPIC_ICR_LO_DELIVERY_MODE           (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
    255 /** ICR Low - The destination mode. */
    256 #define XAPIC_ICR_LO_DEST_MODE               RT_BIT(11)
    257 /** ICR Low - The delivery status. */
    258 #define XAPIC_ICR_LO_DELIVERY_STATUS         RT_BIT(12)
    259 /** ICR Low - The level. */
    260 #define XAPIC_ICR_LO_LEVEL                   RT_BIT(14)
    261 /** ICR Low - The trigger mode. */
    262 #define XAPIC_ICR_TRIGGER_MODE               RT_BIT(15)
    263 /** ICR Low - The destination shorthand. */
    264 #define XAPIC_ICR_LO_DEST_SHORTHAND          (RT_BIT(18) | RT_BIT(19))
    265 /** ICR Low - Valid write bits. */
    266 #define XAPIC_ICR_LO_WR_VALID                (  XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
    267                                               | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)
    268 
    269 /** ICR High - The destination field. */
    270 #define XAPIC_ICR_HI_DEST                    UINT32_C(0xff000000)
    271 /** ICR High - Get the destination field. */
    272 #define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi)    (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)
    273 /** ICR High - Valid write bits in xAPIC mode. */
    274 #define XAPIC_ICR_HI_WR_VALID                XAPIC_ICR_HI_DEST
    275 
    276 /** APIC ID broadcast mask - x2APIC mode. */
    277 #define X2APIC_ID_BROADCAST_MASK             UINT32_C(0xffffffff)
    278 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
    279 /** APIC ID broadcast mask - xAPIC mode. */
    280 # define XAPIC_ID_BROADCAST_MASK             UINT32_C(0xff)
    281 #else
    282 # error "Implement Pentium and P6 family APIC architectures"
    283 #endif
    28474
    28575/**
    … …  
    1055845    APICMSRACCESS_COUNT
    1056846} APICMSRACCESS;
    1057 
    1058 /** @name xAPIC Destination Format Register bits.
    1059  * See Intel spec. 10.6.2.2 "Logical Destination Mode".
    1060  * @{ */
    1061 typedef enum XAPICDESTFORMAT
    1062 {
    1063     XAPICDESTFORMAT_FLAT    = 0xf,
    1064     XAPICDESTFORMAT_CLUSTER = 0
    1065 } XAPICDESTFORMAT;
    1066 /** @} */
    1067 
    1068 /** @name xAPIC Timer Mode bits.
    1069  * See Intel spec. 10.5.1 "Local Vector Table".
    1070  * @{ */
    1071 typedef enum XAPICTIMERMODE
    1072 {
    1073     XAPICTIMERMODE_ONESHOT      = XAPIC_TIMER_MODE_ONESHOT,
    1074     XAPICTIMERMODE_PERIODIC     = XAPIC_TIMER_MODE_PERIODIC,
    1075     XAPICTIMERMODE_TSC_DEADLINE = XAPIC_TIMER_MODE_TSC_DEADLINE
    1076 } XAPICTIMERMODE;
    1077 /** @} */
    1078 
    1079 /** @name xAPIC Interrupt Command Register bits.
    1080  * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)".
    1081  * See Intel spec. 10.5.1 "Local Vector Table".
    1082  * @{ */
    1083 /**
    1084  * xAPIC destination shorthand.
    1085  */
    1086 typedef enum XAPICDESTSHORTHAND
    1087 {
    1088     XAPICDESTSHORTHAND_NONE = 0,
    1089     XAPICDESTSHORTHAND_SELF,
    1090     XAPIDDESTSHORTHAND_ALL_INCL_SELF,
    1091     XAPICDESTSHORTHAND_ALL_EXCL_SELF
    1092 } XAPICDESTSHORTHAND;
    1093 
    1094 /**
    1095  * xAPIC INIT level de-assert delivery mode.
    1096  */
    1097 typedef enum XAPICINITLEVEL
    1098 {
    1099     XAPICINITLEVEL_DEASSERT = 0,
    1100     XAPICINITLEVEL_ASSERT
    1101 } XAPICLEVEL;
    1102 
    1103 /**
    1104  * xAPIC destination mode.
    1105  */
    1106 typedef enum XAPICDESTMODE
    1107 {
    1108     XAPICDESTMODE_PHYSICAL = 0,
    1109     XAPICDESTMODE_LOGICAL
    1110 } XAPICDESTMODE;
    1111 
    1112 /**
    1113  * xAPIC delivery mode type.
    1114  */
    1115 typedef enum XAPICDELIVERYMODE
    1116 {
    1117     XAPICDELIVERYMODE_FIXED               = 0,
    1118     XAPICDELIVERYMODE_LOWEST_PRIO         = 1,
    1119     XAPICDELIVERYMODE_SMI                 = 2,
    1120     XAPICDELIVERYMODE_NMI                 = 4,
    1121     XAPICDELIVERYMODE_INIT                = 5,
    1122     XAPICDELIVERYMODE_STARTUP             = 6,
    1123     XAPICDELIVERYMODE_EXTINT              = 7
    1124 } XAPICDELIVERYMODE;
    1125847/** @} */
    1126848
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