VirtualBox

Ignore:
Timestamp:
Jun 4, 2020 1:12:06 PM (4 years ago)
Author:
vboxsync
Message:

AMD IOMMU: bugref:9654 Add I/O APIC PDM helper for talking to the IOMMU for remapping MSIs and related bits.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/PC/DevIoApic.cpp

    r84666 r84677  
    432432     * See Intel spec. 10.11.2 "Message Data Register Format".
    433433     */
    434     pIntr->u8Dest         = pMsi->MsiAddr.n.u8DestId;
    435     pIntr->u8DestMode     = pMsi->MsiAddr.n.u1DestMode;
    436     pIntr->u8RedirHint    = pMsi->MsiAddr.n.u1RedirHint;
    437 
    438     pIntr->u8Vector       = pMsi->MsiData.n.u8Vector;
    439     pIntr->u8TriggerMode  = pMsi->MsiData.n.u1TriggerMode;
    440     pIntr->u8DeliveryMode = pMsi->MsiData.n.u3DeliveryMode;
     434    pIntr->u8Dest         = pMsi->Addr.n.u8DestId;
     435    pIntr->u8DestMode     = pMsi->Addr.n.u1DestMode;
     436    pIntr->u8RedirHint    = pMsi->Addr.n.u1RedirHint;
     437
     438    pIntr->u8Vector       = pMsi->Data.n.u8Vector;
     439    pIntr->u8TriggerMode  = pMsi->Data.n.u1TriggerMode;
     440    pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
    441441}
    442442
     
    450450DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
    451451{
    452     pMsi->MsiAddr.n.u12Addr        = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
    453     pMsi->MsiAddr.n.u8DestId       = pIntr->u8Dest;
    454     pMsi->MsiAddr.n.u1RedirHint    = pIntr->u8RedirHint;
    455     pMsi->MsiAddr.n.u1DestMode     = pIntr->u8DestMode;
    456 
    457     pMsi->MsiData.n.u8Vector       = pIntr->u8Vector;
    458     pMsi->MsiData.n.u3DeliveryMode = pIntr->u8DeliveryMode;
    459     pMsi->MsiData.n.u1TriggerMode  = pIntr->u8TriggerMode;
    460 
    461     /* pMsi->MsiData.n.u1Level     = ??? */
     452    pMsi->Addr.n.u12Addr        = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
     453    pMsi->Addr.n.u8DestId       = pIntr->u8Dest;
     454    pMsi->Addr.n.u1RedirHint    = pIntr->u8RedirHint;
     455    pMsi->Addr.n.u1DestMode     = pIntr->u8DestMode;
     456
     457    pMsi->Data.n.u8Vector       = pIntr->u8Vector;
     458    pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
     459    pMsi->Data.n.u1TriggerMode  = pIntr->u8TriggerMode;
     460
     461    /* pMsi->Data.n.u1Level     = ??? */
    462462    /** @todo r=ramshankar: Level triggered MSIs don't make much sense though
    463463     *        possible in theory? Maybe document this more explicitly... */
     
    855855    LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
    856856
    857     MSIMSG MsiMsg;
    858     MsiMsg.MsiAddr.u64 = GCPhys;
    859     MsiMsg.MsiData.u32 = uValue;
     857    MSIMSG Msi;
     858    Msi.Addr.u64 = GCPhys;
     859    Msi.Data.u32 = uValue;
    860860
    861861    XAPICINTR ApicIntr;
    862862    RT_ZERO(ApicIntr);
    863     ioapicGetApicIntrFromMsi(&MsiMsg, &ApicIntr);
     863    ioapicGetApicIntrFromMsi(&Msi, &ApicIntr);
    864864
    865865    /*
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