VirtualBox

Ignore:
Timestamp:
Aug 12, 2020 4:09:12 PM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
139865
Message:

Devices/EFI: Merge edk-stable202005 and make it build, bugref:4643

Location:
trunk/src/VBox/Devices/EFI/FirmwareNew
Files:
14 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/FirmwareNew

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c

    r80721 r85718  
    617617  PrepareApStartupVector (mAcpiCpuData.StartupVector);
    618618
    619   mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
     619  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
     620    ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
     621  } else {
     622    ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
     623  }
     624  mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
    620625  mExchangeInfo->ApFunction  = (VOID *) (UINTN) InitializeAp;
    621626
    … …  
    647652  )
    648653{
    649   mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
     654  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
     655    ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
     656  } else {
     657    ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
     658  }
     659  mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
    650660
    651661  //

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c

    r80721 r85718  
    337337  return ;
    338338}
     339
     340/**
     341  Return whether access to non-SMRAM is restricted.
     342
     343  @retval TRUE  Access to non-SMRAM is restricted.
     344  @retval FALSE Access to non-SMRAM is not restricted.
     345**/
     346BOOLEAN
     347IsRestrictedMemoryAccess (
     348  VOID
     349  )
     350{
     351  return TRUE;
     352}

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c

    r80721 r85718  
    22SMM MP service implementation
    33
    4 Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>
    55Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
    66
    … …  
    138138  UINTN                             Index;
    139139
    140   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     140  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    141141    if (IsPresentAp (Index)) {
    142142      ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run);
    … …  
    171171  CpuData = mSmmMpSyncData->CpuData;
    172172  ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;
    173   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     173  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    174174    if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
    175175      if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) {
    … …  
    306306    // Send SMI IPIs to bring outside processors in
    307307    //
    308     for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     308    for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    309309      if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
    310310        SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
    … …  
    362362  UINTN                             Index;
    363363
    364   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     364  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    365365    //
    366366    // Ignore BSP and APs which not call in SMM.
    … …  
    404404
    405405/**
    406   Check whether execute in single AP or all APs.
    407 
    408   Compare two Tokens used by different APs to know whether in StartAllAps call.
    409 
    410   Whether is an valid AP base on AP's Present flag.
    411 
    412   @retval  TRUE      IN StartAllAps call.
    413   @retval  FALSE     Not in StartAllAps call.
    414 
    415 **/
    416 BOOLEAN
    417 InStartAllApsCall (
    418   VOID
    419   )
    420 {
    421   UINTN      ApIndex;
    422   UINTN      ApIndex2;
    423 
    424   for (ApIndex = mMaxNumberOfCpus; ApIndex-- > 0;) {
    425     if (IsPresentAp (ApIndex) && (mSmmMpSyncData->CpuData[ApIndex].Token != NULL)) {
    426       for (ApIndex2 = ApIndex; ApIndex2-- > 0;) {
    427         if (IsPresentAp (ApIndex2) && (mSmmMpSyncData->CpuData[ApIndex2].Token != NULL)) {
    428           return mSmmMpSyncData->CpuData[ApIndex2].Token == mSmmMpSyncData->CpuData[ApIndex].Token;
    429         }
    430       }
    431     }
    432   }
    433 
    434   return FALSE;
    435 }
    436 
    437 /**
    438406  Clean up the status flags used during executing the procedure.
    439407
    … …  
    446414  )
    447415{
    448   UINTN                             Index;
    449   BOOLEAN                           Released;
    450 
    451   if (InStartAllApsCall ()) {
    452     //
    453     // In Start All APs mode, make sure all APs have finished task.
    454     //
    455     if (WaitForAllAPsNotBusy (FALSE)) {
    456       //
    457       // Clean the flags update in the function call.
    458       //
    459       Released = FALSE;
    460       for (Index = mMaxNumberOfCpus; Index-- > 0;) {
    461         //
    462         // Only In SMM APs need to be clean up.
    463         //
    464         if (mSmmMpSyncData->CpuData[Index].Present && mSmmMpSyncData->CpuData[Index].Token != NULL) {
    465           if (!Released) {
    466             ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Token);
    467             Released = TRUE;
    468           }
    469           mSmmMpSyncData->CpuData[Index].Token = NULL;
    470         }
    471       }
    472     }
    473   } else {
    474     //
    475     // In single AP mode.
    476     //
    477     if (mSmmMpSyncData->CpuData[CpuIndex].Token != NULL) {
    478       ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Token);
    479       mSmmMpSyncData->CpuData[CpuIndex].Token = NULL;
    480     }
    481   }
     416  PROCEDURE_TOKEN                         *Token;
     417
     418  Token = mSmmMpSyncData->CpuData[CpuIndex].Token;
     419
     420  if (InterlockedDecrement (&Token->RunningApCount) == 0) {
     421    ReleaseSpinLock (Token->SpinLock);
     422  }
     423
     424  mSmmMpSyncData->CpuData[CpuIndex].Token = NULL;
    482425}
    483426
    … …  
    487430**/
    488431VOID
    489 FreeTokens (
     432ResetTokens (
    490433  VOID
    491434  )
    492435{
    493   LIST_ENTRY            *Link;
    494   PROCEDURE_TOKEN       *ProcToken;
    495 
    496   while (!IsListEmpty (&gSmmCpuPrivate->TokenList)) {
    497     Link = GetFirstNode (&gSmmCpuPrivate->TokenList);
    498     ProcToken = PROCEDURE_TOKEN_FROM_LINK (Link);
    499 
    500     RemoveEntryList (&ProcToken->Link);
    501 
    502     FreePool ((VOID *)ProcToken->ProcedureToken);
    503     FreePool (ProcToken);
    504   }
     436  //
     437  // Reset the FirstFreeToken to the beginning of token list upon exiting SMI.
     438  //
     439  gSmmCpuPrivate->FirstFreeToken = GetFirstNode (&gSmmCpuPrivate->TokenList);
    505440}
    506441
    … …  
    658593    while (TRUE) {
    659594      PresentCount = 0;
    660       for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     595      for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    661596        if (*(mSmmMpSyncData->CpuData[Index].Present)) {
    662597          PresentCount ++;
    … …  
    726661
    727662  //
    728   // Clean the tokens buffer.
    729   //
    730   FreeTokens ();
     663  // Reset the tokens buffer.
     664  //
     665  ResetTokens ();
    731666
    732667  //
    … …  
    896831    }
    897832
     833    if (mSmmMpSyncData->CpuData[CpuIndex].Token != NULL) {
     834      ReleaseToken (CpuIndex);
     835    }
     836
    898837    //
    899838    // Release BUSY
    900839    //
    901840    ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
    902 
    903     ReleaseToken (CpuIndex);
    904841  }
    905842
    … …  
    10921029
    10931030  Link = GetFirstNode (&gSmmCpuPrivate->TokenList);
    1094   while (!IsNull (&gSmmCpuPrivate->TokenList, Link)) {
     1031  //
     1032  // Only search used tokens.
     1033  //
     1034  while (Link != gSmmCpuPrivate->FirstFreeToken) {
    10951035    ProcToken = PROCEDURE_TOKEN_FROM_LINK (Link);
    10961036
    1097     if (ProcToken->ProcedureToken == Token) {
     1037    if (ProcToken->SpinLock == Token) {
    10981038      return TRUE;
    10991039    }
    … …  
    11061046
    11071047/**
    1108   create token and save it to the maintain list.
    1109 
    1110   @retval    return the spin lock used as token.
    1111 
    1112 **/
    1113 SPIN_LOCK *
    1114 CreateToken (
     1048  Allocate buffer for the SPIN_LOCK and PROCEDURE_TOKEN.
     1049
     1050  @return First token of the token buffer.
     1051**/
     1052LIST_ENTRY *
     1053AllocateTokenBuffer (
    11151054  VOID
    11161055  )
    11171056{
    1118   PROCEDURE_TOKEN    *ProcToken;
    1119   SPIN_LOCK           *CpuToken;
    11201057  UINTN               SpinLockSize;
     1058  UINT32              TokenCountPerChunk;
     1059  UINTN               Index;
     1060  SPIN_LOCK           *SpinLock;
     1061  UINT8               *SpinLockBuffer;
     1062  PROCEDURE_TOKEN     *ProcTokens;
    11211063
    11221064  SpinLockSize = GetSpinLockProperties ();
    1123   CpuToken = AllocatePool (SpinLockSize);
    1124   ASSERT (CpuToken != NULL);
    1125   InitializeSpinLock (CpuToken);
    1126   AcquireSpinLock (CpuToken);
    1127 
    1128   ProcToken = AllocatePool (sizeof (PROCEDURE_TOKEN));
    1129   ASSERT (ProcToken != NULL);
    1130   ProcToken->Signature = PROCEDURE_TOKEN_SIGNATURE;
    1131   ProcToken->ProcedureToken = CpuToken;
    1132 
    1133   InsertTailList (&gSmmCpuPrivate->TokenList, &ProcToken->Link);
    1134 
    1135   return CpuToken;
     1065
     1066  TokenCountPerChunk = FixedPcdGet32 (PcdCpuSmmMpTokenCountPerChunk);
     1067  ASSERT (TokenCountPerChunk != 0);
     1068  if (TokenCountPerChunk == 0) {
     1069    DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n"));
     1070    CpuDeadLoop ();
     1071  }
     1072  DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk));
     1073
     1074  //
     1075  // Separate the Spin_lock and Proc_token because the alignment requires by Spin_Lock.
     1076  //
     1077  SpinLockBuffer = AllocatePool (SpinLockSize * TokenCountPerChunk);
     1078  ASSERT (SpinLockBuffer != NULL);
     1079
     1080  ProcTokens = AllocatePool (sizeof (PROCEDURE_TOKEN) * TokenCountPerChunk);
     1081  ASSERT (ProcTokens != NULL);
     1082
     1083  for (Index = 0; Index < TokenCountPerChunk; Index++) {
     1084    SpinLock = (SPIN_LOCK *)(SpinLockBuffer + SpinLockSize * Index);
     1085    InitializeSpinLock (SpinLock);
     1086
     1087    ProcTokens[Index].Signature      = PROCEDURE_TOKEN_SIGNATURE;
     1088    ProcTokens[Index].SpinLock       = SpinLock;
     1089    ProcTokens[Index].RunningApCount = 0;
     1090
     1091    InsertTailList (&gSmmCpuPrivate->TokenList, &ProcTokens[Index].Link);
     1092  }
     1093
     1094  return &ProcTokens[0].Link;
     1095}
     1096
     1097/**
     1098  Get the free token.
     1099
     1100  If no free token, allocate new tokens then return the free one.
     1101
     1102  @param RunningApsCount    The Running Aps count for this token.
     1103
     1104  @retval    return the first free PROCEDURE_TOKEN.
     1105
     1106**/
     1107PROCEDURE_TOKEN *
     1108GetFreeToken (
     1109  IN UINT32       RunningApsCount
     1110  )
     1111{
     1112  PROCEDURE_TOKEN  *NewToken;
     1113
     1114  //
     1115  // If FirstFreeToken meets the end of token list, enlarge the token list.
     1116  // Set FirstFreeToken to the first free token.
     1117  //
     1118  if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) {
     1119    gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();
     1120  }
     1121  NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);
     1122  gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken);
     1123
     1124  NewToken->RunningApCount = RunningApsCount;
     1125  AcquireSpinLock (NewToken->SpinLock);
     1126
     1127  return NewToken;
    11361128}
    11371129
    … …  
    12061198  )
    12071199{
     1200  PROCEDURE_TOKEN    *ProcToken;
     1201
    12081202  if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) {
    12091203    DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
    … …  
    12361230  }
    12371231
    1238   if (Token == NULL) {
    1239     AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
    1240   } else {
    1241     if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy)) {
    1242       DEBUG((DEBUG_ERROR, "Can't acquire mSmmMpSyncData->CpuData[%d].Busy\n", CpuIndex));
    1243       return EFI_NOT_READY;
    1244     }
    1245 
    1246     *Token = (MM_COMPLETION) CreateToken ();
    1247   }
     1232  AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
    12481233
    12491234  mSmmMpSyncData->CpuData[CpuIndex].Procedure = Procedure;
    12501235  mSmmMpSyncData->CpuData[CpuIndex].Parameter = ProcArguments;
    12511236  if (Token != NULL) {
    1252     mSmmMpSyncData->CpuData[CpuIndex].Token   = (SPIN_LOCK *)(*Token);
     1237    ProcToken= GetFreeToken (1);
     1238    mSmmMpSyncData->CpuData[CpuIndex].Token = ProcToken;
     1239    *Token = (MM_COMPLETION)ProcToken->SpinLock;
    12531240  }
    12541241  mSmmMpSyncData->CpuData[CpuIndex].Status    = CpuStatus;
    … …  
    13081295  UINTN               Index;
    13091296  UINTN               CpuCount;
     1297  PROCEDURE_TOKEN     *ProcToken;
    13101298
    13111299  if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
    … …  
    13171305
    13181306  CpuCount = 0;
    1319   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     1307  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    13201308    if (IsPresentAp (Index)) {
    13211309      CpuCount ++;
    … …  
    13361324
    13371325  if (Token != NULL) {
    1338     *Token = (MM_COMPLETION) CreateToken ();
     1326    ProcToken = GetFreeToken ((UINT32)mMaxNumberOfCpus);
     1327    *Token = (MM_COMPLETION)ProcToken->SpinLock;
     1328  } else {
     1329    ProcToken = NULL;
    13391330  }
    13401331
    … …  
    13461337  // block mode.
    13471338  //
    1348   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     1339  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    13491340    if (IsPresentAp (Index)) {
    13501341      AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
    … …  
    13521343  }
    13531344
    1354   for (Index = mMaxNumberOfCpus; Index-- > 0;) {
     1345  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
    13551346    if (IsPresentAp (Index)) {
    13561347      mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2) Procedure;
    13571348      mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments;
    1358       if (Token != NULL) {
    1359         mSmmMpSyncData->CpuData[Index].Token   = (SPIN_LOCK *)(*Token);
     1349      if (ProcToken != NULL) {
     1350        mSmmMpSyncData->CpuData[Index].Token   = ProcToken;
    13601351      }
    13611352      if (CPUStatus != NULL) {
    … …  
    13721363      if (CPUStatus != NULL) {
    13731364        CPUStatus[Index] = EFI_NOT_STARTED;
     1365      }
     1366
     1367      //
     1368      // Decrease the count to mark this processor(AP or BSP) as finished.
     1369      //
     1370      if (ProcToken != NULL) {
     1371        WaitForSemaphore (&ProcToken->RunningApCount);
    13741372      }
    13751373    }
    … …  
    17421740
    17431741  InitializeListHead (&gSmmCpuPrivate->TokenList);
     1742
     1743  gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();
    17441744}
    17451745

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c

    r80721 r85718  
    216216  @retval EFI_SUCCESS   The register was read from Save State
    217217  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
    218   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
     218  @retval EFI_INVALID_PARAMETER   This or Buffer is NULL.
    219219
    220220**/
    … …  
    288288  @retval EFI_SUCCESS   The register was written from Save State
    289289  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
    290   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
     290  @retval EFI_INVALID_PARAMETER   ProcessorIndex or Width is not correct
    291291
    292292**/
    … …  
    14321432    SetMemMapAttributes ();
    14331433
    1434     //
    1435     // For outside SMRAM, we only map SMM communication buffer or MMIO.
    1436     //
    1437     SetUefiMemMapAttributes ();
    1438 
    1439     //
    1440     // Set page table itself to be read-only
    1441     //
    1442     SetPageTableAttributes ();
     1434    if (IsRestrictedMemoryAccess ()) {
     1435      //
     1436      // For outside SMRAM, we only map SMM communication buffer or MMIO.
     1437      //
     1438      SetUefiMemMapAttributes ();
     1439
     1440      //
     1441      // Set page table itself to be read-only
     1442      //
     1443      SetPageTableAttributes ();
     1444    }
    14431445
    14441446    //

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

    r80721 r85718  
    22Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
    33
    4 Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
     4Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>
    55Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
    66
    … …  
    213213  LIST_ENTRY              Link;
    214214
    215   SPIN_LOCK               *ProcedureToken;
     215  SPIN_LOCK               *SpinLock;
     216  volatile UINT32         RunningApCount;
    216217} PROCEDURE_TOKEN;
    217218
    218219#define PROCEDURE_TOKEN_FROM_LINK(a)  CR (a, PROCEDURE_TOKEN, Link, PROCEDURE_TOKEN_SIGNATURE)
     220
     221#define TOKEN_BUFFER_SIGNATURE  SIGNATURE_32 ('T', 'K', 'B', 'S')
     222
     223typedef struct {
     224  UINTN                   Signature;
     225  LIST_ENTRY              Link;
     226
     227  UINT8                   *Buffer;
     228} TOKEN_BUFFER;
     229
     230#define TOKEN_BUFFER_FROM_LINK(a)  CR (a, TOKEN_BUFFER, Link, TOKEN_BUFFER_SIGNATURE)
    219231
    220232//
    … …  
    243255  PROCEDURE_WRAPPER               *ApWrapperFunc;
    244256  LIST_ENTRY                      TokenList;
    245 
     257  LIST_ENTRY                      *FirstFreeToken;
    246258} SMM_CPU_PRIVATE_DATA;
    247259
    … …  
    273285  @retval EFI_SUCCESS   The register was read from Save State
    274286  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
    275   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
     287  @retval EFI_INVALID_PARAMETER   This or Buffer is NULL.
    276288
    277289**/
    … …  
    297309  @retval EFI_SUCCESS   The register was written from Save State
    298310  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
    299   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
     311  @retval EFI_INVALID_PARAMETER   ProcessorIndex or Width is not correct
    300312
    301313**/
    … …  
    325337@retval EFI_SUCCESS           The register was read from Save State.
    326338@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
    327 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
     339@retval EFI_INVALID_PARAMETER  This or Buffer is NULL.
    328340
    329341**/
    … …  
    352364@retval EFI_SUCCESS           The register was written to Save State.
    353365@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
    354 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
     366@retval EFI_INVALID_PARAMETER  ProcessorIndex or Width is not correct.
    355367
    356368**/
    … …  
    393405  volatile UINT32                   *Run;
    394406  volatile BOOLEAN                  *Present;
    395   SPIN_LOCK                         *Token;
     407  PROCEDURE_TOKEN                   *Token;
    396408  EFI_STATUS                        *Status;
    397409} SMM_CPU_DATA_BLOCK;
    … …  
    12521264/**
    12531265  This function fixes up the address of the global variable or function
    1254   referred in SmmInit assembly files to be the absoute address.
     1266  referred in SmmInit assembly files to be the absolute address.
    12551267**/
    12561268VOID
    … …  
    12611273/**
    12621274  This function fixes up the address of the global variable or function
    1263   referred in SmiEntry assembly files to be the absoute address.
     1275  referred in SmiEntry assembly files to be the absolute address.
    12641276**/
    12651277VOID
    … …  
    14511463  );
    14521464
     1465/**
     1466  Return whether access to non-SMRAM is restricted.
     1467
     1468  @retval TRUE  Access to non-SMRAM is restricted.
     1469  @retval FALSE Access to non-SMRAM is not restricted.
     1470**/
     1471BOOLEAN
     1472IsRestrictedMemoryAccess (
     1473  VOID
     1474  );
     1475
    14531476#endif

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf

    r80721 r85718  
    134134  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable         ## CONSUMES
    135135  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode                      ## CONSUMES
    136   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable               ## CONSUMES
    137136  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize               ## SOMETIMES_CONSUMES
    138137  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable                   ## CONSUMES
    … …  
    142141  gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask        ## CONSUMES
    143142
     143[FixedPcd]
     144  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk               ## CONSUMES
     145
     146[Pcd.X64]
     147  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess        ## CONSUMES
     148
    144149[Depex]
    145150  gEfiMpServiceProtocolGuid

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c

    r80721 r85718  
    466466
    467467  //
    468   // Below logic is to check 2M/4K page to make sure we donot waist memory.
     468  // Below logic is to check 2M/4K page to make sure we do not waste memory.
    469469  //
    470470  while (Length != 0) {
    … …  
    10661066
    10671067/**
    1068   Merge continous memory map entries whose type is
     1068  Merge continuous memory map entries whose type is
    10691069  EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory,
    10701070  EfiUnusableMemory, EfiACPIReclaimMemory, because the memory described by

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c

    r80721 r85718  
    658658            ASSERT (Pt != NULL);
    659659
    660             *Pd = (UINTN) Pt | IA32_PG_RW | IA32_PG_P;
    661 
    662660            // Split it
    663             for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {
    664               *Pt = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
     661            for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {
     662              Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
    665663            } // end for PT
    666664            *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c

    r80721 r85718  
    261261  @retval EFI_SUCCESS           The register was read from Save State.
    262262  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
    263   @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
     263  @retval EFI_INVALID_PARAMETER  This or Buffer is NULL.
    264264
    265265**/
    … …  
    344344  @retval EFI_SUCCESS           The register was read from Save State.
    345345  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
    346   @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
     346  @retval EFI_INVALID_PARAMETER  This or Buffer is NULL.
    347347
    348348**/
    … …  
    456456  @retval EFI_SUCCESS           The register was written to Save State.
    457457  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
    458   @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
     458  @retval EFI_INVALID_PARAMETER  ProcessorIndex or Width is not correct.
    459459
    460460**/

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c

    r80721 r85718  
    1616LIST_ENTRY                          mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);
    1717BOOLEAN                             m1GPageTableSupport = FALSE;
    18 BOOLEAN                             mCpuSmmStaticPageTable;
    19 BOOLEAN                             m5LevelPagingSupport;
    20 X86_ASSEMBLY_PATCH_LABEL            gPatch5LevelPagingSupport;
     18BOOLEAN                             mCpuSmmRestrictedMemoryAccess;
     19BOOLEAN                             m5LevelPagingNeeded;
     20X86_ASSEMBLY_PATCH_LABEL            gPatch5LevelPagingNeeded;
    2121
    2222/**
    … …  
    6464
    6565/**
    66   Check if 5-level paging is supported by processor or not.
    67 
    68   @retval TRUE   5-level paging is supported.
    69   @retval FALSE  5-level paging is not supported.
    70 
     66  The routine returns TRUE when CPU supports it (CPUID[7,0].ECX.BIT[16] is set) and
     67  the max physical address bits is bigger than 48. Because 4-level paging can support
     68  to address physical address up to 2^48 - 1, there is no need to enable 5-level paging
     69  with max physical address bits <= 48.
     70
     71  @retval TRUE  5-level paging enabling is needed.
     72  @retval FALSE 5-level paging enabling is not needed.
    7173**/
    7274BOOLEAN
    73 Is5LevelPagingSupport (
     75Is5LevelPagingNeeded (
    7476  VOID
    7577  )
    7678{
    77   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;
    78 
     79  CPUID_VIR_PHY_ADDRESS_SIZE_EAX              VirPhyAddressSize;
     80  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx;
     81  UINT32                                      MaxExtendedFunctionId;
     82
     83  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL);
     84  if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) {
     85    AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
     86  } else {
     87    VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
     88  }
    7989  AsmCpuidEx (
    8090    CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
    8191    CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
    82     NULL,
    83     NULL,
    84     &EcxFlags.Uint32,
    85     NULL
     92    NULL, NULL, &ExtFeatureEcx.Uint32, NULL
    8693    );
    87   return (BOOLEAN) (EcxFlags.Bits.FiveLevelPage != 0);
     94  DEBUG ((
     95    DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n",
     96    VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage
     97    ));
     98
     99  if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
     100    ASSERT (ExtFeatureEcx.Bits.FiveLevelPage == 1);
     101    return TRUE;
     102  } else {
     103    return FALSE;
     104  }
    88105}
    89106
    … …  
    191208  //
    192209  ASSERT (mPhysicalAddressBits <= 52);
    193   if (!m5LevelPagingSupport && mPhysicalAddressBits > 48) {
     210  if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) {
    194211    mPhysicalAddressBits = 48;
    195212  }
    … …  
    218235  PageMapLevel4Entry = PageMap;
    219236  PageMapLevel5Entry = NULL;
    220   if (m5LevelPagingSupport) {
     237  if (m5LevelPagingNeeded) {
    221238    //
    222239    // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
    … …  
    234251    // When 5-Level Paging is disabled, below allocation happens only once.
    235252    //
    236     if (m5LevelPagingSupport) {
     253    if (m5LevelPagingNeeded) {
    237254      PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);
    238255      if (PageMapLevel4Entry == NULL) {
    … …  
    335352  InitializeSpinLock (mPFLock);
    336353
    337   mCpuSmmStaticPageTable = PcdGetBool (PcdCpuSmmStaticPageTable);
    338   m1GPageTableSupport    = Is1GPageSupport ();
    339   m5LevelPagingSupport   = Is5LevelPagingSupport ();
    340   mPhysicalAddressBits   = CalculateMaximumSupportAddress ();
    341   PatchInstructionX86 (gPatch5LevelPagingSupport, m5LevelPagingSupport, 1);
    342   DEBUG ((DEBUG_INFO, "5LevelPaging Support     - %d\n", m5LevelPagingSupport));
    343   DEBUG ((DEBUG_INFO, "1GPageTable Support      - %d\n", m1GPageTableSupport));
    344   DEBUG ((DEBUG_INFO, "PcdCpuSmmStaticPageTable - %d\n", mCpuSmmStaticPageTable));
    345   DEBUG ((DEBUG_INFO, "PhysicalAddressBits      - %d\n", mPhysicalAddressBits));
     354  mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess);
     355  m1GPageTableSupport           = Is1GPageSupport ();
     356  m5LevelPagingNeeded           = Is5LevelPagingNeeded ();
     357  mPhysicalAddressBits          = CalculateMaximumSupportAddress ();
     358  PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1);
     359  DEBUG ((DEBUG_INFO, "5LevelPaging Needed             - %d\n", m5LevelPagingNeeded));
     360  DEBUG ((DEBUG_INFO, "1GPageTable Support             - %d\n", m1GPageTableSupport));
     361  DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRestrictedMemoryAccess));
     362  DEBUG ((DEBUG_INFO, "PhysicalAddressBits             - %d\n", mPhysicalAddressBits));
    346363  //
    347364  // Generate PAE page table for the first 4GB memory space
    … …  
    371388  PTEntry = Pml4Entry;
    372389
    373   if (m5LevelPagingSupport) {
     390  if (m5LevelPagingNeeded) {
    374391    //
    375392    // Fill PML5 entry
    … …  
    386403  }
    387404
    388   if (mCpuSmmStaticPageTable) {
     405  if (mCpuSmmRestrictedMemoryAccess) {
     406    //
     407    // When access to non-SMRAM memory is restricted, create page table
     408    // that covers all memory space.
     409    //
    389410    SetStaticPageTable ((UINTN)PTEntry);
    390411  } else {
    … …  
    973994  PFAddress = AsmReadCr2 ();
    974995
    975   if (mCpuSmmStaticPageTable && (PFAddress >= LShiftU64 (1, (mPhysicalAddressBits - 1)))) {
     996  if (mCpuSmmRestrictedMemoryAccess && (PFAddress >= LShiftU64 (1, (mPhysicalAddressBits - 1)))) {
    976997    DumpCpuContext (InterruptType, SystemContext);
    977998    DEBUG ((DEBUG_ERROR, "Do not support address 0x%lx by processor!\n", PFAddress));
    … …  
    10501071    }
    10511072
    1052     if (mCpuSmmStaticPageTable && IsSmmCommBufferForbiddenAddress (PFAddress)) {
     1073    if (mCpuSmmRestrictedMemoryAccess && IsSmmCommBufferForbiddenAddress (PFAddress)) {
    10531074      DumpCpuContext (InterruptType, SystemContext);
    10541075      DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress));
    … …  
    11011122
    11021123  //
    1103   // Don't do this if
    1104   //  - no static page table; or
     1124  // Don't mark page table memory as read-only if
     1125  //  - no restriction on access to non-SMRAM memory; or
    11051126  //  - SMM heap guard feature enabled; or
    11061127  //      BIT2: SMM page guard enabled
    … …  
    11081129  //  - SMM profile feature enabled
    11091130  //
    1110   if (!mCpuSmmStaticPageTable ||
     1131  if (!mCpuSmmRestrictedMemoryAccess ||
    11111132      ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
    11121133      FeaturePcdGet (PcdCpuSmmProfileEnable)) {
    11131134    //
    1114     // Static paging and heap guard could not be enabled at the same time.
    1115     //
    1116     ASSERT (!(mCpuSmmStaticPageTable &&
     1135    // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
     1136    //
     1137    ASSERT (!(mCpuSmmRestrictedMemoryAccess &&
    11171138              (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0));
    11181139
    11191140    //
    1120     // Static paging and SMM profile could not be enabled at the same time.
    1121     //
    1122     ASSERT (!(mCpuSmmStaticPageTable && FeaturePcdGet (PcdCpuSmmProfileEnable)));
     1141    // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
     1142    //
     1143    ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));
    11231144    return ;
    11241145  }
    … …  
    12241245  )
    12251246{
    1226   if (!mCpuSmmStaticPageTable) {
     1247  if (!mCpuSmmRestrictedMemoryAccess) {
     1248    //
     1249    // On-demand paging is enabled when access to non-SMRAM is not restricted.
     1250    //
    12271251    *Cr2 = AsmReadCr2 ();
    12281252  }
    … …  
    12391263  )
    12401264{
    1241   if (!mCpuSmmStaticPageTable) {
     1265  if (!mCpuSmmRestrictedMemoryAccess) {
     1266    //
     1267    // On-demand paging is enabled when access to non-SMRAM is not restricted.
     1268    //
    12421269    AsmWriteCr2 (Cr2);
    12431270  }
    12441271}
     1272
     1273/**
     1274  Return whether access to non-SMRAM is restricted.
     1275
     1276  @retval TRUE  Access to non-SMRAM is restricted.
     1277  @retval FALSE Access to non-SMRAM is not restricted.
     1278**/
     1279BOOLEAN
     1280IsRestrictedMemoryAccess (
     1281  VOID
     1282  )
     1283{
     1284  return mCpuSmmRestrictedMemoryAccess;
     1285}

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c

    r80721 r85718  
    5959
    6060  //
    61   // Use temp value to fix ICC complier warning
     61  // Use temp value to fix ICC compiler warning
    6262  //
    6363  TempValue = (UINTN)&mSmmRelocationOriginalAddress;

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm

    r80721 r85718  
    1717
    1818;
    19 ; Variables referrenced by C code
     19; Variables referenced by C code
    2020;
    2121
    … …  
    7070global ASM_PFX(gPatchSmiStack)
    7171global ASM_PFX(gPatchSmiCr3)
    72 global ASM_PFX(gPatch5LevelPagingSupport)
     72global ASM_PFX(gPatch5LevelPagingNeeded)
    7373global ASM_PFX(gcSmiHandlerTemplate)
    7474global ASM_PFX(gcSmiHandlerSize)
    … …  
    128128
    129129    mov     cl, strict byte 0            ; source operand will be patched
    130 ASM_PFX(gPatch5LevelPagingSupport):
     130ASM_PFX(gPatch5LevelPagingNeeded):
    131131    cmp     cl, 0
    132132    je      SkipEnable5LevelPaging

  • trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

    r80721 r85718  
    7373    and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
    7474    ;
    75     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
     75    ; According to X64 calling convention, XMM0~5 are volatile, we need to save
    7676    ; them before calling C-function.
    7777    ;
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