- Timestamp:
- Sep 10, 2020 5:52:45 PM (4 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r86084 r86087 27 27 28 28 #include <iprt/x86.h> 29 #include <iprt/alloc.h> 29 30 #include <iprt/string.h> 30 31 … … 3184 3185 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); 3185 3186 3186 LogFlowFunc(("pThis=%p pszArgs=%s\n", pThis, pszArgs));3187 3187 bool fVerbose; 3188 3188 if ( pszArgs … … 3734 3734 3735 3735 3736 static void iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix) 3737 { 3738 RT_NOREF(pDevIns); 3739 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid); 3740 pHlp->pfnPrintf(pHlp, " %sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid); 3741 } 3742 3743 3744 /** 3745 * @callback_method_impl{FNDBGFHANDLERDEV} 3746 */ 3747 static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 3748 { 3749 RT_NOREF(pszArgs); 3750 3751 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 3752 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 3753 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); 3754 3755 uint8_t cTables = 0; 3756 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++) 3757 { 3758 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i]; 3759 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT; 3760 if (GCPhysDevTab) 3761 ++cTables; 3762 } 3763 3764 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n"); 3765 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables); 3766 if (!cTables) 3767 return; 3768 3769 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++) 3770 { 3771 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i]; 3772 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT; 3773 if (GCPhysDevTab) 3774 { 3775 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size); 3776 uint32_t const cDtes = cbDevTab / sizeof(DTE_T); 3777 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes); 3778 3779 void *pvDevTab = RTMemAllocZ(cbDevTab); 3780 if (RT_LIKELY(pvDevTab)) 3781 { 3782 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab); 3783 if (RT_SUCCESS(rc)) 3784 { 3785 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++) 3786 { 3787 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T)); 3788 if ( pDte->n.u1Valid 3789 || pDte->n.u1IntrMapValid) 3790 { 3791 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte); 3792 iommuAmdR3DbgInfoDte(pDevIns, pHlp, pDte, " "); 3793 } 3794 } 3795 pHlp->pfnPrintf(pHlp, "\n"); 3796 } 3797 else 3798 { 3799 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab, 3800 cbDevTab, rc); 3801 } 3802 3803 RTMemFree(pvDevTab); 3804 } 3805 else 3806 { 3807 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab); 3808 return; 3809 } 3810 } 3811 } 3812 3813 } 3814 3815 3736 3816 /** 3737 3817 * @callback_method_impl{FNSSMDEVSAVEEXEC} … … 4032 4112 4033 4113 /* 4034 * Register debugger info item .4114 * Register debugger info items. 4035 4115 */ 4036 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu","Display IOMMU state.", iommuAmdR3DbgInfo);4037 AssertLogRelRCReturn(rc, rc);4116 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo); 4117 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs); 4038 4118 4039 4119 # ifdef VBOX_WITH_STATISTICS
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