Changeset 86661 in vbox for trunk/include/VBox
- Timestamp:
- Oct 21, 2020 11:39:04 AM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 141037
- File:
-
- 1 edited
-
trunk/include/VBox/vmm/pdmdev.h (modified) (10 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/pdmdev.h
r86621 r86661 1257 1257 1258 1258 1259 /** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags. 1260 * These flags are used for memory access transactions via the IOMMU interface. 1261 * @{ */ 1262 /** Memory read. */ 1263 #define PDMIOMMU_MEM_F_READ RT_BIT_32(0) 1264 /** Memory write. */ 1265 #define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1) 1266 /** Valid flag mask. */ 1267 #define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ | PDMIOMMU_MEM_F_WRITE) 1268 /** @} */ 1269 1259 1270 /** 1260 1271 * IOMMU registration structure for ring-0. … … 1269 1280 1270 1281 /** 1271 * Translates the physical address for a memory readtransaction through the IOMMU.1282 * Translates the physical address for a memory transaction through the IOMMU. 1272 1283 * 1273 1284 * @returns VBox status code. 1274 1285 * @param pDevIns The IOMMU device instance. 1275 1286 * @param uDevId The device identifier (bus, device, function). 1276 * @param uIova The I/O virtual address being read. 1277 * @param cbRead The number of bytes being read. 1287 * @param uIova The I/O virtual address being accessed. 1288 * @param cbAccess The number of bytes being accessed. 1289 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1278 1290 * @param pGCPhysSpa Where to store the translated system physical address. 1279 1291 * 1280 1292 * @thread Any. 1281 1293 */ 1282 DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, 1283 PRTGCPHYS pGCPhysSpa)); 1284 1285 /** 1286 * Translates the physical address for a memory write transaction through the IOMMU. 1287 * 1288 * @returns VBox status code. 1289 * @param pDevIns The IOMMU device instance. 1290 * @param uDevId The device identifier (bus, device, function). 1291 * @param uIova The I/O virtual address being written. 1292 * @param cbRead The number of bytes being written. 1293 * @param pGCPhysSpa Where to store the translated system physical address. 1294 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, 1295 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)); 1296 1297 /** 1298 * Translates in bulk physical page addresses for memory transactions through the 1299 * IOMMU. 1300 * 1301 * @returns VBox status code. 1302 * @param pDevIns The IOMMU device instance. 1303 * @param uDevId The device identifier (bus, device, function). 1304 * @param cIovas The number of I/O virtual addresses being accessed. 1305 * @param pauIovas The I/O virtual addresses being accessed. 1306 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1307 * @param paGCPhysSpa Where to store the translated system physical page 1308 * addresses. 1294 1309 * 1295 1310 * @thread Any. 1296 1311 */ 1297 DECLR0CALLBACKMEMBER(int, pfnMem Write,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,1298 PRTGCPHYS pGCPhysSpa));1312 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas, 1313 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)); 1299 1314 1300 1315 /** … … 1318 1333 1319 1334 /** Current PDMIOMMUREG version number. */ 1320 #define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 1, 0)1335 #define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 2, 0) 1321 1336 1322 1337 … … 1333 1348 1334 1349 /** 1335 * Translates the physical address for a memory readtransaction through the IOMMU.1350 * Translates the physical address for a memory transaction through the IOMMU. 1336 1351 * 1337 1352 * @returns VBox status code. 1338 1353 * @param pDevIns The IOMMU device instance. 1339 1354 * @param uDevId The device identifier (bus, device, function). 1340 * @param uIova The I/O virtual address being read. 1341 * @param cbRead The number of bytes being read. 1355 * @param uIova The I/O virtual address being accessed. 1356 * @param cbAccess The number of bytes being accessed. 1357 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1342 1358 * @param pGCPhysSpa Where to store the translated system physical address. 1343 1359 * 1344 1360 * @thread Any. 1345 1361 */ 1346 DECLRCCALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, 1347 PRTGCPHYS pGCPhysSpa)); 1348 1349 /** 1350 * Translates the physical address for a memory write transaction through the IOMMU. 1351 * 1352 * @returns VBox status code. 1353 * @param pDevIns The IOMMU device instance. 1354 * @param uDevId The device identifier (bus, device, function). 1355 * @param uIova The I/O virtual address being written. 1356 * @param cbRead The number of bytes being written. 1357 * @param pGCPhysSpa Where to store the translated system physical address. 1362 DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, 1363 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)); 1364 1365 /** 1366 * Translates in bulk physical page addresses for memory transactions through the 1367 * IOMMU. 1368 * 1369 * @returns VBox status code. 1370 * @param pDevIns The IOMMU device instance. 1371 * @param uDevId The device identifier (bus, device, function). 1372 * @param cIovas The number of I/O virtual addresses being accessed. 1373 * @param pauIovas The I/O virtual addresses being accessed. 1374 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1375 * @param paGCPhysSpa Where to store the translated system physical page 1376 * addresses. 1358 1377 * 1359 1378 * @thread Any. 1360 1379 */ 1361 DECLRCCALLBACKMEMBER(int, pfnMem Write,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,1362 PRTGCPHYS pGCPhysSpa));1380 DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas, 1381 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)); 1363 1382 1364 1383 /** … … 1382 1401 1383 1402 /** Current PDMIOMMUREG version number. */ 1384 #define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 1, 0)1403 #define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 2, 0) 1385 1404 1386 1405 … … 1397 1416 1398 1417 /** 1399 * Translates the physical address for a memory readtransaction through the IOMMU.1418 * Translates the physical address for a memory transaction through the IOMMU. 1400 1419 * 1401 1420 * @returns VBox status code. 1402 1421 * @param pDevIns The IOMMU device instance. 1403 1422 * @param uDevId The device identifier (bus, device, function). 1404 * @param uIova The I/O virtual address being read. 1405 * @param cbRead The number of bytes being read. 1423 * @param uIova The I/O virtual address being accessed. 1424 * @param cbAccess The number of bytes being accessed. 1425 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1406 1426 * @param pGCPhysSpa Where to store the translated system physical address. 1407 1427 * 1408 1428 * @thread Any. 1409 1429 */ 1410 DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, 1411 PRTGCPHYS pGCPhysSpa)); 1412 1413 /** 1414 * Translates the physical address for a memory write transaction through the IOMMU. 1415 * 1416 * @returns VBox status code. 1417 * @param pDevIns The IOMMU device instance. 1418 * @param uDevId The device identifier (bus, device, function). 1419 * @param uIova The I/O virtual address being written. 1420 * @param cbWrite The number of bytes being written. 1421 * @param pGCPhysSpa Where to store the translated system physical address. 1430 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, 1431 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)); 1432 1433 /** 1434 * Translates in bulk physical page addresses for memory transactions through the 1435 * IOMMU. 1436 * 1437 * @returns VBox status code. 1438 * @param pDevIns The IOMMU device instance. 1439 * @param uDevId The device identifier (bus, device, function). 1440 * @param cIovas The number of I/O virtual addresses being accessed. 1441 * @param pauIovas The I/O virtual addresses being accessed. 1442 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX. 1443 * @param paGCPhysSpa Where to store the translated system physical page 1444 * addresses. 1422 1445 * 1423 1446 * @thread Any. 1424 1447 */ 1425 DECLR3CALLBACKMEMBER(int, pfnMem Write,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,1426 PRTGCPHYS pGCPhysSpa));1448 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas, 1449 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)); 1427 1450 1428 1451 /** … … 1446 1469 1447 1470 /** Current PDMIOMMUREG version number. */ 1448 #define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 1, 0)1471 #define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 2, 0) 1449 1472 1450 1473 /** IOMMU registration structure for the current context. */ … … 2264 2287 2265 2288 /** Current PDMDEVHLPR3 version number. */ 2266 #define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 4 4, 0)2289 #define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 45, 0) 2267 2290 2268 2291 /** … … 3350 3373 3351 3374 /** 3375 * Requests the mapping of a guest page into ring-3 in preparation for a bus master 3376 * physical memory write operation. 3377 * 3378 * Refer pfnPhysGCPhys2CCPtr() for further details. 3379 * 3380 * @returns VBox status code. 3381 * @param pDevIns The device instance. 3382 * @param pPciDev The PCI device structure. If NULL the default 3383 * PCI device for this device instance is used. 3384 * @param GCPhys The guest physical address of the page that should be 3385 * mapped. 3386 * @param fFlags Flags reserved for future use, MBZ. 3387 * @param ppv Where to store the address corresponding to GCPhys. 3388 * @param pLock Where to store the lock information that 3389 * pfnPhysReleasePageMappingLock needs. 3390 * 3391 * @remarks Avoid calling this API from within critical sections (other than the PGM 3392 * one) because of the deadlock risk when we have to delegating the task to 3393 * an EMT. 3394 * @thread Any. 3395 */ 3396 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, 3397 void **ppv, PPGMPAGEMAPLOCK pLock)); 3398 3399 /** 3400 * Requests the mapping of a guest page into ring-3, external threads, in prepartion 3401 * for a bus master physical memory read operation. 3402 * 3403 * Refer pfnPhysGCPhys2CCPtrReadOnly() for further details. 3404 * 3405 * @returns VBox status code. 3406 * @param pDevIns The device instance. 3407 * @param pPciDev The PCI device structure. If NULL the default 3408 * PCI device for this device instance is used. 3409 * @param GCPhys The guest physical address of the page that 3410 * should be mapped. 3411 * @param fFlags Flags reserved for future use, MBZ. 3412 * @param ppv Where to store the address corresponding to 3413 * GCPhys. 3414 * @param pLock Where to store the lock information that 3415 * pfnPhysReleasePageMappingLock needs. 3416 * 3417 * @remarks Avoid calling this API from within critical sections. 3418 * @thread Any. 3419 */ 3420 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, 3421 uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock)); 3422 3423 /** 3424 * Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus 3425 * master physical memory write operation. 3426 * 3427 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks() 3428 * ASAP to release them. 3429 * 3430 * Refer pfnPhysBulkGCPhys2CCPtr() for further details. 3431 * 3432 * @returns VBox status code. 3433 * @param pDevIns The device instance. 3434 * @param pPciDev The PCI device structure. If NULL the default 3435 * PCI device for this device instance is used. 3436 * @param cPages Number of pages to lock. 3437 * @param paGCPhysPages The guest physical address of the pages that 3438 * should be mapped (@a cPages entries). 3439 * @param fFlags Flags reserved for future use, MBZ. 3440 * @param papvPages Where to store the ring-3 mapping addresses 3441 * corresponding to @a paGCPhysPages. 3442 * @param paLocks Where to store the locking information that 3443 * pfnPhysBulkReleasePageMappingLock needs (@a cPages 3444 * in length). 3445 */ 3446 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, 3447 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, 3448 PPGMPAGEMAPLOCK paLocks)); 3449 3450 /** 3451 * Requests the mapping of multiple guest pages into ring-3 in preparation for a bus 3452 * master physical memory read operation. 3453 * 3454 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks() 3455 * ASAP to release them. 3456 * 3457 * Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details. 3458 * 3459 * @returns VBox status code. 3460 * @param pDevIns The device instance. 3461 * @param pPciDev The PCI device structure. If NULL the default 3462 * PCI device for this device instance is used. 3463 * @param cPages Number of pages to lock. 3464 * @param paGCPhysPages The guest physical address of the pages that 3465 * should be mapped (@a cPages entries). 3466 * @param fFlags Flags reserved for future use, MBZ. 3467 * @param papvPages Where to store the ring-3 mapping addresses 3468 * corresponding to @a paGCPhysPages. 3469 * @param paLocks Where to store the lock information that 3470 * pfnPhysReleasePageMappingLock needs (@a cPages 3471 * in length). 3472 */ 3473 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, 3474 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, 3475 void const **papvPages, PPGMPAGEMAPLOCK paLocks)); 3476 3477 /** 3352 3478 * Sets the IRQ for the given PCI device. 3353 3479 * … … 7217 7343 } 7218 7344 7345 #ifdef IN_RING3 7346 /** 7347 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr 7348 */ 7349 DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, 7350 void **ppv, PPGMPAGEMAPLOCK pLock) 7351 { 7352 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock); 7353 } 7354 7355 /** 7356 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly 7357 */ 7358 DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, 7359 void const **ppv, PPGMPAGEMAPLOCK pLock) 7360 { 7361 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock); 7362 } 7363 7364 /** 7365 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr 7366 */ 7367 DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, 7368 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, 7369 PPGMPAGEMAPLOCK paLocks) 7370 { 7371 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages, 7372 paLocks); 7373 } 7374 7375 /** 7376 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly 7377 */ 7378 DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, 7379 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages, 7380 PPGMPAGEMAPLOCK paLocks) 7381 { 7382 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, 7383 papvPages, paLocks); 7384 } 7385 #endif /* IN_RING3 */ 7386 7219 7387 /** 7220 7388 * Sets the IRQ for the default PCI device.
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