VirtualBox

Changeset 87480 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Jan 29, 2021 2:55:56 PM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
142502
Message:

VMM/HMVMX: Moving more stuff to HMR0PERVCPU. bugref:9217

Location:
trunk/src/VBox/VMM/VMMR0
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r87479 r87480  
    12841284    Assert(pHostCpu->idCpu != NIL_RTCPUID);
    12851285    if (   pVCpu->hmr0.s.idLastCpu   != pHostCpu->idCpu
    1286         || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
     1286        || pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes
    12871287#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    12881288        || CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
    … …  
    13141314        pHostCpu->uCurrentAsid           = 1;
    13151315        pVCpu->hmr0.s.uCurrentAsid       = 1;
    1316         pVCpu->hm.s.cTlbFlushes          = pHostCpu->cTlbFlushes;
     1316        pVCpu->hmr0.s.cTlbFlushes        = pHostCpu->cTlbFlushes;
    13171317        pVCpu->hmr0.s.idLastCpu          = pHostCpu->idCpu;
    13181318        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
    … …  
    13381338                    pHostCpu->uCurrentAsid = 1;      /* Wraparound at 1; host uses 0 */
    13391339                    pHostCpu->cTlbFlushes++;         /* All VCPUs that run on this host CPU must use a new ASID. */
    1340                     fHitASIDLimit      = true;
     1340                    fHitASIDLimit          = true;
    13411341                }
    13421342
    … …  
    13501350                pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
    13511351                pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
    1352                 pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
     1352                pVCpu->hmr0.s.cTlbFlushes  = pHostCpu->cTlbFlushes;
    13531353            }
    13541354            else
    … …  
    13731373    AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
    13741374              ("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
    1375     AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
    1376               ("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
     1375    AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
     1376              ("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
    13771377    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    13781378              ("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
    … …  
    43414341    uint64_t const uHostTsc = ASMReadTSC();                     /* Read the TSC as soon as possible. */
    43424342    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);   /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
    4343     ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits);            /* Initialized in vmR3CreateUVM(): used for EMT poking. */
     4343    ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits);          /* Initialized in vmR3CreateUVM(): used for EMT poking. */
    43444344
    43454345    PSVMVMCB     pVmcb     = pSvmTransient->pVmcb;

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r87479 r87480  
    29862986
    29872987    Assert(pHostCpu->idCpu != NIL_RTCPUID);
    2988     pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
    2989     pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    2990     pVCpu->hm.s.fForceTLBFlush = false;
     2988    pVCpu->hmr0.s.idLastCpu     = pHostCpu->idCpu;
     2989    pVCpu->hmr0.s.cTlbFlushes   = pHostCpu->cTlbFlushes;
     2990    pVCpu->hm.s.fForceTLBFlush  = false;
    29912991    return;
    29922992}
    … …  
    30353035     * cannot reuse the current ASID anymore.
    30363036     */
    3037     if (   pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
    3038         || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
     3037    if (   pVCpu->hmr0.s.idLastCpu   != pHostCpu->idCpu
     3038        || pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    30393039    {
    30403040        ++pHostCpu->uCurrentAsid;
    … …  
    30483048        pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
    30493049        pVCpu->hmr0.s.idLastCpu    = pHostCpu->idCpu;
    3050         pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
     3050        pVCpu->hmr0.s.cTlbFlushes  = pHostCpu->cTlbFlushes;
    30513051
    30523052        /*
    … …  
    30933093
    30943094    Assert(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu);
    3095     Assert(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes);
    3096     AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
    3097               ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
     3095    Assert(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes);
     3096    AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
     3097              ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
    30983098    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    30993099              ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
    3100                pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
     3100               pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes));
    31013101    AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
    31023102              ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
    … …  
    31323132     */
    31333133    if (   pVCpu->hmr0.s.idLastCpu   != pHostCpu->idCpu
    3134         || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
     3134        || pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    31353135    {
    31363136        pVCpu->hm.s.fForceTLBFlush = true;
    … …  
    31543154
    31553155    pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
    3156     pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
     3156    pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
    31573157
    31583158    if (pVCpu->hm.s.fForceTLBFlush)
    … …  
    31873187     */
    31883188    if (   pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
    3189         || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
     3189        || pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
    31903190    {
    31913191        pVCpu->hm.s.fForceTLBFlush = true;
    … …  
    32273227
    32283228        pVCpu->hm.s.fForceTLBFlush = false;
    3229         pVCpu->hm.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
     3229        pVCpu->hmr0.s.cTlbFlushes    = pHostCpu->cTlbFlushes;
    32303230        pVCpu->hmr0.s.uCurrentAsid   = pHostCpu->uCurrentAsid;
    32313231        if (pHostCpu->fFlushAsidBeforeUse)
    … …  
    32463246    }
    32473247
    3248     AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
    3249               ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
     3248    AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
     3249              ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
    32503250    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
    32513251              ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
    3252                pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
     3252               pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes));
    32533253    AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
    32543254              ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
    … …  
    1110011100
    1110111101    ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);   /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
    11102     ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits);            /* Initialized in vmR3CreateUVM(): used for EMT poking. */
     11102    ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits);          /* Initialized in vmR3CreateUVM(): used for EMT poking. */
    1110311103    pVCpu->hm.s.fCtxChanged            = 0;                     /* Exits/longjmps to ring-3 requires saving the guest state. */
    1110411104    pVmxTransient->fVmcsFieldsRead     = 0;                     /* Transient fields need to be read from the VMCS. */
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