- Timestamp:
- Feb 1, 2021 9:01:16 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 142543
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/HMAll.cpp
r87515 r87518 662 662 * @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed 663 663 */ 664 VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM)665 { 666 return HMIsEnabled(pVM) && pVM->hm.s.fAllow64BitGuests;664 VMM_INT_DECL(bool) HMIsLongModeAllowed(PVMCC pVM) 665 { 666 return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fAllow64BitGuestsCfg, pVM->hmr0.s.fAllow64BitGuests, RT_NOTHING); 667 667 } 668 668 -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r87515 r87518 990 990 991 991 /* 992 * Validate some parameters.992 * Validate and copy over some parameters. 993 993 */ 994 994 AssertReturn(pVM->hm.s.svm.fSupported, VERR_INCOMPATIBLE_CONFIG); … … 998 998 VERR_INCOMPATIBLE_CONFIG); 999 999 pVM->hmr0.s.fNestedPaging = fNestedPaging; 1000 pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg; 1000 1001 1001 1002 /* -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r87515 r87518 2504 2504 { 2505 2505 Assert(!(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */ 2506 if (pVCpu->CTX_SUFF(pVM)->hm .s.fAllow64BitGuests)2506 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests) 2507 2507 { 2508 2508 pVCpu->hmr0.s.vmx.u64HostMsrLStar = ASMRdMsr(MSR_K8_LSTAR); … … 2526 2526 static bool hmR0VmxIsLazyGuestMsr(PCVMCPUCC pVCpu, uint32_t idMsr) 2527 2527 { 2528 if (pVCpu->CTX_SUFF(pVM)->hm .s.fAllow64BitGuests)2528 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests) 2529 2529 { 2530 2530 switch (idMsr) … … 2559 2559 2560 2560 Assert(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST); 2561 if (pVCpu->CTX_SUFF(pVM)->hm .s.fAllow64BitGuests)2561 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests) 2562 2562 { 2563 2563 /* … … 2615 2615 { 2616 2616 Assert(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST); 2617 if (pVCpu->CTX_SUFF(pVM)->hm .s.fAllow64BitGuests)2617 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests) 2618 2618 { 2619 2619 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hmr0.s.vmx.u64HostMsrLStar); … … 3774 3774 * required for 64-bit guests. 3775 3775 */ 3776 if (pVM->hm .s.fAllow64BitGuests)3776 if (pVM->hmr0.s.fAllow64BitGuests) 3777 3777 { 3778 3778 hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_LSTAR, VMXMSRPM_ALLOW_RD_WR); … … 3990 3990 /* Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is 3991 3991 invalid on 32-bit Intel CPUs. Set this control only for 64-bit guests. */ 3992 if (pVM->hm.s.fAllow64BitGuests) 3993 { 3992 if (pVM->hmr0.s.fAllow64BitGuests) 3994 3993 fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */ 3995 3994 | VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */ 3996 }3997 3995 } 3998 3996 … … 4538 4536 VERR_INCOMPATIBLE_CONFIG); 4539 4537 pVM->hmr0.s.fNestedPaging = fNestedPaging; 4538 pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg; 4540 4539 4541 4540 /* Initialize these always, see hmR3InitFinalizeR0().*/ … … 7754 7753 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE) 7755 7754 { 7756 if ( pVM->hm .s.fAllow64BitGuests7755 if ( pVM->hmr0.s.fAllow64BitGuests 7757 7756 && (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)) 7758 7757 pCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE); … … 7761 7760 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS) 7762 7761 { 7763 if ( pVM->hm .s.fAllow64BitGuests7762 if ( pVM->hmr0.s.fAllow64BitGuests 7764 7763 && (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)) 7765 7764 { … … 10596 10595 * be taken care of by EPT/shadow paging. 10597 10596 */ 10598 if (pVM->hm.s.fAllow64BitGuests) 10599 { 10597 if (pVM->hmr0.s.fAllow64BitGuests) 10600 10598 u32ProcCtls |= VMX_PROC_CTLS_CR8_STORE_EXIT 10601 10599 | VMX_PROC_CTLS_CR8_LOAD_EXIT; 10602 }10603 10600 } 10604 10601 -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r87515 r87518 346 346 * already have the support. */ 347 347 #ifdef VBOX_WITH_64_BITS_GUESTS 348 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests , HC_ARCH_BITS == 64);348 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64); 349 349 AssertLogRelRCReturn(rc, rc); 350 350 #else 351 pVM->hm.s.fAllow64BitGuests = false;351 pVM->hm.s.fAllow64BitGuestsCfg = false; 352 352 #endif 353 353 … … 1665 1665 } 1666 1666 1667 LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"1668 : "HM: Guest support: 32-bit only\n"));1667 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n" 1668 : "HM: Guest support: 32-bit only\n")); 1669 1669 1670 1670 /* … … 1695 1695 */ 1696 1696 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP); 1697 if (pVM->hm.s.fAllow64BitGuests )1697 if (pVM->hm.s.fAllow64BitGuestsCfg) 1698 1698 { 1699 1699 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE); … … 1869 1869 case CPUMCPUVENDOR_AMD: 1870 1870 case CPUMCPUVENDOR_HYGON: 1871 if (pVM->hm.s.fAllow64BitGuests )1871 if (pVM->hm.s.fAllow64BitGuestsCfg) 1872 1872 { 1873 1873 LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n")); … … 1922 1922 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP); 1923 1923 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); 1924 if (pVM->hm.s.fAllow64BitGuests )1924 if (pVM->hm.s.fAllow64BitGuestsCfg) 1925 1925 { 1926 1926 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE); … … 1936 1936 : "HM: Disabled TPR patching\n")); 1937 1937 1938 LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"1939 : "HM: Guest support: 32-bit only\n"));1938 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n" 1939 : "HM: Guest support: 32-bit only\n")); 1940 1940 return VINF_SUCCESS; 1941 1941 } -
trunk/src/VBox/VMM/include/HMInternal.h
r87515 r87518 433 433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */ 434 434 bool fNestedPagingCfg; 435 /** Set when we've initialized VMX or SVM. */ 435 /** Set when we've finalized the VMX / SVM initialization in ring-3 436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */ 436 437 bool fInitialized; 437 /** Set if large pages are enabled (requires nested paging). */ 438 /** Set if large pages are enabled (requires nested paging). 439 * Config only, passed on the PGM where it really belongs. 440 * @todo move to PGM */ 438 441 bool fLargePages; 439 /** Set if we can support 64-bit guests or not. */ 440 bool fAllow64BitGuests; 442 /** Set if we can support 64-bit guests or not. 443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */ 444 bool fAllow64BitGuestsCfg; 441 445 /** Set when TPR patching is allowed. */ 442 446 bool fTprPatchingAllowed; … … 657 661 /** Set if nested paging is enabled. */ 658 662 bool fNestedPaging; 659 660 bool afAlignment0[7]; 663 /** Set if we can support 64-bit guests or not. */ 664 bool fAllow64BitGuests; 665 666 bool afAlignment0[6]; 661 667 662 668 /** SVM specific data. */
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