Changeset 87521 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Feb 1, 2021 9:48:09 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 142546
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r87519 r87521 144 144 } svm; 145 145 } u; 146 /** Maximum allowed ASID/VPID (inclusive). */147 uint32_t uMaxAsid;148 146 /** MSRs. */ 149 147 SUPHWVIRTMSRS Msrs; … … 168 166 RTONCE EnableAllCpusOnce; 169 167 } g_HmR0; 168 169 /** Maximum allowed ASID/VPID (inclusive). 170 * @todo r=bird: This is exclusive for VT-x according to source code comment. 171 * Couldn't immediately find any docs on AMD-V, but suspect it is 172 * exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */ 173 uint32_t g_uHmMaxAsid; 170 174 171 175 … … 345 349 346 350 /* Initialize VPID - 16 bits ASID. */ 347 g_ HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */351 g_uHmMaxAsid = 0x10000; /* exclusive */ 348 352 349 353 /* … … 487 491 /* Query AMD features. */ 488 492 uint32_t u32Dummy; 489 ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_ HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);493 ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_uHmMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features); 490 494 491 495 /* … … 1179 1183 } 1180 1184 pVM->hm.s.rcInit = g_HmR0.rcInit; 1181 pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;1185 pVM->hm.s.uMaxAsidForLog = g_uHmMaxAsid; 1182 1186 1183 1187 /* … … 1218 1222 * but it shouldn't be done later than this point so we do it here. 1219 1223 */ 1220 pVM->hm .s.fHostKernelFeatures = SUPR0GetKernelFeatures();1224 pVM->hmr0.s.fHostKernelFeatures = SUPR0GetKernelFeatures(); 1221 1225 1222 1226 /* -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r87519 r87521 1346 1346 1347 1347 bool fHitASIDLimit = false; 1348 if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)1348 if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid) 1349 1349 { 1350 1350 pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */ … … 1387 1387 AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes, 1388 1388 ("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes)); 1389 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,1389 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid, 1390 1390 ("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid)); 1391 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,1391 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid, 1392 1392 ("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid)); 1393 1393 -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r87519 r87521 3040 3040 { 3041 3041 ++pHostCpu->uCurrentAsid; 3042 if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)3042 if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid) 3043 3043 { 3044 3044 pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */ … … 3097 3097 AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes, 3098 3098 ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes)); 3099 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,3099 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid, 3100 3100 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu, 3101 3101 pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes)); 3102 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,3102 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid, 3103 3103 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid)); 3104 3104 … … 3220 3220 { 3221 3221 ++pHostCpu->uCurrentAsid; 3222 if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)3222 if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid) 3223 3223 { 3224 3224 pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */ … … 3249 3249 AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes, 3250 3250 ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes)); 3251 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,3251 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid, 3252 3252 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu, 3253 3253 pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes)); 3254 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < pVM->hm.s.uMaxAsid,3254 AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid, 3255 3255 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid)); 3256 3256 … … 4812 4812 4813 4813 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */ 4814 PVM pVM = pVCpu->CTX_SUFF(pVM);4815 if (pVM->hm .s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)4814 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 4815 if (pVM->hmr0.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY) 4816 4816 fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY; 4817 if (pVM->hm .s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE)4817 if (pVM->hmr0.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE) 4818 4818 { 4819 4819 /* The GDT is read-only but the writable GDT is available. */
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