VirtualBox

Ignore:
Timestamp:
Feb 2, 2021 3:01:24 PM (4 years ago)
Author:
vboxsync
Message:

VMM/HM: Moved the rest of the stuff out of g_HmR0 structure. bugref:9217

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMR0.cpp

    r87536 r87537  
    9494*********************************************************************************************************************************/
    9595/** The active ring-0 HM operations (copied from one of the table at init). */
    96 static HMR0VTABLE   g_HmR0Ops;
     96static HMR0VTABLE       g_HmR0Ops;
     97/** Indicates whether the host is suspending or not.  We'll refuse a few
     98 *  actions when the host is being suspended to speed up the suspending and
     99 *  avoid trouble. */
     100static bool volatile    g_fHmSuspended;
     101/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
     102 * enabled and disabled each time it's used to execute guest code. */
     103static bool             g_fHmGlobalInit;
    97104
    98105/** Maximum allowed ASID/VPID (inclusive).
    … …  
    100107 *       Couldn't immediately find any docs on AMD-V, but suspect it is
    101108 *       exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */
    102 uint32_t            g_uHmMaxAsid;
     109uint32_t                g_uHmMaxAsid;
    103110
    104111
    105112/** Set if VT-x (VMX) is supported by the CPU. */
    106 bool                g_fHmVmxSupported = false;
     113bool                    g_fHmVmxSupported = false;
    107114/** Whether we're using the preemption timer or not. */
    108 bool                g_fHmVmxUsePreemptTimer;
     115bool                    g_fHmVmxUsePreemptTimer;
    109116/** The shift mask employed by the VMX-Preemption timer. */
    110 uint8_t             g_cHmVmxPreemptTimerShift;
     117uint8_t                 g_cHmVmxPreemptTimerShift;
     118/** Whether we're using SUPR0EnableVTx or not. */
     119static bool             g_fHmVmxUsingSUPR0EnableVTx = false;
     120/** Set if we've called SUPR0EnableVTx(true) and should disable it during
     121 * module termination. */
     122static bool             g_fHmVmxCalledSUPR0EnableVTx = false;
    111123/** Host CR4 value (set by ring-0 VMX init) */
    112 uint64_t            g_uHmVmxHostCr4;
     124uint64_t                g_uHmVmxHostCr4;
    113125/** Host EFER value (set by ring-0 VMX init) */
    114 uint64_t            g_uHmVmxHostMsrEfer;
     126uint64_t                g_uHmVmxHostMsrEfer;
    115127/** Host SMM monitor control (used for logging/diagnostics) */
    116 uint64_t            g_uHmVmxHostSmmMonitorCtl;
     128uint64_t                g_uHmVmxHostSmmMonitorCtl;
     129
    117130
    118131/** Set if AMD-V is supported by the CPU. */
    119 bool                g_fHmSvmSupported = false;
     132bool                    g_fHmSvmSupported = false;
    120133/** SVM revision. */
    121 uint32_t            g_uHmSvmRev;
     134uint32_t                g_uHmSvmRev;
    122135/** SVM feature bits from cpuid 0x8000000a */
    123 uint32_t            g_uHmSvmFeatures;
     136uint32_t                g_uHmSvmFeatures;
     137
    124138
    125139/** MSRs. */
    126 SUPHWVIRTMSRS       g_HmMsrs;
    127 
    128 
    129 /**
    130  * Global data.
    131  */
    132 static struct
    133 {
    134     /** Per CPU globals. */
    135     HMPHYSCPU                       aCpuInfo[RTCPUSET_MAX_CPUS];
    136 
    137     /** Hardware-virtualization data. */
    138     struct
    139     {
    140         union
    141         {
    142             /** VT-x data. */
    143             struct
    144             {
    145                 /** Last instruction error. */
    146                 uint32_t                    ulLastInstrError;
    147                 /** Whether we're using SUPR0EnableVTx or not. */
    148                 bool                        fUsingSUPR0EnableVTx;
    149                 /** Set if we've called SUPR0EnableVTx(true) and should disable it during
    150                  * module termination. */
    151                 bool                        fCalledSUPR0EnableVTx;
    152             } vmx;
    153         } u;
    154     } hwvirt;
    155 
    156     /** Last recorded error code during HM ring-0 init. */
    157     int32_t                         rcInit;
    158 
    159     /** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
    160      * enabled and disabled each time it's used to execute guest code. */
    161     bool                            fGlobalInit;
    162     /** Indicates whether the host is suspending or not.  We'll refuse a few
    163      *  actions when the host is being suspended to speed up the suspending and
    164      *  avoid trouble. */
    165     bool volatile                   fSuspended;
    166 
    167     /** Whether we've already initialized all CPUs.
    168      * @remarks We could check the EnableAllCpusOnce state, but this is
    169      *          simpler and hopefully easier to understand. */
    170     bool                            fEnabled;
    171     /** Serialize initialization in HMR0EnableAllCpus. */
    172     RTONCE                          EnableAllCpusOnce;
    173 } g_HmR0;
     140SUPHWVIRTMSRS           g_HmMsrs;
     141
     142/** Last recorded error code during HM ring-0 init. */
     143static int32_t          g_rcHmInit = VINF_SUCCESS;
     144
     145/** Per CPU globals. */
     146static HMPHYSCPU        g_aHmCpuInfo[RTCPUSET_MAX_CPUS];
     147
     148/** Whether we've already initialized all CPUs.
     149 * @remarks We could check the EnableAllCpusOnce state, but this is
     150 *          simpler and hopefully easier to understand. */
     151static bool             g_fHmEnabled = false;
     152/** Serialize initialization in HMR0EnableAllCpus. */
     153static RTONCE           g_HmEnableAllCpusOnce = RTONCE_INITIALIZER;
    174154
    175155
    … …  
    377357     */
    378358    int rc;
    379     g_HmR0.rcInit = rc = SUPR0EnableVTx(true /* fEnable */);
    380     g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
    381     if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     359    g_rcHmInit = rc = SUPR0EnableVTx(true /* fEnable */);
     360    g_fHmVmxUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
     361    if (g_fHmVmxUsingSUPR0EnableVTx)
    382362    {
    383363        AssertLogRelMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
    … …  
    394374        HMR0FIRSTRC FirstRc;
    395375        hmR0FirstRcInit(&FirstRc);
    396         g_HmR0.rcInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
     376        g_rcHmInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
    397377        if (RT_SUCCESS(rc))
    398             g_HmR0.rcInit = rc = hmR0FirstRcGetStatus(&FirstRc);
     378            g_rcHmInit = rc = hmR0FirstRcGetStatus(&FirstRc);
    399379    }
    400380
    … …  
    424404         * to really verify if VT-x is usable.
    425405         */
    426         if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     406        if (!g_fHmVmxUsingSUPR0EnableVTx)
    427407        {
    428408            /* Allocate a temporary VMXON region. */
    … …  
    471451                 * They should fix their code, but until they do we simply refuse to run.
    472452                 */
    473                 g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
     453                g_rcHmInit = VERR_VMX_IN_VMX_ROOT_MODE;
    474454                Assert(g_fHmVmxSupported == false);
    475455            }
    … …  
    512492            else
    513493            {
    514                 g_HmR0.rcInit = rc;
     494                g_rcHmInit = rc;
    515495                g_fHmVmxSupported = false;
    516496            }
    … …  
    519499#ifdef LOG_ENABLED
    520500    else
    521         SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
     501        SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_rcHmInit);
    522502#endif
    523503    return VINF_SUCCESS;
    … …  
    586566        else
    587567        {
    588             g_HmR0.rcInit = rc;
     568            g_rcHmInit = rc;
    589569            if (rc == VERR_SVM_DISABLED || rc == VERR_SVM_IN_USE)
    590570                rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
    … …  
    592572    }
    593573    else
    594         g_HmR0.rcInit = rc;
     574        g_rcHmInit = rc;
    595575    return rc;
    596576}
    … …  
    607587     * Initialize the globals.
    608588     */
    609     g_HmR0.fEnabled = false;
    610     static RTONCE s_OnceInit = RTONCE_INITIALIZER;
    611     g_HmR0.EnableAllCpusOnce = s_OnceInit;
    612     for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
    613     {
    614         g_HmR0.aCpuInfo[i].idCpu        = NIL_RTCPUID;
    615         g_HmR0.aCpuInfo[i].hMemObj      = NIL_RTR0MEMOBJ;
    616         g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
    617         g_HmR0.aCpuInfo[i].pvMemObj     = NULL;
     589    g_fHmEnabled = false;
     590    for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
     591    {
     592        g_aHmCpuInfo[i].idCpu        = NIL_RTCPUID;
     593        g_aHmCpuInfo[i].hMemObj      = NIL_RTR0MEMOBJ;
     594        g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
     595        g_aHmCpuInfo[i].pvMemObj     = NULL;
    618596#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    619         g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm      = NIL_RTR0MEMOBJ;
    620         g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
    621         g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm     = NULL;
     597        g_aHmCpuInfo[i].n.svm.hNstGstMsrpm      = NIL_RTR0MEMOBJ;
     598        g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
     599        g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm     = NULL;
    622600#endif
    623601    }
    624602
    625603    /* Fill in all callbacks with placeholders. */
    626     g_HmR0Ops            = g_HmR0OpsDummy;
     604    g_HmR0Ops          = g_HmR0OpsDummy;
    627605
    628606    /* Default is global VT-x/AMD-V init. */
    629     g_HmR0.fGlobalInit = true;
     607    g_fHmGlobalInit    = true;
    630608
    631609    g_fHmVmxSupported  = false;
    … …  
    636614     * Make sure aCpuInfo is big enough for all the CPUs on this system.
    637615     */
    638     if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
    639     {
    640         LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
     616    if (RTMpGetArraySize() > RT_ELEMENTS(g_aHmCpuInfo))
     617    {
     618        LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aHmCpuInfo)));
    641619        return VERR_TOO_MANY_CPUS;
    642620    }
    … …  
    663641             * when brought offline/online or suspending/resuming.
    664642             */
    665             if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     643            if (!g_fHmVmxUsingSUPR0EnableVTx)
    666644            {
    667645                rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
    … …  
    681659                        SVMR0GlobalTerm();
    682660                    g_HmR0Ops         = g_HmR0OpsDummy;
    683                     g_HmR0.rcInit     = rc;
     661                    g_rcHmInit     = rc;
    684662                    g_fHmSvmSupported = false;
    685663                    g_fHmVmxSupported = false;
    … …  
    690668    else
    691669    {
    692         g_HmR0.rcInit = rc;
     670        g_rcHmInit = rc;
    693671        rc = VINF_SUCCESS; /* We return success here because module init shall not fail if HM fails to initialize. */
    694672    }
    … …  
    706684    int rc;
    707685    if (   g_fHmVmxSupported
    708         && g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     686        && g_fHmVmxUsingSUPR0EnableVTx)
    709687    {
    710688        /*
    711689         * Simple if the host OS manages VT-x.
    712690         */
    713         Assert(g_HmR0.fGlobalInit);
    714 
    715         if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
     691        Assert(g_fHmGlobalInit);
     692
     693        if (g_fHmVmxCalledSUPR0EnableVTx)
    716694        {
    717695            rc = SUPR0EnableVTx(false /* fEnable */);
    718             g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
     696            g_fHmVmxCalledSUPR0EnableVTx = false;
    719697        }
    720698        else
    721699            rc = VINF_SUCCESS;
    722700
    723         for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
     701        for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aHmCpuInfo); iCpu++)
    724702        {
    725             g_HmR0.aCpuInfo[iCpu].fConfigured = false;
    726             Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
     703            g_aHmCpuInfo[iCpu].fConfigured = false;
     704            Assert(g_aHmCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
    727705        }
    728706    }
    729707    else
    730708    {
    731         Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     709        Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    732710
    733711        /* Doesn't really matter if this fails. */
    … …  
    739717         * Disable VT-x/AMD-V on all CPUs if we enabled it before.
    740718         */
    741         if (g_HmR0.fGlobalInit)
     719        if (g_fHmGlobalInit)
    742720        {
    743721            HMR0FIRSTRC FirstRc;
    … …  
    752730         * Free the per-cpu pages used for VT-x and AMD-V.
    753731         */
    754         for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
     732        for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
    755733        {
    756             if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
     734            if (g_aHmCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
    757735            {
    758                 RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
    759                 g_HmR0.aCpuInfo[i].hMemObj      = NIL_RTR0MEMOBJ;
    760                 g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
    761                 g_HmR0.aCpuInfo[i].pvMemObj     = NULL;
     736                RTR0MemObjFree(g_aHmCpuInfo[i].hMemObj, false);
     737                g_aHmCpuInfo[i].hMemObj      = NIL_RTR0MEMOBJ;
     738                g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
     739                g_aHmCpuInfo[i].pvMemObj     = NULL;
    762740            }
    763741#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    764             if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
     742            if (g_aHmCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
    765743            {
    766                 RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
    767                 g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm      = NIL_RTR0MEMOBJ;
    768                 g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
    769                 g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm     = NULL;
     744                RTR0MemObjFree(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, false);
     745                g_aHmCpuInfo[i].n.svm.hNstGstMsrpm      = NIL_RTR0MEMOBJ;
     746                g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
     747                g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm     = NULL;
    770748            }
    771749#endif
    … …  
    797775static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
    798776{
    799     PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
     777    PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
    800778
    801779    Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
    802     Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
     780    Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
    803781    Assert(!pHostCpu->fConfigured);
    804782    Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
    … …  
    809787    int rc;
    810788    if (   g_fHmVmxSupported
    811         && g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     789        && g_fHmVmxUsingSUPR0EnableVTx)
    812790        rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmMsrs);
    813791    else
    … …  
    833811    PVMCC           pVM      = (PVMCC)pvUser1;     /* can be NULL! */
    834812    PHMR0FIRSTRC    pFirstRc = (PHMR0FIRSTRC)pvUser2;
    835     AssertReturnVoid(g_HmR0.fGlobalInit);
     813    AssertReturnVoid(g_fHmGlobalInit);
    836814    Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
    837815    hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
    … …  
    855833     *       notification.  Kind of unlikely though, so ignored for now.
    856834     */
    857     AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
    858     ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
     835    AssertReturn(!g_fHmEnabled, VERR_HM_ALREADY_ENABLED_IPE);
     836    ASMAtomicWriteBool(&g_fHmEnabled, true);
    859837
    860838    /*
    861839     * The global init variable is set by the first VM.
    862840     */
    863     g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
     841    g_fHmGlobalInit = pVM->hm.s.fGlobalInit;
    864842
    865843#ifdef VBOX_STRICT
    866     for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
    867     {
    868         Assert(g_HmR0.aCpuInfo[i].hMemObj      == NIL_RTR0MEMOBJ);
    869         Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
    870         Assert(g_HmR0.aCpuInfo[i].pvMemObj     == NULL);
    871         Assert(!g_HmR0.aCpuInfo[i].fConfigured);
    872         Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
    873         Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
     844    for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
     845    {
     846        Assert(g_aHmCpuInfo[i].hMemObj      == NIL_RTR0MEMOBJ);
     847        Assert(g_aHmCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
     848        Assert(g_aHmCpuInfo[i].pvMemObj     == NULL);
     849        Assert(!g_aHmCpuInfo[i].fConfigured);
     850        Assert(!g_aHmCpuInfo[i].cTlbFlushes);
     851        Assert(!g_aHmCpuInfo[i].uCurrentAsid);
    874852# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    875         Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm      == NIL_RTR0MEMOBJ);
    876         Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
    877         Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm     == NULL);
     853        Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm      == NIL_RTR0MEMOBJ);
     854        Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
     855        Assert(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm     == NULL);
    878856# endif
    879857    }
    … …  
    882860    int rc;
    883861    if (   g_fHmVmxSupported
    884         && g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
     862        && g_fHmVmxUsingSUPR0EnableVTx)
    885863    {
    886864        /*
    … …  
    890868        if (RT_SUCCESS(rc))
    891869        {
    892             g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
     870            g_fHmVmxCalledSUPR0EnableVTx = true;
    893871            /* If the host provides a VT-x init API, then we'll rely on that for global init. */
    894             g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
     872            g_fHmGlobalInit = pVM->hm.s.fGlobalInit = true;
    895873        }
    896874        else
    … …  
    903881         */
    904882        /* Allocate one page per cpu for the global VT-x and AMD-V pages */
    905         for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
     883        for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
    906884        {
    907             Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
     885            Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
    908886#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    909             Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
     887            Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
    910888#endif
    911889            if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
    912890            {
    913891                /** @todo NUMA */
    914                 rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
     892                rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
    915893                AssertLogRelRCReturn(rc, rc);
    916894
    917                 g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
    918                 Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
    919                 Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
    920 
    921                 g_HmR0.aCpuInfo[i].pvMemObj     = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
    922                 AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
    923                 ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
     895                g_aHmCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].hMemObj, 0);
     896                Assert(g_aHmCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
     897                Assert(!(g_aHmCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
     898
     899                g_aHmCpuInfo[i].pvMemObj     = RTR0MemObjAddress(g_aHmCpuInfo[i].hMemObj);
     900                AssertPtr(g_aHmCpuInfo[i].pvMemObj);
     901                ASMMemZeroPage(g_aHmCpuInfo[i].pvMemObj);
    924902
    925903#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
    926                 rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
     904                rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
    927905                                         false /* executable R0 mapping */);
    928906                AssertLogRelRCReturn(rc, rc);
    929907
    930                 g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
    931                 Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
    932                 Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
    933 
    934                 g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm    = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
    935                 AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
    936                 ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
     908                g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, 0);
     909                Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
     910                Assert(!(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
     911
     912                g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm    = RTR0MemObjAddress(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm);
     913                AssertPtr(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm);
     914                ASMMemFill32(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
    937915#endif
    938916            }
    … …  
    943921
    944922    if (   RT_SUCCESS(rc)
    945         && g_HmR0.fGlobalInit)
     923        && g_fHmGlobalInit)
    946924    {
    947925        /* First time, so initialize each cpu/core. */
    … …  
    966944{
    967945    /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
    968     if (ASMAtomicReadBool(&g_HmR0.fSuspended))
     946    if (ASMAtomicReadBool(&g_fHmSuspended))
    969947        return VERR_HM_SUSPEND_PENDING;
    970948
    971     return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
     949    return RTOnce(&g_HmEnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
    972950}
    973951
    … …  
    983961static int hmR0DisableCpu(RTCPUID idCpu)
    984962{
    985     PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
    986 
    987     Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     963    PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
     964
     965    Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    988966    Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
    989967    Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
    990     Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
     968    Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
    991969    Assert(!pHostCpu->fConfigured || pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
    992970    AssertRelease(idCpu == RTMpCpuId());
    … …  
    10231001{
    10241002    PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
    1025     AssertReturnVoid(g_HmR0.fGlobalInit);
     1003    AssertReturnVoid(g_fHmGlobalInit);
    10261004    hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
    10271005}
    … …  
    10541032{
    10551033    NOREF(pvData);
    1056     Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     1034    Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    10571035
    10581036    /*
    … …  
    10951073{
    10961074    NOREF(pvUser);
    1097     Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     1075    Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    10981076
    10991077#ifdef LOG_ENABLED
    … …  
    11051083
    11061084    if (enmEvent == RTPOWEREVENT_SUSPEND)
    1107         ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
    1108 
    1109     if (g_HmR0.fEnabled)
     1085        ASMAtomicWriteBool(&g_fHmSuspended, true);
     1086
     1087    if (g_fHmEnabled)
    11101088    {
    11111089        int         rc;
    … …  
    11151093        if (enmEvent == RTPOWEREVENT_SUSPEND)
    11161094        {
    1117             if (g_HmR0.fGlobalInit)
     1095            if (g_fHmGlobalInit)
    11181096            {
    11191097                /* Turn off VT-x or AMD-V on all CPUs. */
    … …  
    11381116                SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
    11391117#endif
    1140             if (g_HmR0.fGlobalInit)
     1118            if (g_fHmGlobalInit)
    11411119            {
    11421120                /* Turn VT-x or AMD-V back on on all CPUs. */
    … …  
    11491127
    11501128    if (enmEvent == RTPOWEREVENT_RESUME)
    1151         ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
     1129        ASMAtomicWriteBool(&g_fHmSuspended, false);
    11521130}
    11531131
    … …  
    11701148
    11711149    /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
    1172     if (ASMAtomicReadBool(&g_HmR0.fSuspended))
     1150    if (ASMAtomicReadBool(&g_fHmSuspended))
    11731151        return VERR_HM_SUSPEND_PENDING;
    11741152
    … …  
    12251203        /* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
    12261204    }
    1227     pVM->hm.s.rcInit              = g_HmR0.rcInit;
     1205    pVM->hm.s.rcInit              = g_rcHmInit;
    12281206    pVM->hm.s.uMaxAsidForLog      = g_uHmMaxAsid;
    12291207
    … …  
    13391317
    13401318    /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
    1341     AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
     1319    AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
    13421320
    13431321    /* On first entry we'll sync everything. */
    … …  
    13541332    /* Enable VT-x or AMD-V if local init is required. */
    13551333    int rc;
    1356     if (!g_HmR0.fGlobalInit)
    1357     {
    1358         Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     1334    if (!g_fHmGlobalInit)
     1335    {
     1336        Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    13591337        rc = hmR0EnableCpu(pVM, idCpu);
    13601338        if (RT_FAILURE(rc))
    … …  
    13691347
    13701348    /* Disable VT-x or AMD-V if local init was done before. */
    1371     if (!g_HmR0.fGlobalInit)
    1372     {
    1373         Assert(!g_fHmVmxSupported || !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
     1349    if (!g_fHmGlobalInit)
     1350    {
     1351        Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
    13741352        int rc2 = hmR0DisableCpu(idCpu);
    13751353        AssertRC(rc2);
    … …  
    14131391    int              rc       = VINF_SUCCESS;
    14141392    RTCPUID const    idCpu    = RTMpCpuId();
    1415     PHMPHYSCPU       pHostCpu = &g_HmR0.aCpuInfo[idCpu];
     1393    PHMPHYSCPU       pHostCpu = &g_aHmCpuInfo[idCpu];
    14161394    AssertPtr(pHostCpu);
    14171395
    … …  
    14461424{
    14471425    /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
    1448     AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
     1426    AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
    14491427    Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
    14501428
    … …  
    14981476
    14991477    RTCPUID const idCpu    = RTMpCpuId();
    1500     PCHMPHYSCPU   pHostCpu = &g_HmR0.aCpuInfo[idCpu];
    1501 
    1502     if (   !g_HmR0.fGlobalInit
     1478    PCHMPHYSCPU   pHostCpu = &g_aHmCpuInfo[idCpu];
     1479
     1480    if (   !g_fHmGlobalInit
    15031481        && pHostCpu->fConfigured)
    15041482    {
    … …  
    15331511    Assert(g_HmR0Ops.pfnThreadCtxCallback);
    15341512
    1535     g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
     1513    g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_fHmGlobalInit);
    15361514}
    15371515
    … …  
    15561534    if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
    15571535    {
    1558         PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
     1536        PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[RTMpCpuId()];
    15591537        Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
    15601538        Assert(pHostCpu->fConfigured);
    1561         AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
     1539        AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
    15621540    }
    15631541#endif
    … …  
    16081586VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
    16091587{
    1610     return ASMAtomicReadBool(&g_HmR0.fSuspended);
     1588    return ASMAtomicReadBool(&g_fHmSuspended);
    16111589}
    16121590
    … …  
    16371615    Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
    16381616    RTCPUID const idCpu = RTMpCpuId();
    1639     Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
    1640     return &g_HmR0.aCpuInfo[idCpu];
     1617    Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
     1618    return &g_aHmCpuInfo[idCpu];
    16411619}
    16421620
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