VirtualBox

Changeset 87543 in vbox


Ignore:
Timestamp:
Feb 2, 2021 5:00:24 PM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
142569
Message:

VMM/HMVMX: Use g_HmMsrs instead of pVM->hm.s.vmx.Msrs in ring-0, part 2. bugref:9217

Location:
trunk/src/VBox/VMM
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/HMAll.cpp

    r87542 r87543  
    683683
    684684        if (   pVM->hm.s.vmx.fSupported
    685             && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
     685            && (  CTX_EXPR(pVM->hm.s.vmx.MsrsForRing3.ProcCtls.n.allowed1, g_HmMsrs.u.vmx.ProcCtls.n.allowed1, RT_NOTHING)
     686                & VMX_PROC_CTLS_USE_MSR_BITMAPS))
    686687            return true;
    687688    }

  • trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp

    r87541 r87543  
    767767    {
    768768        /* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
    769         uint32_t uCr0Mask = (uint32_t)CTX_EXPR(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0, g_HmMsrs.u.vmx.u64Cr0Fixed0, RT_NOTHING);
     769        uint32_t uCr0Mask = (uint32_t)CTX_EXPR(pVM->hm.s.vmx.MsrsForRing3.u64Cr0Fixed0, g_HmMsrs.u.vmx.u64Cr0Fixed0, RT_NOTHING);
    770770
    771771        /* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
    … …  
    786786
    787787        /* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
    788         uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.vmx.Msrs.u64Cr0Fixed1, g_HmMsrs.u.vmx.u64Cr0Fixed1, RT_NOTHING);
     788        uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.vmx.MsrsForRing3.u64Cr0Fixed1, g_HmMsrs.u.vmx.u64Cr0Fixed1, RT_NOTHING);
    789789        if ((pCtx->cr0 & uCr0Mask) != 0)
    790790            return false;
    791791
    792792        /* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
    793         uCr0Mask  = (uint32_t)CTX_EXPR(pVM->hm.s.vmx.Msrs.u64Cr4Fixed0, g_HmMsrs.u.vmx.u64Cr4Fixed0, RT_NOTHING);
     793        uCr0Mask  = (uint32_t)CTX_EXPR(pVM->hm.s.vmx.MsrsForRing3.u64Cr4Fixed0, g_HmMsrs.u.vmx.u64Cr4Fixed0, RT_NOTHING);
    794794        uCr0Mask &= ~X86_CR4_VMXE;
    795795        if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
    … …  
    797797
    798798        /* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
    799         uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.vmx.Msrs.u64Cr4Fixed1, g_HmMsrs.u.vmx.u64Cr4Fixed1, RT_NOTHING);
     799        uCr0Mask = (uint32_t)~CTX_EXPR(pVM->hm.s.vmx.MsrsForRing3.u64Cr4Fixed1, g_HmMsrs.u.vmx.u64Cr4Fixed1, RT_NOTHING);
    800800        if ((pCtx->cr4 & uCr0Mask) != 0)
    801801            return false;

  • trunk/src/VBox/VMM/VMMR0/HMR0.cpp

    r87542 r87543  
    11661166        pVM->hm.s.vmx.u64HostMsrEfer        = g_uHmVmxHostMsrEfer;
    11671167        pVM->hm.s.vmx.u64HostSmmMonitorCtl  = g_uHmVmxHostSmmMonitorCtl;
    1168         HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.vmx.Msrs);
     1168        HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.vmx.MsrsForRing3);
    11691169        /* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
    11701170
    11711171        /* Enable VPID if supported and configured. */
    1172         if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
     1172        if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
    11731173            pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
    11741174
    … …  
    11761176        Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
    11771177        if (   pVM->cpum.ro.GuestFeatures.fVmx
    1178             && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
     1178            && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
    11791179            pVM->hm.s.vmx.fUseVmcsShadowing = true;
    11801180
    11811181        /* Use the VMCS controls for swapping the EFER MSR if supported. */
    11821182        Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
    1183         if (   (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
    1184             && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_LOAD_EFER_MSR)
    1185             && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_SAVE_EFER_MSR))
     1183        if (   (g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
     1184            && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_LOAD_EFER_MSR)
     1185            && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_SAVE_EFER_MSR))
    11861186            pVM->hm.s.vmx.fSupportsVmcsEfer = true;
    11871187
    11881188#if 0
    11891189        /* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
    1190         if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
    1191             && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
     1190        if (   (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
     1191            && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
    11921192            pVM->hm.s.fVirtApicRegs = true;
    11931193
    … …  
    11951195        /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
    11961196         *        here. */
    1197         if (   (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT)
    1198             && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
     1197        if (   (g_HmMsrs.u.vmx.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT)
     1198            && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
    11991199            pVM->hm.s.fPostedIntrs = true;
    12001200#endif

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r87541 r87543  
    19151915    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    19161916
    1917     bool const fMsrBitmaps = RT_BOOL(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS);
     1917    bool const fMsrBitmaps = RT_BOOL(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS);
    19181918    bool const fShadowVmcs = !fIsNstGstVmcs ? pVM->hm.s.vmx.fUseVmcsShadowing : pVM->cpum.ro.GuestFeatures.fVmxVmcsShadowing;
    19191919    Assert(!pVM->cpum.ro.GuestFeatures.fVmxVmcsShadowing);  /* VMCS shadowing is not yet exposed to the guest. */
    … …  
    19431943     * Get the virtual-APIC page rather than allocating them again.
    19441944     */
    1945     if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
     1945    if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
    19461946    {
    19471947        if (!fIsNstGstVmcs)
    … …  
    20272027     * Allocate per-VM VT-x structures.
    20282028     */
    2029     bool const fVirtApicAccess   = RT_BOOL(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
     2029    bool const fVirtApicAccess   = RT_BOOL(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
    20302030    bool const fUseVmcsShadowing = pVM->hm.s.vmx.fUseVmcsShadowing;
    20312031    VMXPAGEALLOCINFO aAllocInfo[] =
    … …  
    22352235{
    22362236    /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
    2237     uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc);
     2237    uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc);
    22382238    if (RT_LIKELY(cMsrs < cMaxSupportedMsrs))
    22392239    {
    … …  
    27492749
    27502750    /* Verify the MSR counts do not exceed the maximum count supported by the hardware. */
    2751     Assert(cMsrs < VMX_MISC_MAX_MSRS(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc));
     2751    Assert(cMsrs < VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc));
    27522752
    27532753    /* Verify the MSR counts are within the allocated page size. */
    … …  
    37963796{
    37973797    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    3798     uint32_t       fVal = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed0;      /* Bits set here must always be set. */
    3799     uint32_t const fZap = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1;      /* Bits cleared here must always be cleared. */
     3798    uint32_t       fVal = g_HmMsrs.u.vmx.PinCtls.n.allowed0;      /* Bits set here must always be set. */
     3799    uint32_t const fZap = g_HmMsrs.u.vmx.PinCtls.n.allowed1;      /* Bits cleared here must always be cleared. */
    38003800
    38013801    fVal |= VMX_PIN_CTLS_EXT_INT_EXIT                        /* External interrupts cause a VM-exit. */
    38023802         |  VMX_PIN_CTLS_NMI_EXIT;                           /* Non-maskable interrupts (NMIs) cause a VM-exit. */
    38033803
    3804     if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
     3804    if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
    38053805        fVal |= VMX_PIN_CTLS_VIRT_NMI;                       /* Use virtual NMIs and virtual-NMI blocking features. */
    38063806
    … …  
    38083808    if (pVM->hm.s.vmx.fUsePreemptTimer)
    38093809    {
    3810         Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
     3810        Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
    38113811        fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
    38123812    }
    … …  
    38163816    if (pVM->hm.s.fPostedIntrs)
    38173817    {
    3818         Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT);
    3819         Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
     3818        Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT);
     3819        Assert(g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
    38203820        fVal |= VMX_PIN_CTLS_POSTED_INT;
    38213821    }
    … …  
    38253825    {
    38263826        LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
    3827                     pVM->hm.s.vmx.Msrs.PinCtls.n.allowed0, fVal, fZap));
     3827                    g_HmMsrs.u.vmx.PinCtls.n.allowed0, fVal, fZap));
    38283828        pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
    38293829        return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
    … …  
    38493849{
    38503850    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    3851     uint32_t       fVal = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed0;    /* Bits set here must be set in the VMCS. */
    3852     uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;    /* Bits cleared here must be cleared in the VMCS. */
     3851    uint32_t       fVal = g_HmMsrs.u.vmx.ProcCtls2.n.allowed0;    /* Bits set here must be set in the VMCS. */
     3852    uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls2.n.allowed1;    /* Bits cleared here must be cleared in the VMCS. */
    38533853
    38543854    /* WBINVD causes a VM-exit. */
    3855     if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
     3855    if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
    38563856        fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
    38573857
    … …  
    38633863       by the hardware. Without this, guest executing INVPCID would cause a #UD. */
    38643864    if (   pVM->cpum.ro.GuestFeatures.fInvpcid
    3865         && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID))
     3865        && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID))
    38663866        fVal |= VMX_PROC_CTLS2_INVPCID;
    38673867
    … …  
    38783878    {
    38793879        /* Enable APIC-register virtualization. */
    3880         Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
     3880        Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
    38813881        fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
    38823882
    38833883        /* Enable virtual-interrupt delivery. */
    3884         Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
     3884        Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
    38853885        fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
    38863886    }
    … …  
    38913891    /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
    38923892     *        done dynamically. */
    3893     if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     3893    if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
    38943894    {
    38953895        fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS;
    … …  
    39003900       by the hardware. Without this, guest executing RDTSCP would cause a #UD. */
    39013901    if (   pVM->cpum.ro.GuestFeatures.fRdTscP
    3902         && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP))
     3902        && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP))
    39033903        fVal |= VMX_PROC_CTLS2_RDTSCP;
    39043904
    39053905    /* Enable Pause-Loop exiting. */
    3906     if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
     3906    if (   (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
    39073907        && pVM->hm.s.vmx.cPleGapTicks
    39083908        && pVM->hm.s.vmx.cPleWindowTicks)
    … …  
    39173917    {
    39183918        LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
    3919                     pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed0, fVal, fZap));
     3919                    g_HmMsrs.u.vmx.ProcCtls2.n.allowed0, fVal, fZap));
    39203920        pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
    39213921        return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
    … …  
    39413941{
    39423942    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    3943     uint32_t       fVal = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0;     /* Bits set here must be set in the VMCS. */
    3944     uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;     /* Bits cleared here must be cleared in the VMCS. */
     3943    uint32_t       fVal = g_HmMsrs.u.vmx.ProcCtls.n.allowed0;     /* Bits set here must be set in the VMCS. */
     3944    uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls.n.allowed1;     /* Bits cleared here must be cleared in the VMCS. */
    39453945
    39463946    fVal |= VMX_PROC_CTLS_HLT_EXIT                                    /* HLT causes a VM-exit. */
    … …  
    39533953
    39543954    /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
    3955     if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
    3956         ||  (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
     3955    if (   !(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
     3956        ||  (g_HmMsrs.u.vmx.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
    39573957    {
    39583958        pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
    … …  
    39713971    /* Use TPR shadowing if supported by the CPU. */
    39723972    if (   PDMHasApic(pVM)
    3973         && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
     3973        && (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
    39743974    {
    39753975        fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW;                /* CR8 reads from the Virtual-APIC page. */
    … …  
    39893989
    39903990    /* Use MSR-bitmaps if supported by the CPU. */
    3991     if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
     3991    if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
    39923992    {
    39933993        fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
    … …  
    39963996
    39973997    /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
    3998     if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
     3998    if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
    39993999        fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
    40004000
    … …  
    40024002    {
    40034003        LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
    4004                     pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0, fVal, fZap));
     4004                    g_HmMsrs.u.vmx.ProcCtls.n.allowed0, fVal, fZap));
    40054005        pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
    40064006        return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
    … …  
    41324132    if (RT_SUCCESS(rc))
    41334133    {
    4134         if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
     4134        if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
    41354135            hmR0VmxSetupVmcsMsrBitmapAddr(pVmcsInfo);
    41364136
    … …  
    45224522    bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
    45234523    AssertReturn(   !fNestedPaging
    4524                  || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT), /** @todo use a ring-0 copy of ProcCtls2.n.allowed1 */
     4524                 || (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT), /** @todo use a ring-0 copy of ProcCtls2.n.allowed1 */
    45254525                 VERR_INCOMPATIBLE_CONFIG);
    45264526    pVM->hmr0.s.fNestedPaging = fNestedPaging;
    … …  
    49914991         */
    49924992        {
    4993             uint32_t       fVal = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0;    /* Bits set here must be set in the VMCS. */
    4994             uint32_t const fZap = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1;    /* Bits cleared here must be cleared in the VMCS. */
     4993            uint32_t       fVal = g_HmMsrs.u.vmx.EntryCtls.n.allowed0;    /* Bits set here must be set in the VMCS. */
     4994            uint32_t const fZap = g_HmMsrs.u.vmx.EntryCtls.n.allowed1;    /* Bits cleared here must be cleared in the VMCS. */
    49954995
    49964996            /*
    … …  
    50485048            {
    50495049                Log4Func(("Invalid VM-entry controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
    5050                           pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0, fVal, fZap));
     5050                          g_HmMsrs.u.vmx.EntryCtls.n.allowed0, fVal, fZap));
    50515051                pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
    50525052                return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
    … …  
    50665066         */
    50675067        {
    5068             uint32_t       fVal = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed0;     /* Bits set here must be set in the VMCS. */
    5069             uint32_t const fZap = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1;     /* Bits cleared here must be cleared in the VMCS. */
     5068            uint32_t       fVal = g_HmMsrs.u.vmx.ExitCtls.n.allowed0;     /* Bits set here must be set in the VMCS. */
     5069            uint32_t const fZap = g_HmMsrs.u.vmx.ExitCtls.n.allowed1;     /* Bits cleared here must be cleared in the VMCS. */
    50705070
    50715071            /*
    … …  
    51075107             */
    51085108            if (    pVM->hm.s.vmx.fUsePreemptTimer
    5109                 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
     5109                && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
    51105110                fVal |= VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER;
    51115111
    … …  
    51225122            {
    51235123                Log4Func(("Invalid VM-exit controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%R#X32\n",
    5124                           pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed0, fVal, fZap));
     5124                          g_HmMsrs.u.vmx.ExitCtls.n.allowed0, fVal, fZap));
    51255125                pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
    51265126                return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
    … …  
    60856085    {
    60866086        /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
    6087         PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    6088         if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
     6087        if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
    60896088        {
    60906089            uProcCtls |= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
    … …  
    82338232static void hmR0VmxSetIntWindowExitVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
    82348233{
    8235     if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT)
     8234    if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT)
    82368235    {
    82378236        if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
    … …  
    82708269static void hmR0VmxSetNmiWindowExitVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
    82718270{
    8272     if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
     8271    if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
    82738272    {
    82748273        if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
    … …  
    1052210521    if (u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
    1052310522    {
    10524         Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
     10523        Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
    1052510524        RTGCPHYS const GCPhysApicAccess = pVmcsNstGst->u64AddrApicAccess.u;
    1052610525
    … …  
    1055410553    if (u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
    1055510554    {
    10556         Assert(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW);
     10555        Assert(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW);
    1055710556        RTGCPHYS const GCPhysVirtApic = pVmcsNstGst->u64AddrVirtApic.u;
    1055810557
    … …  
    1059310592    PVMXVMCSINFO pVmcsInfoNstGst = &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
    1059410593    Assert(pVM->hm.s.vmx.fUnrestrictedGuest);
    10595     Assert(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
     10594    Assert(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
    1059610595    Assert(hmGetVmxActiveVmcsInfo(pVCpu) == pVmcsInfoNstGst);
    1059710596
    … …  
    1061910618        &&  (u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT))
    1062010619    {
    10621         Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
     10620        Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
    1062210621        rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, cPleGapTicks);
    1062310622        rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, cPleWindowTicks);
    … …  
    1073710736    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    1073810737    if (   !pVCpu->hm.s.vmx.u64GstMsrApicBase
    10739         && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     10738        && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
    1074010739        && PDMHasApic(pVM))
    1074110740    {
    … …  
    1197711976     * Sanitize the control stuff.
    1197811977     */
    11979     pDbgState->fCpe2Extra       &= pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;
     11978    pDbgState->fCpe2Extra       &= g_HmMsrs.u.vmx.ProcCtls2.n.allowed1;
    1198011979    if (pDbgState->fCpe2Extra)
    1198111980        pDbgState->fCpe1Extra   |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
    11982     pDbgState->fCpe1Extra       &= pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;
    11983     pDbgState->fCpe1Unwanted    &= ~pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0;
     11981    pDbgState->fCpe1Extra       &= g_HmMsrs.u.vmx.ProcCtls.n.allowed1;
     11982    pDbgState->fCpe1Unwanted    &= ~g_HmMsrs.u.vmx.ProcCtls.n.allowed0;
    1198411983    if (pVCpu->hmr0.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
    1198511984    {

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r87531 r87543  
    10731073    {
    10741074        LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
    1075         LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
     1075        LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.MsrsForRing3.u64FeatCtrl));
    10761076        switch (pVM->hm.s.rcInit)
    10771077        {
    … …  
    15021502
    15031503    LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
    1504     AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
     1504    AssertLogRelReturn(pVM->hm.s.vmx.MsrsForRing3.u64FeatCtrl != 0, VERR_HM_IPE_4);
    15051505
    15061506    LogRel(("HM: Using VT-x implementation 3.0\n"));
    … …  
    15101510    LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL          = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
    15111511
    1512     hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
    1513     hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
    1514 
    1515     hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
    1516     hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
    1517     if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
    1518         hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
    1519 
    1520     hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
    1521     hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
    1522 
    1523     if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
     1512    hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.MsrsForRing3.u64FeatCtrl);
     1513    hmR3VmxReportBasicMsr(pVM->hm.s.vmx.MsrsForRing3.u64Basic);
     1514
     1515    hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.MsrsForRing3.PinCtls);
     1516    hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.MsrsForRing3.ProcCtls);
     1517    if (pVM->hm.s.vmx.MsrsForRing3.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
     1518        hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.MsrsForRing3.ProcCtls2);
     1519
     1520    hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.MsrsForRing3.EntryCtls);
     1521    hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.MsrsForRing3.ExitCtls);
     1522
     1523    if (RT_BF_GET(pVM->hm.s.vmx.MsrsForRing3.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
    15241524    {
    15251525        /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
    1526         LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS   = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
    1527         LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS  = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
    1528         LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS      = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
    1529         LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS       = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
    1530     }
    1531 
    1532     hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
    1533     hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
    1534     if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
    1535         hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
    1536     if (pVM->hm.s.vmx.Msrs.u64VmFunc)
    1537         hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
    1538     hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
     1526        LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS   = %#RX64\n", pVM->hm.s.vmx.MsrsForRing3.TruePinCtls));
     1527        LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS  = %#RX64\n", pVM->hm.s.vmx.MsrsForRing3.TrueProcCtls));
     1528        LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS      = %#RX64\n", pVM->hm.s.vmx.MsrsForRing3.TrueEntryCtls));
     1529        LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS       = %#RX64\n", pVM->hm.s.vmx.MsrsForRing3.TrueExitCtls));
     1530    }
     1531
     1532    hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.MsrsForRing3.u64Misc);
     1533    hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.MsrsForRing3.u64VmcsEnum);
     1534    if (pVM->hm.s.vmx.MsrsForRing3.u64EptVpidCaps)
     1535        hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.MsrsForRing3.u64EptVpidCaps);
     1536    if (pVM->hm.s.vmx.MsrsForRing3.u64VmFunc)
     1537        hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.MsrsForRing3.u64VmFunc);
     1538    hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.MsrsForRing3);
    15391539
    15401540#ifdef TODO_9217_VMCSINFO
    … …  
    15641564     */
    15651565    AssertLogRelReturn(   !pVM->hm.s.fNestedPagingCfg
    1566                        || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
     1566                       || (pVM->hm.s.vmx.MsrsForRing3.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
    15671567                       VERR_HM_IPE_1);
    15681568    AssertLogRelReturn(   !pVM->hm.s.vmx.fUnrestrictedGuest
    1569                        || (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
     1569                       || (   (pVM->hm.s.vmx.MsrsForRing3.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
    15701570                           && pVM->hm.s.fNestedPagingCfg),
    15711571                       VERR_HM_IPE_1);
    … …  
    15761576     * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
    15771577     */
    1578     if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
     1578    if (   !(pVM->hm.s.vmx.MsrsForRing3.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
    15791579        && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
    15801580    {
    … …  
    17491749    if (pVM->hm.s.vmx.fUseVmcsShadowing)
    17501750    {
    1751         bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
     1751        bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.MsrsForRing3.u64Misc & VMX_MISC_VMWRITE_ALL);
    17521752        LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
    17531753    }
    … …  
    30723072    if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
    30733073    {
    3074         LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1  %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
    3075         LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0  %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
     3074        LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1  %#RX32\n", pVM->hm.s.vmx.MsrsForRing3.EntryCtls.n.allowed1));
     3075        LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0  %#RX32\n", pVM->hm.s.vmx.MsrsForRing3.EntryCtls.n.allowed0));
    30763076    }
    30773077    else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)

  • trunk/src/VBox/VMM/include/HMInternal.h

    r87539 r87543  
    552552
    553553        /** VMX MSR values. */
    554         VMXMSRS                     Msrs;
     554        VMXMSRS                     MsrsForRing3;
    555555
    556556        /** Virtual address of the TSS page used for real mode emulation. */

  • trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp

    r87521 r87543  
    370370    CHECK_MEMBER_ALIGNMENT(HM, uMaxAsidForLog, 8);
    371371    CHECK_MEMBER_ALIGNMENT(HM, vmx, 8);
    372     CHECK_MEMBER_ALIGNMENT(HM, vmx.Msrs, 8);
     372    CHECK_MEMBER_ALIGNMENT(HM, vmx.MsrsForRing3, 8);
    373373    CHECK_MEMBER_ALIGNMENT(HM, svm, 8);
    374374    CHECK_MEMBER_ALIGNMENT(HM, PatchTree, 8);
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