- Timestamp:
- Apr 1, 2021 8:23:15 AM (4 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 3 edited
-
Bus/DevIommuIntel.cpp (modified) (44 diffs)
-
Bus/DevIommuIntel.h (modified) (1 diff)
-
PC/DevACPI.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r88332 r88342 34 34 * This is suitable for casting constants outside code (since RT_LO_U32 can't be 35 35 * used as it asserts for correctness when compiling on certain compilers). */ 36 #define VTD_LO_U32(a) (uint32_t)(UINT32_MAX & (a))36 #define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a)) 37 37 38 38 /** Gets the high uint32_t of a uint64_t or something equivalent. … … 40 40 * This is suitable for casting constants outside code (since RT_HI_U32 can't be 41 41 * used as it asserts for correctness when compiling on certain compilers). */ 42 #define VTD_HI_U32(a) (uint32_t)((a) >> 32)42 #define DMAR_HI_U32(a) (uint32_t)((a) >> 32) 43 43 44 44 /** Asserts MMIO access' offset and size are valid or returns appropriate error 45 45 * code suitable for returning from MMIO access handlers. */ 46 #define VTD_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \46 #define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \ 47 47 do { \ 48 48 AssertReturn(!(off & 3), VINF_IOM_MMIO_UNUSED_FF); \ … … 51 51 52 52 /** Checks whether the MMIO offset is valid. */ 53 #define VTD_IS_MMIO_OFF_VALID(a_off) ( (a_off) < VTD_MMIO_GROUP_0_OFF_END \54 || (a_off) - VTD_MMIO_GROUP_1_OFF_FIRST < VTD_MMIO_GROUP_1_SIZE)53 #define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \ 54 || (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE) 55 55 56 56 /** The number of fault recording registers our implementation supports. … … 59 59 * 60 60 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */ 61 #define VTD_FRCD_REG_COUNTUINT32_C(1)61 #define DMAR_FRCD_REG_COUNT UINT32_C(1) 62 62 63 63 /** Offset of first register in group 0. */ 64 #define VTD_MMIO_GROUP_0_OFF_FIRSTVTD_MMIO_OFF_VER_REG64 #define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG 65 65 /** Offset of last register in group 0 (inclusive). */ 66 #define VTD_MMIO_GROUP_0_OFF_LASTVTD_MMIO_OFF_MTRR_PHYSMASK9_REG66 #define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 67 67 /** Last valid offset in group 0 (exclusive). */ 68 #define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)68 #define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */) 69 69 /** Size of the group 0 (in bytes). */ 70 #define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST)71 72 #define VTD_MMIO_OFF_IVA_REG0xe40 /**< Implementation-specific MMIO offset of IVA_REG. */73 #define VTD_MMIO_OFF_IOTLB_REG0xe48 /**< Implementation-specific MMIO offset of IOTLB_REG. */74 #define VTD_MMIO_OFF_FRCD_LO_REG0xe60 /**< Implementation-specific MMIO offset of FRCD_LO_REG. */75 #define VTD_MMIO_OFF_FRCD_HI_REG0xe68 /**< Implementation-specific MMIO offset of FRCD_HI_REG. */76 AssertCompile(!( VTD_MMIO_OFF_FRCD_LO_REG & 0xf));70 #define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST) 71 72 #define DMAR_MMIO_OFF_IVA_REG 0xe40 /**< Implementation-specific MMIO offset of IVA_REG. */ 73 #define DMAR_MMIO_OFF_IOTLB_REG 0xe48 /**< Implementation-specific MMIO offset of IOTLB_REG. */ 74 #define DMAR_MMIO_OFF_FRCD_LO_REG 0xe60 /**< Implementation-specific MMIO offset of FRCD_LO_REG. */ 75 #define DMAR_MMIO_OFF_FRCD_HI_REG 0xe68 /**< Implementation-specific MMIO offset of FRCD_HI_REG. */ 76 AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf)); 77 77 78 78 /** Offset of first register in group 1. */ 79 #define VTD_MMIO_GROUP_1_OFF_FIRSTVTD_MMIO_OFF_VCCAP_REG79 #define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG 80 80 /** Offset of last register in group 1 (inclusive). */ 81 #define VTD_MMIO_GROUP_1_OFF_LAST (VTD_MMIO_OFF_FRCD_LO_REG + 8) * VTD_FRCD_REG_COUNT81 #define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT 82 82 /** Last valid offset in group 1 (exclusive). */ 83 #define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)83 #define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */) 84 84 /** Size of the group 1 (in bytes). */ 85 #define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST)85 #define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST) 86 86 87 87 /** Release log prefix string. */ 88 #define IOMMU_LOG_PFX"Intel-IOMMU"88 #define DMAR_LOG_PFX "Intel-IOMMU" 89 89 90 90 /** The current saved state version. */ 91 #define IOMMU_SAVED_STATE_VERSION191 #define DMAR_SAVED_STATE_VERSION 1 92 92 93 93 … … 96 96 *********************************************************************************************************************************/ 97 97 /** 98 * The shared IOMMUdevice state.99 */ 100 typedef struct IOMMU101 { 102 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */98 * The shared DMAR device state. 99 */ 100 typedef struct DMAR 101 { 102 /** IOMMU device index. */ 103 103 uint32_t idxIommu; 104 /** IOMMUmagic. */104 /** DMAR magic. */ 105 105 uint32_t u32Magic; 106 106 … … 108 108 IOMMMIOHANDLE hMmio; 109 109 110 /** IOMMUregisters (group 0). */111 uint8_t abRegs0[ VTD_MMIO_GROUP_0_SIZE];112 /** IOMMUregisters (group 1). */113 uint8_t abRegs1[ VTD_MMIO_GROUP_1_SIZE];114 } IOMMU;115 /** Pointer to the IOMMUdevice state. */116 typedef IOMMU *PIOMMU;117 /** Pointer to the const IOMMUdevice state. */118 typedef const IOMMU *PCIOMMU;119 120 /** 121 * The ring-3 IOMMUdevice state.122 */ 123 typedef struct IOMMUR3110 /** DMAR registers (group 0). */ 111 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE]; 112 /** DMAR registers (group 1). */ 113 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE]; 114 } DMAR; 115 /** Pointer to the DMAR device state. */ 116 typedef DMAR *PDMAR; 117 /** Pointer to the const DMAR device state. */ 118 typedef const DMAR *PCDMAR; 119 120 /** 121 * The ring-3 DMAR device state. 122 */ 123 typedef struct DMARR3 124 124 { 125 125 /** Device instance. */ … … 127 127 /** The IOMMU helper. */ 128 128 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3; 129 } IOMMUR3;130 /** Pointer to the ring-3 IOMMUdevice state. */131 typedef IOMMUR3 *PIOMMUR3;132 /** Pointer to the const ring-3 IOMMUdevice state. */133 typedef const IOMMUR3 *PCIOMMUR3;134 135 /** 136 * The ring-0 IOMMUdevice state.137 */ 138 typedef struct IOMMUR0129 } DMARR3; 130 /** Pointer to the ring-3 DMAR device state. */ 131 typedef DMARR3 *PDMARR3; 132 /** Pointer to the const ring-3 DMAR device state. */ 133 typedef const DMARR3 *PCDMARR3; 134 135 /** 136 * The ring-0 DMAR device state. 137 */ 138 typedef struct DMARR0 139 139 { 140 140 /** Device instance. */ … … 142 142 /** The IOMMU helper. */ 143 143 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0; 144 } IOMMUR0;144 } DMARR0; 145 145 /** Pointer to the ring-0 IOMMU device state. */ 146 typedef IOMMUR0 *PIOMMUR0;146 typedef DMARR0 *PDMARR0; 147 147 /** Pointer to the const ring-0 IOMMU device state. */ 148 typedef const IOMMUR0 *PCIOMMUR0;149 150 /** 151 * The raw-mode IOMMUdevice state.152 */ 153 typedef struct IOMMURC148 typedef const DMARR0 *PCDMARR0; 149 150 /** 151 * The raw-mode DMAR device state. 152 */ 153 typedef struct DMARRC 154 154 { 155 155 /** Device instance. */ … … 157 157 /** The IOMMU helper. */ 158 158 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC; 159 } IOMMURC;160 /** Pointer to the raw-mode IOMMUdevice state. */161 typedef IOMMURC *PIOMMURC;162 /** Pointer to the const raw-mode IOMMUdevice state. */163 typedef const IOMMURC *PCIOMMURC;164 165 /** The IOMMUdevice state for the current context. */166 typedef CTX_SUFF( IOMMU) IOMMUCC;167 /** Pointer to the IOMMUdevice state for the current context. */168 typedef CTX_SUFF(P IOMMU) PIOMMUCC;159 } DMARRC; 160 /** Pointer to the raw-mode DMAR device state. */ 161 typedef DMARRC *PDMARRC; 162 /** Pointer to the const raw-mode DMAR device state. */ 163 typedef const DMARRC *PCIDMARRC; 164 165 /** The DMAR device state for the current context. */ 166 typedef CTX_SUFF(DMAR) DMARCC; 167 /** Pointer to the DMAR device state for the current context. */ 168 typedef CTX_SUFF(PDMAR) PDMARCC; 169 169 170 170 … … 173 173 *********************************************************************************************************************************/ 174 174 /** 175 * Read-write masks for IOMMUregisters (group 0).175 * Read-write masks for DMAR registers (group 0). 176 176 */ 177 177 static const uint32_t g_au32RwMasks0[] = … … 180 180 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK, 181 181 /* 0x004 Reserved */ 0, 182 /* 0x008 CAP_REG */ VTD_LO_U32(VTD_CAP_REG_RW_MASK), VTD_HI_U32(VTD_CAP_REG_RW_MASK),183 /* 0x010 ECAP_REG */ VTD_LO_U32(VTD_ECAP_REG_RW_MASK), VTD_HI_U32(VTD_ECAP_REG_RW_MASK),182 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK), 183 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK), 184 184 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK, 185 185 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK, 186 /* 0x020 RTADDR_REG */ VTD_LO_U32(VTD_RTADDR_REG_RW_MASK), VTD_HI_U32(VTD_RTADDR_REG_RW_MASK),187 /* 0x028 CCMD_REG */ VTD_LO_U32(VTD_CCMD_REG_RW_MASK), VTD_HI_U32(VTD_CCMD_REG_RW_MASK),186 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK), 187 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK), 188 188 /* 0x030 Reserved */ 0, 189 189 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK, … … 194 194 /* 0x048 Reserved */ 0, 0, 195 195 /* 0x050 Reserved */ 0, 0, 196 /* 0x058 AFLOG_REG */ VTD_LO_U32(VTD_AFLOG_REG_RW_MASK), VTD_HI_U32(VTD_AFLOG_REG_RW_MASK),196 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK), 197 197 /* 0x060 Reserved */ 0, 198 198 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */ … … 201 201 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */ 202 202 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */ 203 /* 0x080 IQH_REG */ VTD_LO_U32(VTD_IQH_REG_RW_MASK), VTD_HI_U32(VTD_IQH_REG_RW_MASK),204 /* 0x088 IQT_REG */ VTD_LO_U32(VTD_IQT_REG_RW_MASK), VTD_HI_U32(VTD_IQT_REG_RW_MASK),205 /* 0x090 IQA_REG */ VTD_LO_U32(VTD_IQA_REG_RW_MASK), VTD_HI_U32(VTD_IQA_REG_RW_MASK),203 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK), 204 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK), 205 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK), 206 206 /* 0x098 Reserved */ 0, 207 207 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK, … … 210 210 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK, 211 211 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK, 212 /* 0x0b0 IQERCD_REG */ VTD_LO_U32(VTD_IQERCD_REG_RW_MASK), VTD_HI_U32(VTD_IQERCD_REG_RW_MASK),213 /* 0x0b8 IRTA_REG */ VTD_LO_U32(VTD_IRTA_REG_RW_MASK), VTD_HI_U32(VTD_IRTA_REG_RW_MASK),214 /* 0x0c0 PQH_REG */ VTD_LO_U32(VTD_PQH_REG_RW_MASK), VTD_HI_U32(VTD_PQH_REG_RW_MASK),215 /* 0x0c8 PQT_REG */ VTD_LO_U32(VTD_PQT_REG_RW_MASK), VTD_HI_U32(VTD_PQT_REG_RW_MASK),216 /* 0x0d0 PQA_REG */ VTD_LO_U32(VTD_PQA_REG_RW_MASK), VTD_HI_U32(VTD_PQA_REG_RW_MASK),212 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK), 213 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK), 214 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK), 215 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK), 216 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK), 217 217 /* 0x0d8 Reserved */ 0, 218 218 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK, … … 223 223 /* 0x0f0 Reserved */ 0, 0, 224 224 /* 0x0f8 Reserved */ 0, 0, 225 /* 0x100 MTRRCAP_REG */ VTD_LO_U32(VTD_MTRRCAP_REG_RW_MASK), VTD_HI_U32(VTD_MTRRCAP_REG_RW_MASK),225 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK), 226 226 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */ 227 227 /* 0x110 Reserved */ 0, 0, … … 260 260 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0, 261 261 }; 262 AssertCompile(sizeof(g_au32RwMasks0) == VTD_MMIO_GROUP_0_SIZE);263 264 /** 265 * Read-only Status, Write-1-to-clear masks for IOMMUregisters (group 0).262 AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE); 263 264 /** 265 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0). 266 266 */ 267 267 static const uint32_t g_au32Rw1cMasks0[] = 268 268 { 269 /* Offset Register Low High */269 /* Offset Register Low High */ 270 270 /* 0x000 VER_REG */ 0, 271 271 /* 0x004 Reserved */ 0, 272 /* 0x008 CAP_REG */ 0, 0,273 /* 0x010 ECAP_REG */ 0, 0,272 /* 0x008 CAP_REG */ 0, 0, 273 /* 0x010 ECAP_REG */ 0, 0, 274 274 /* 0x018 GCMD_REG */ 0, 275 275 /* 0x01c GSTS_REG */ 0, 276 /* 0x020 RTADDR_REG */ 0, 0,277 /* 0x028 CCMD_REG */ 0, 0,276 /* 0x020 RTADDR_REG */ 0, 0, 277 /* 0x028 CCMD_REG */ 0, 0, 278 278 /* 0x030 Reserved */ 0, 279 279 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK, … … 282 282 /* 0x040 FEADDR_REG */ 0, 283 283 /* 0x044 FEUADDR_REG */ 0, 284 /* 0x048 Reserved */ 0, 0,285 /* 0x050 Reserved */ 0, 0,286 /* 0x058 AFLOG_REG */ 0, 0,284 /* 0x048 Reserved */ 0, 0, 285 /* 0x050 Reserved */ 0, 0, 286 /* 0x058 AFLOG_REG */ 0, 0, 287 287 /* 0x060 Reserved */ 0, 288 288 /* 0x064 PMEN_REG */ 0, 289 289 /* 0x068 PLMBASE_REG */ 0, 290 290 /* 0x06c PLMLIMIT_REG */ 0, 291 /* 0x070 PHMBASE_REG */ 0, 0,292 /* 0x078 PHMLIMIT_REG */ 0, 0,293 /* 0x080 IQH_REG */ 0, 0,294 /* 0x088 IQT_REG */ 0, 0,295 /* 0x090 IQA_REG */ 0, 0,291 /* 0x070 PHMBASE_REG */ 0, 0, 292 /* 0x078 PHMLIMIT_REG */ 0, 0, 293 /* 0x080 IQH_REG */ 0, 0, 294 /* 0x088 IQT_REG */ 0, 0, 295 /* 0x090 IQA_REG */ 0, 0, 296 296 /* 0x098 Reserved */ 0, 297 297 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK, … … 300 300 /* 0x0a8 IEADDR_REG */ 0, 301 301 /* 0x0ac IEUADDR_REG */ 0, 302 /* 0x0b0 IQERCD_REG */ 0, 0,303 /* 0x0b8 IRTA_REG */ 0, 0,304 /* 0x0c0 PQH_REG */ 0, 0,305 /* 0x0c8 PQT_REG */ 0, 0,306 /* 0x0d0 PQA_REG */ 0, 0,302 /* 0x0b0 IQERCD_REG */ 0, 0, 303 /* 0x0b8 IRTA_REG */ 0, 0, 304 /* 0x0c0 PQH_REG */ 0, 0, 305 /* 0x0c8 PQT_REG */ 0, 0, 306 /* 0x0d0 PQA_REG */ 0, 0, 307 307 /* 0x0d8 Reserved */ 0, 308 308 /* 0x0dc PRS_REG */ 0, … … 311 311 /* 0x0e8 PEADDR_REG */ 0, 312 312 /* 0x0ec PEUADDR_REG */ 0, 313 /* 0x0f0 Reserved */ 0, 0,314 /* 0x0f8 Reserved */ 0, 0,315 /* 0x100 MTRRCAP_REG */ 0, 0,316 /* 0x108 MTRRDEF_REG */ 0, 0,317 /* 0x110 Reserved */ 0, 0,318 /* 0x118 Reserved */ 0, 0,319 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,320 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,321 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,322 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,323 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,324 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,325 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,326 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,327 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,328 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,329 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,330 /* 0x178 Reserved */ 0, 0,331 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,332 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,333 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,334 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,335 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,336 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,337 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,338 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,339 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,340 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,341 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,342 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,343 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,344 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,345 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,346 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,347 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,348 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,349 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,350 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,313 /* 0x0f0 Reserved */ 0, 0, 314 /* 0x0f8 Reserved */ 0, 0, 315 /* 0x100 MTRRCAP_REG */ 0, 0, 316 /* 0x108 MTRRDEF_REG */ 0, 0, 317 /* 0x110 Reserved */ 0, 0, 318 /* 0x118 Reserved */ 0, 0, 319 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, 320 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0, 321 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0, 322 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0, 323 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0, 324 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0, 325 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0, 326 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0, 327 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0, 328 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0, 329 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0, 330 /* 0x178 Reserved */ 0, 0, 331 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, 332 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0, 333 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0, 334 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0, 335 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0, 336 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0, 337 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0, 338 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0, 339 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0, 340 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0, 341 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0, 342 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0, 343 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0, 344 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0, 345 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0, 346 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0, 347 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0, 348 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0, 349 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0, 350 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0, 351 351 }; 352 AssertCompile(sizeof(g_au32Rw1cMasks0) == VTD_MMIO_GROUP_0_SIZE);353 354 /** 355 * Read-write masks for IOMMUregisters (group 1).352 AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE); 353 354 /** 355 * Read-write masks for DMAR registers (group 1). 356 356 */ 357 357 static const uint32_t g_au32RwMasks1[] = 358 358 { 359 /* Offset Register Low High */360 /* 0xe00 VCCAP_REG */ VTD_LO_U32(VTD_VCCAP_REG_RW_MASK), VTD_HI_U32(VTD_VCCAP_REG_RW_MASK),361 /* 0xe08 Reserved */ 0, 0,362 /* 0xe10 VCMD_REG */ 0, 0, /* RO as we don't support VCS. */363 /* 0xe18 VCMDRSVD_REG */ 0, 0,364 /* 0xe20 VCRSP_REG */ 0, 0, /* RO as we don't support VCS. */365 /* 0xe28 VCRSPRSVD_REG */ 0, 0,366 /* 0xe30 Reserved */ 0, 0,367 /* 0xe38 Reserved */ 0, 0,368 /* 0xe40 IVA_REG */ VTD_LO_U32(VTD_IVA_REG_RW_MASK), VTD_HI_U32(VTD_IVA_REG_RW_MASK),369 /* 0xe48 IOTLB_REG */ VTD_LO_U32(VTD_IOTLB_REG_RW_MASK), VTD_HI_U32(VTD_IOTLB_REG_RW_MASK),370 /* 0xe50 Reserved */ 0, 0,371 /* 0xe58 Reserved */ 0, 0,372 /* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW_MASK),373 /* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW_MASK),359 /* Offset Register Low High */ 360 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK), 361 /* 0xe08 Reserved */ 0, 0, 362 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */ 363 /* 0xe18 VCMDRSVD_REG */ 0, 0, 364 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */ 365 /* 0xe28 VCRSPRSVD_REG */ 0, 0, 366 /* 0xe30 Reserved */ 0, 0, 367 /* 0xe38 Reserved */ 0, 0, 368 /* 0xe40 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK), 369 /* 0xe48 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK), 370 /* 0xe50 Reserved */ 0, 0, 371 /* 0xe58 Reserved */ 0, 0, 372 /* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK), 373 /* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK), 374 374 }; 375 AssertCompile(sizeof(g_au32RwMasks1) == VTD_MMIO_GROUP_1_SIZE);376 AssertCompile(( VTD_MMIO_OFF_FRCD_LO_REG - VTD_MMIO_GROUP_1_OFF_FIRST) + VTD_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );377 378 /** 379 * Read-only Status, Write-1-to-clear masks for IOMMUregisters (group 1).375 AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE); 376 AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) ); 377 378 /** 379 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1). 380 380 */ 381 381 static const uint32_t g_au32Rw1cMasks1[] = 382 382 { 383 /* Offset Register Low High */384 /* 0xe00 VCCAP_REG */ 0, 0,385 /* 0xe08 Reserved */ 0, 0,386 /* 0xe10 VCMD_REG */ 0, 0,387 /* 0xe18 VCMDRSVD_REG */ 0, 0,388 /* 0xe20 VCRSP_REG */ 0, 0,389 /* 0xe28 VCRSPRSVD_REG */ 0, 0,390 /* 0xe30 Reserved */ 0, 0,391 /* 0xe38 Reserved */ 0, 0,392 /* 0xe40 IVA_REG */ 0, 0,393 /* 0xe48 IOTLB_REG */ 0, 0,394 /* 0xe50 Reserved */ 0, 0,395 /* 0xe58 Reserved */ 0, 0,396 /* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),397 /* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),383 /* Offset Register Low High */ 384 /* 0xe00 VCCAP_REG */ 0, 0, 385 /* 0xe08 Reserved */ 0, 0, 386 /* 0xe10 VCMD_REG */ 0, 0, 387 /* 0xe18 VCMDRSVD_REG */ 0, 0, 388 /* 0xe20 VCRSP_REG */ 0, 0, 389 /* 0xe28 VCRSPRSVD_REG */ 0, 0, 390 /* 0xe30 Reserved */ 0, 0, 391 /* 0xe38 Reserved */ 0, 0, 392 /* 0xe40 IVA_REG */ 0, 0, 393 /* 0xe48 IOTLB_REG */ 0, 0, 394 /* 0xe50 Reserved */ 0, 0, 395 /* 0xe58 Reserved */ 0, 0, 396 /* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK), 397 /* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK), 398 398 }; 399 AssertCompile(sizeof(g_au32Rw1cMasks1) == VTD_MMIO_GROUP_1_SIZE);399 AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE); 400 400 401 401 /** Array of RW masks for each register group. */ … … 415 415 * 416 416 * @returns Pointer to the first element of the register group. 417 * @param pThis The shared IOMMUdevice state.417 * @param pThis The shared DMAR device state. 418 418 * @param offReg The MMIO offset of the register. 419 419 * @param cbReg The size of the access being made (for bounds checking on … … 422 422 * belongs to. 423 423 */ 424 DECLINLINE(uint8_t *) iommuIntelRegGetGroup(PIOMMUpThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)424 DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup) 425 425 { 426 426 uint16_t const offLast = offReg + cbReg - 1; 427 AssertCompile( VTD_MMIO_GROUP_0_OFF_FIRST == 0);428 AssertMsg( VTD_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));427 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0); 428 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg)); 429 429 430 430 uint8_t *const apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] }; 431 *pIdxGroup = !(offLast < VTD_MMIO_GROUP_0_OFF_END);431 *pIdxGroup = !(offLast < DMAR_MMIO_GROUP_0_OFF_END); 432 432 return apbRegs[*pIdxGroup]; 433 433 } … … 437 437 * Writes a 64-bit register with the exactly the supplied value. 438 438 * 439 * @param pThis The shared IOMMUdevice state.439 * @param pThis The shared DMAR device state. 440 440 * @param offReg The MMIO offset of the register. 441 441 * @param uReg The 64-bit value to write. 442 442 */ 443 DECLINLINE(void) iommuIntelRegWriteRaw64(PIOMMUpThis, uint16_t offReg, uint64_t uReg)443 DECLINLINE(void) dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg) 444 444 { 445 445 uint8_t idxGroup; 446 uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);446 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup); 447 447 NOREF(idxGroup); 448 448 *(uint64_t *)(pabRegs + offReg) = uReg; … … 453 453 * Writes a 32-bit register with the exactly the supplied value. 454 454 * 455 * @param pThis The shared IOMMUdevice state.455 * @param pThis The shared DMAR device state. 456 456 * @param offReg The MMIO offset of the register. 457 457 * @param uReg The 32-bit value to write. 458 458 */ 459 DECLINLINE(void) iommuIntelRegWriteRaw32(PIOMMUpThis, uint16_t offReg, uint32_t uReg)459 DECLINLINE(void) dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg) 460 460 { 461 461 uint8_t idxGroup; 462 uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);462 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup); 463 463 NOREF(idxGroup); 464 464 *(uint32_t *)(pabRegs + offReg) = uReg; … … 469 469 * Reads a 64-bit register with exactly the value it contains. 470 470 * 471 * @param pThis The shared IOMMUdevice state.471 * @param pThis The shared DMAR device state. 472 472 * @param offReg The MMIO offset of the register. 473 473 * @param puReg Where to store the raw 64-bit register value. … … 475 475 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register. 476 476 */ 477 DECLINLINE(void) iommuIntelRegReadRaw64(PIOMMUpThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)477 DECLINLINE(void) dmarRegReadRaw64(PDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask) 478 478 { 479 479 uint8_t idxGroup; 480 uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);480 uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup); 481 481 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks)); 482 482 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup]; … … 491 491 * Reads a 32-bit register with exactly the value it contains. 492 492 * 493 * @param pThis The shared IOMMUdevice state.493 * @param pThis The shared DMAR device state. 494 494 * @param offReg The MMIO offset of the register. 495 495 * @param puReg Where to store the raw 32-bit register value. … … 497 497 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register. 498 498 */ 499 DECLINLINE(void) iommuIntelRegReadRaw32(PIOMMUpThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)499 DECLINLINE(void) dmarRegReadRaw32(PDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask) 500 500 { 501 501 uint8_t idxGroup; 502 uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);502 uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup); 503 503 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks)); 504 504 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup]; … … 514 514 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits. 515 515 * 516 * @param pThis The shared IOMMUdevice state.516 * @param pThis The shared DMAR device state. 517 517 * @param offReg The MMIO offset of the register. 518 518 * @param uReg The 64-bit value to write. 519 519 */ 520 static void iommuIntelRegWrite64(PIOMMUpThis, uint16_t offReg, uint64_t uReg)520 static void dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg) 521 521 { 522 522 /* Read current value from the 64-bit register. */ … … 524 524 uint64_t fRwMask; 525 525 uint64_t fRw1cMask; 526 iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);526 dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask); 527 527 528 528 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */ … … 532 532 533 533 /* Write new value to the 64-bit register. */ 534 iommuIntelRegWriteRaw64(pThis, offReg, uNewReg);534 dmarRegWriteRaw64(pThis, offReg, uNewReg); 535 535 } 536 536 … … 540 540 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits. 541 541 * 542 * @param pThis The shared IOMMUdevice state.542 * @param pThis The shared DMAR device state. 543 543 * @param offReg The MMIO offset of the register. 544 544 * @param uReg The 32-bit value to write. 545 545 */ 546 static void iommuIntelRegWrite32(PIOMMUpThis, uint16_t offReg, uint32_t uReg)546 static void dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg) 547 547 { 548 548 /* Read current value from the 32-bit register. */ … … 550 550 uint32_t fRwMask; 551 551 uint32_t fRw1cMask; 552 iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);552 dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask); 553 553 554 554 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */ … … 558 558 559 559 /* Write new value to the 32-bit register. */ 560 iommuIntelRegWriteRaw32(pThis, offReg, uNewReg);560 dmarRegWriteRaw32(pThis, offReg, uNewReg); 561 561 } 562 562 … … 566 566 * 567 567 * @returns The 64-bit register value. 568 * @param pThis The shared IOMMUdevice state.568 * @param pThis The shared DMAR device state. 569 569 * @param offReg The MMIO offset of the register. 570 570 */ 571 static uint64_t iommuIntelRegRead64(PIOMMUpThis, uint16_t offReg)571 static uint64_t dmarRegRead64(PDMAR pThis, uint16_t offReg) 572 572 { 573 573 uint64_t uCurReg; 574 574 uint64_t fRwMask; 575 575 uint64_t fRw1cMask; 576 iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);576 dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask); 577 577 NOREF(fRwMask); NOREF(fRw1cMask); 578 578 return uCurReg; … … 584 584 * 585 585 * @returns The 32-bit register value. 586 * @param pThis The shared IOMMUdevice state.586 * @param pThis The shared DMAR device state. 587 587 * @param offReg The MMIO offset of the register. 588 588 */ 589 static uint32_t iommuIntelRegRead32(PIOMMUpThis, uint16_t offReg)589 static uint32_t dmarRegRead32(PDMAR pThis, uint16_t offReg) 590 590 { 591 591 uint32_t uCurReg; 592 592 uint32_t fRwMask; 593 593 uint32_t fRw1cMask; 594 iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);594 dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask); 595 595 NOREF(fRwMask); NOREF(fRw1cMask); 596 596 return uCurReg; … … 661 661 * @callback_method_impl{FNIOMMMIONEWWRITE} 662 662 */ 663 static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)663 static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb) 664 664 { 665 665 RT_NOREF1(pvUser); 666 VTD_ASSERT_MMIO_ACCESS_RET(off, cb);667 668 P IOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);666 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb); 667 668 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 669 669 uint16_t const offReg = off; 670 670 uint16_t const offLast = offReg + cb - 1; 671 if ( VTD_IS_MMIO_OFF_VALID(offLast))671 if (DMAR_IS_MMIO_OFF_VALID(offLast)) 672 672 { 673 673 switch (off) … … 676 676 { 677 677 if (cb == 8) 678 iommuIntelRegWrite64(pThis, offReg, *(uint64_t *)pv);678 dmarRegWrite64(pThis, offReg, *(uint64_t *)pv); 679 679 else 680 iommuIntelRegWrite32(pThis, offReg, *(uint32_t *)pv);680 dmarRegWrite32(pThis, offReg, *(uint32_t *)pv); 681 681 break; 682 682 } … … 691 691 * @callback_method_impl{FNIOMMMIONEWREAD} 692 692 */ 693 static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)693 static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb) 694 694 { 695 695 RT_NOREF1(pvUser); 696 VTD_ASSERT_MMIO_ACCESS_RET(off, cb);697 698 P IOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);696 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb); 697 698 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 699 699 uint16_t const offReg = off; 700 700 uint16_t const offLast = offReg + cb - 1; 701 if ( VTD_IS_MMIO_OFF_VALID(offLast))701 if (DMAR_IS_MMIO_OFF_VALID(offLast)) 702 702 { 703 703 if (cb == 8) 704 *(uint64_t *)pv = iommuIntelRegRead64(pThis, offReg);704 *(uint64_t *)pv = dmarRegRead64(pThis, offReg); 705 705 else 706 *(uint32_t *)pv = iommuIntelRegRead32(pThis, offReg);706 *(uint32_t *)pv = dmarRegRead32(pThis, offReg); 707 707 return VINF_SUCCESS; 708 708 } … … 739 739 RT_NOREF(pCfg); 740 740 741 P IOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);742 P IOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);741 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 742 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3); 743 743 pThisR3->pDevInsR3 = pDevIns; 744 744 … … 780 780 781 781 /* Header. */ 782 PDMPciDevSetVendorId(pPciDev, VTD_PCI_VENDOR_ID); /* Intel */783 PDMPciDevSetDeviceId(pPciDev, VTD_PCI_DEVICE_ID); /* VirtualBox DMAR device */784 PDMPciDevSetRevisionId(pPciDev, VTD_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */782 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */ 783 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */ 784 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */ 785 785 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */ 786 786 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */ 787 787 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */ 788 PDMPciDevSetSubSystemId(pPciDev, VTD_PCI_DEVICE_ID);/* VirtualBox DMAR device */789 PDMPciDevSetSubSystemVendorId(pPciDev, VTD_PCI_VENDOR_ID);/* Intel */788 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */ 789 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */ 790 790 791 791 /** @todo VTD: Chipset spec says PCI Express Capability Id. Relevant for us? */ … … 821 821 * Register MMIO region. 822 822 */ 823 AssertCompile(!( VTD_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));824 rc = PDMDevHlpMmioCreateAndMap(pDevIns, VTD_MMIO_BASE_PHYSADDR, VTD_MMIO_SIZE, iommuIntelMmioWrite, iommuIntelMmioRead,823 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK)); 824 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead, 825 825 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, 826 826 "Intel-IOMMU", &pThis->hMmio); … … 838 838 { 839 839 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 840 P IOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);841 P IOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);840 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR); 841 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC); 842 842 pThisCC->CTX_SUFF(pDevIns) = pDevIns; 843 843 … … 847 847 848 848 /* Set up the MMIO RZ handlers. */ 849 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuIntelMmioWrite, iommuIntelMmioRead, NULL /* pvUser */);849 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */); 850 850 AssertRCReturn(rc, rc); 851 851 … … 884 884 /* .cMaxInstances = */ 1, 885 885 /* .uSharedVersion = */ 42, 886 /* .cbInstanceShared = */ sizeof( IOMMU),887 /* .cbInstanceCC = */ sizeof( IOMMUCC),888 /* .cbInstanceRC = */ sizeof( IOMMURC),886 /* .cbInstanceShared = */ sizeof(DMAR), 887 /* .cbInstanceCC = */ sizeof(DMARCC), 888 /* .cbInstanceRC = */ sizeof(DMARRC), 889 889 /* .cMaxPciDevices = */ 1, /** @todo Make this 0 if this isn't a PCI device. */ 890 890 /* .cMaxMsixVectors = */ 0, -
trunk/src/VBox/Devices/Bus/DevIommuIntel.h
r88332 r88342 25 25 26 26 /** Intel vendor ID for the DMAR unit. */ 27 #define VTD_PCI_VENDOR_ID0x808627 #define DMAR_PCI_VENDOR_ID 0x8086 28 28 /** VirtualBox DMAR unit's device ID. */ 29 #define VTD_PCI_DEVICE_ID0xc0de29 #define DMAR_PCI_DEVICE_ID 0xc0de 30 30 /** VirtualBox DMAR unit's device revision ID. */ 31 #define VTD_PCI_REVISION_ID0x0131 #define DMAR_PCI_REVISION_ID 0x01 32 32 33 33 /** Feature/capability flags exposed to the guest (x2APIC Opt Out until we get 34 34 * regular APIC setup working). */ 35 #define VTD_ACPI_DMAR_FLAGS(ACPI_DMAR_F_INTR_REMAP | ACPI_DMAR_F_X2APIC_OPT_OUT)35 #define DMAR_ACPI_DMAR_FLAGS (ACPI_DMAR_F_INTR_REMAP | ACPI_DMAR_F_X2APIC_OPT_OUT) 36 36 37 37 /** The MMIO base address of the DMAR unit (taken from real hardware). */ 38 #define VTD_MMIO_BASE_PHYSADDRUINT64_C(0xfed90000)38 #define DMAR_MMIO_BASE_PHYSADDR UINT64_C(0xfed90000) 39 39 /** The size of the MMIO region (in bytes). */ 40 #define VTD_MMIO_SIZE409640 #define DMAR_MMIO_SIZE 4096 41 41 42 42 #endif /* !VBOX_INCLUDED_SRC_Bus_DevIommuIntel_h */ -
trunk/src/VBox/Devices/PC/DevACPI.cpp
r88340 r88342 3382 3382 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits); 3383 3383 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1; 3384 VtdTable.Dmar.fFlags = VTD_ACPI_DMAR_FLAGS;3384 VtdTable.Dmar.fFlags = DMAR_ACPI_DMAR_FLAGS; 3385 3385 3386 3386 /* DRHD. */ 3387 3387 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD) /* + sizeof(VtdTable.DevScope) */; 3388 3388 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL; 3389 VtdTable.Drhd.uRegBaseAddr = VTD_MMIO_BASE_PHYSADDR;3389 VtdTable.Drhd.uRegBaseAddr = DMAR_MMIO_BASE_PHYSADDR; 3390 3390 3391 3391 /* Finally, compute checksum. */
Note:
See TracChangeset
for help on using the changeset viewer.
