Changeset 89553 in vbox for trunk/src/VBox/Devices

Timestamp:

Jun 8, 2021 5:42:46 AM (4 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Use uint16_t since the page table entity index is at most 11 bits (for all levels).

File:

• trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (3 diffs)

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -2162 +2162 @@
     Assert(   pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
            || pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
+    Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
 
     /* Mask of valid paging entry bits. */
@@ -2196 +2197 @@
         uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
         {
-            uint64_t const idxPte         = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
-            uint64_t const offPte         = idxPte << 3;
-            RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_BASE_MASK) | offPte;
+            uint16_t const idxPte         = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
+            uint16_t const offPte         = idxPte << 3;
+            RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) | offPte;
             int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
             if (RT_SUCCESS(rc))
@@ -2466 +2467 @@
                                             pMemReqAux->cPagingLevel = cPagingLevel;
                                             pMemReqAux->GCPhysSlPt   = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
-                                            Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_OFFSET_MASK));
                                             return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
                                         }