Changeset 90363 in vbox for trunk/src/VBox/Devices/PC/DevIoApic.cpp

Timestamp:

Jul 27, 2021 9:59:18 PM (4 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

145936

Message:

DevIoApic: Comment update for flip-flip case. bugref:10073

File:

• trunk/src/VBox/Devices/PC/DevIoApic.cpp (modified) (2 diffs)

trunk/src/VBox/Devices/PC/DevIoApic.cpp

@@ -262 +262 @@
     /** The IRQ tags and source IDs for each pin (tracing purposes). */
     uint32_t                au32TagSrc[IOAPIC_NUM_INTR_PINS];
-    /** Bitmap keeping the flip-flop-ness of pending interrupts. */
+    /** Bitmap keeping the flip-flop-ness of pending interrupts.
+     * The information held here is only relevan between SetIrq and the
+     * delivery, thus no real need to initialize or reset this. */
     uint64_t                bmFlipFlop[(IOAPIC_NUM_INTR_PINS + 63) / 64];
 
@@ -1004 +1006 @@
              * after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
              * hence just the assert is done.
-             */
+             *
+             * Update @bugref{10073}: We now de-assert the interrupt line once it has been
+             * delivered to the APIC to prevent it from getting re-delivered by accident (e.g.
+             * on RTE write or by buggy EOI code).  The XT-PIC works differently because of the
+             * INTA, so it's set IRQ function will do what's described above: first lower the
+             * interrupt line and then immediately raising it again, leaving the IRR flag set
+             * most of the time.  (How a real HPET/IOAPIC does this is a really good question
+             * and would be observable if we could get at the IRR register of the IOAPIC...
+             * Maybe by modifying the RTE? Our code will retrigger the interrupt that way.) */
             ASMBitSet(pThis->bmFlipFlop, idxRte);
             IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, true);