- Timestamp:
- Sep 24, 2021 9:49:20 AM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 147028
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r91357 r91358 3337 3337 3338 3338 /* Make sure the write-back cacheable memory type for EPT is supported. */ 3339 if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_ EMT_WB)))3339 if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB))) 3340 3340 { 3341 3341 pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED; … … 5889 5889 ("EPTP %#RX64\n", pVmcsInfo->HCPhysEPTP)); 5890 5890 AssertMsg( !((pVmcsInfo->HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */ 5891 || (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_ EPT_ACCESS_DIRTY),5891 || (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY), 5892 5892 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVmcsInfo->HCPhysEPTP)); 5893 5893 -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r91356 r91358 1462 1462 uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_RWX_X_ONLY); 1463 1463 uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4); 1464 uint8_t const f EptMemUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_UC);1465 uint8_t const f EptMemWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_WB);1464 uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC); 1465 uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB); 1466 1466 uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M); 1467 1467 uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G); 1468 1468 uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT); 1469 uint8_t const f EptAccDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY);1469 uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); 1470 1470 uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX); 1471 1471 uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX); … … 1476 1476 pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_RWX_X_ONLY, fExecOnly) 1477 1477 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4) 1478 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ EMT_UC, fEptMemUc)1479 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ EMT_WB, fEptMemWb)1478 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc) 1479 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb) 1480 1480 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage) 1481 1481 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage) 1482 1482 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept) 1483 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ EPT_ACCESS_DIRTY, fEptAccDirty)1484 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT ,0)1483 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, fAccessDirty) 1484 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0) 1485 1485 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0) 1486 1486 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle) -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r91343 r91358 1399 1399 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4); 1400 1400 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5); 1401 HMVMX_REPORT_MSR_CAP(fCaps, " EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);1402 HMVMX_REPORT_MSR_CAP(fCaps, " EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);1401 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC); 1402 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB); 1403 1403 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M); 1404 1404 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G); 1405 1405 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT); 1406 HMVMX_REPORT_MSR_CAP(fCaps, " EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);1407 HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT ", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);1406 HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY); 1407 HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION); 1408 1408 HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK); 1409 1409 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
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