Changeset 9212 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

May 29, 2008 9:38:38 AM (17 years ago)

Author:

vboxsync

Message:

Major changes for sizeof(RTGCPTR) == uint64_t.
Introduced RCPTRTYPE for pointers valid in raw mode only (RTGCPTR32).

Disabled by default. Enable by adding VBOX_WITH_64_BITS_GUESTS to your LocalConfig.kmk.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• DBGFR0.cpp (modified) (1 diff)
• HWSVMR0.cpp (modified) (2 diffs)
• HWVMXR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/DBGFR0.cpp

@@ -45 +45 @@
  * @param   uDr6        The DR6 register value.
  */
-DBGFR0DECL(int) DBGFR0Trap01Handler(PVM pVM, PCPUMCTXCORE pRegFrame, RTUINTREG uDr6)
+DBGFR0DECL(int) DBGFR0Trap01Handler(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6)
 {
     /** @todo Intel docs say that X86_DR6_BS has the highest priority... */

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -681 +681 @@
     pVMCB->guest.u64RAX    = pCtx->eax;
 
-    /* vmrun will fail otherwise. */
-    pVMCB->guest.u64EFER   = MSR_K6_EFER_SVME;
+    /* vmrun will fail without MSR_K6_EFER_SVME. */
+    pVMCB->guest.u64EFER   = pCtx->msrEFER | MSR_K6_EFER_SVME;
 
     /** TSC offset. */
@@ -696 +696 @@
     }
 
-    /** @todo 64 bits stuff (?):
-     * - STAR
-     * - LSTAR
-     * - CSTAR
-     * - SFMASK
-     * - KernelGSBase
-     */
+    /* Sync the various msrs for 64 bits mode. */
+    pVMCB->guest.u64STAR            = pCtx->msrSTAR;            /* legacy syscall eip, cs & ss */
+    pVMCB->guest.u64LSTAR           = pCtx->msrLSTAR;           /* 64 bits mode syscall rip */
+    pVMCB->guest.u64CSTAR           = pCtx->msrCSTAR;           /* compatibility mode syscall rip */
+    pVMCB->guest.u64SFMASK          = pCtx->msrSFMASK;          /* syscall flag mask */
+    pVMCB->guest.u64KernelGSBase    = pCtx->msrKERNELGSBASE;    /* swapgs exchange value */
 
 #ifdef DEBUG

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -273 +273 @@
     AssertRC(rc);
 
-    /* VMX_VMCS_CTRL_ENTRY_CONTROLS
-     * Set required bits to one and zero according to the MSR capabilities.
-     */
-    val  = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
-    if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
-    {
-        /** @todo 32 bits guest mode only for now. */
-        /* val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
-    }
-    /* Mask away the bits that the CPU doesn't support */
-    /** @todo make sure they don't conflict with the above requirements. */
-    val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
-    /* else Must be zero when AMD64 is not available. */
-    rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
-    AssertRC(rc);
-
     /* VMX_VMCS_CTRL_EXIT_CONTROLS
      * Set required bits to one and zero according to the MSR capabilities.
@@ -958 +942 @@
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
     }
+
+    /* VMX_VMCS_CTRL_ENTRY_CONTROLS
+     * Set required bits to one and zero according to the MSR capabilities.
+     */
+    val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
+
+    /* 64 bits guest mode? */
+    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
+        val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
+
+    /* Mask away the bits that the CPU doesn't support */
+    /** @todo make sure they don't conflict with the above requirements. */
+    val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
+    /* else Must be zero when AMD64 is not available. */
+    rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
+    AssertRC(rc);
 
     /* Done. */