Changeset 96731 in vbox
- Timestamp:
- Sep 14, 2022 9:21:03 AM (2 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
-
VMMAll/IEMAllAImpl.asm (modified) (1 diff)
-
VMMAll/IEMAllAImplC.cpp (modified) (1 diff)
-
VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (2 diffs)
-
include/IEMInternal.h (modified) (2 diffs)
-
include/IEMMc.h (modified) (1 diff)
-
testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r96726 r96731 5589 5589 EPILOGUE_4_ARGS 5590 5590 ENDPROC iemAImpl_cvtsd2si_i64_r64 5591 5592 5593 ;; 5594 ; cvttss2si instruction - 32-bit variant. 5595 ; 5596 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5597 ; @param A1 Where to return the MXCSR value. 5598 ; @param A2 Pointer to the result operand (output). 5599 ; @param A3 Pointer to the second operand (input). 5600 ; 5601 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i32_r32, 16 5602 PROLOGUE_4_ARGS 5603 IEMIMPL_SSE_PROLOGUE 5604 SSE_LD_FXSTATE_MXCSR A0 5605 5606 cvttss2si T0_32, [A3] 5607 mov dword [A2], T0_32 5608 5609 SSE_ST_FXSTATE_MXCSR_ONLY A1, A0 5610 IEMIMPL_SSE_PROLOGUE 5611 EPILOGUE_4_ARGS 5612 ENDPROC iemAImpl_cvttss2si_i32_r32 5613 5614 ;; 5615 ; cvttss2si instruction - 64-bit variant. 5616 ; 5617 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5618 ; @param A1 Where to return the MXCSR value. 5619 ; @param A2 Pointer to the result operand (output). 5620 ; @param A3 Pointer to the second operand (input). 5621 ; 5622 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i64_r32, 16 5623 PROLOGUE_4_ARGS 5624 IEMIMPL_SSE_PROLOGUE 5625 SSE_LD_FXSTATE_MXCSR A0 5626 5627 cvttss2si T0, [A3] 5628 mov qword [A2], T0 5629 5630 SSE_ST_FXSTATE_MXCSR_ONLY A1, A0 5631 IEMIMPL_SSE_PROLOGUE 5632 EPILOGUE_4_ARGS 5633 ENDPROC iemAImpl_cvttss2si_i64_r32 5634 5635 5636 ;; 5637 ; cvtss2si instruction - 32-bit variant. 5638 ; 5639 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5640 ; @param A1 Where to return the MXCSR value. 5641 ; @param A2 Pointer to the result operand (output). 5642 ; @param A3 Pointer to the second operand (input). 5643 ; 5644 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i32_r32, 16 5645 PROLOGUE_4_ARGS 5646 IEMIMPL_SSE_PROLOGUE 5647 SSE_LD_FXSTATE_MXCSR A0 5648 5649 cvtss2si T0_32, [A3] 5650 mov dword [A2], T0_32 5651 5652 SSE_ST_FXSTATE_MXCSR_ONLY A1, A0 5653 IEMIMPL_SSE_PROLOGUE 5654 EPILOGUE_4_ARGS 5655 ENDPROC iemAImpl_cvtss2si_i32_r32 5656 5657 ;; 5658 ; cvtss2si instruction - 64-bit variant. 5659 ; 5660 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5661 ; @param A1 Where to return the MXCSR value. 5662 ; @param A2 Pointer to the result operand (output). 5663 ; @param A3 Pointer to the second operand (input). 5664 ; 5665 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i64_r32, 16 5666 PROLOGUE_4_ARGS 5667 IEMIMPL_SSE_PROLOGUE 5668 SSE_LD_FXSTATE_MXCSR A0 5669 5670 cvtss2si T0, [A3] 5671 mov qword [A2], T0 5672 5673 SSE_ST_FXSTATE_MXCSR_ONLY A1, A0 5674 IEMIMPL_SSE_PROLOGUE 5675 EPILOGUE_4_ARGS 5676 ENDPROC iemAImpl_cvtss2si_i64_r32 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r96726 r96731 16061 16061 } 16062 16062 #endif 16063 16064 16065 /** 16066 * CVTTSS2SI 16067 */ 16068 #ifdef IEM_WITHOUT_ASSEMBLY 16069 IEM_DECL_IMPL_DEF(void, iemAImpl_cvttss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)) 16070 { 16071 RTFLOAT32U r32Src; 16072 16073 r32Src.u = *pu32Src; 16074 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */ 16075 16076 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR); 16077 *pi32Dst = f32_to_i32_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState); 16078 *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 16079 } 16080 16081 16082 IEM_DECL_IMPL_DEF(void, iemAImpl_cvttss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)) 16083 { 16084 RTFLOAT32U r32Src; 16085 16086 r32Src.u = *pu32Src; 16087 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */ 16088 16089 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR); 16090 *pi64Dst = f32_to_i64_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState); 16091 *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 16092 } 16093 #endif 16094 16095 16096 /** 16097 * CVTSS2SI 16098 */ 16099 #ifdef IEM_WITHOUT_ASSEMBLY 16100 IEM_DECL_IMPL_DEF(void, iemAImpl_cvtss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)) 16101 { 16102 RTFLOAT32U r32Src; 16103 16104 r32Src.u = *pu32Src; 16105 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */ 16106 16107 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR); 16108 *pi32Dst = f32_to_i32(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState); 16109 *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 16110 } 16111 16112 16113 IEM_DECL_IMPL_DEF(void, iemAImpl_cvtss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)) 16114 { 16115 RTFLOAT32U r32Src; 16116 16117 r32Src.u = *pu32Src; 16118 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */ 16119 16120 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR); 16121 *pi64Dst = f32_to_i64(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState); 16122 *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 16123 } 16124 #endif 16125 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r96726 r96731 3676 3676 /** Opcode 0x66 0x0f 0x2c - cvttpd2pi Ppi, Wpd */ 3677 3677 FNIEMOP_STUB(iemOp_cvttpd2pi_Ppi_Wpd); 3678 3679 3678 3680 /** Opcode 0xf3 0x0f 0x2c - cvttss2si Gy, Wss */ 3679 FNIEMOP_STUB(iemOp_cvttss2si_Gy_Wss); 3681 FNIEMOP_DEF(iemOp_cvttss2si_Gy_Wss) 3682 { 3683 IEMOP_MNEMONIC2(RM, CVTTSS2SI, cvttss2si, Gy, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 3684 3685 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 3686 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3687 { 3688 if (IEM_IS_MODRM_REG_MODE(bRm)) 3689 { 3690 /* greg64, XMM */ 3691 IEM_MC_BEGIN(3, 4); 3692 IEM_MC_LOCAL(uint32_t, fMxcsr); 3693 IEM_MC_LOCAL(int64_t, i64Dst); 3694 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3695 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 3696 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 3697 3698 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3699 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3700 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3701 3702 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3703 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 3704 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3705 IEM_MC_IF_MXCSR_XCPT_PENDING() 3706 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3707 IEM_MC_ELSE() 3708 IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3709 IEM_MC_ENDIF(); 3710 3711 IEM_MC_ADVANCE_RIP(); 3712 IEM_MC_END(); 3713 } 3714 else 3715 { 3716 /* greg64, [mem64] */ 3717 IEM_MC_BEGIN(3, 4); 3718 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3719 IEM_MC_LOCAL(uint32_t, fMxcsr); 3720 IEM_MC_LOCAL(int64_t, i64Dst); 3721 IEM_MC_LOCAL(uint32_t, u32Src); 3722 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3723 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 3724 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 3725 3726 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3727 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3728 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3729 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3730 3731 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3732 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 3733 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3734 IEM_MC_IF_MXCSR_XCPT_PENDING() 3735 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3736 IEM_MC_ELSE() 3737 IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3738 IEM_MC_ENDIF(); 3739 3740 IEM_MC_ADVANCE_RIP(); 3741 IEM_MC_END(); 3742 } 3743 } 3744 else 3745 { 3746 if (IEM_IS_MODRM_REG_MODE(bRm)) 3747 { 3748 /* greg, XMM */ 3749 IEM_MC_BEGIN(3, 4); 3750 IEM_MC_LOCAL(uint32_t, fMxcsr); 3751 IEM_MC_LOCAL(int32_t, i32Dst); 3752 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3753 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 3754 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 3755 3756 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3757 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3758 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3759 3760 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3761 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 3762 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3763 IEM_MC_IF_MXCSR_XCPT_PENDING() 3764 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3765 IEM_MC_ELSE() 3766 IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3767 IEM_MC_ENDIF(); 3768 3769 IEM_MC_ADVANCE_RIP(); 3770 IEM_MC_END(); 3771 } 3772 else 3773 { 3774 /* greg, [mem] */ 3775 IEM_MC_BEGIN(3, 4); 3776 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3777 IEM_MC_LOCAL(uint32_t, fMxcsr); 3778 IEM_MC_LOCAL(int32_t, i32Dst); 3779 IEM_MC_LOCAL(uint32_t, u32Src); 3780 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3781 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 3782 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 3783 3784 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3785 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3786 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3787 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3788 3789 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3790 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 3791 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3792 IEM_MC_IF_MXCSR_XCPT_PENDING() 3793 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3794 IEM_MC_ELSE() 3795 IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3796 IEM_MC_ENDIF(); 3797 3798 IEM_MC_ADVANCE_RIP(); 3799 IEM_MC_END(); 3800 } 3801 } 3802 return VINF_SUCCESS; 3803 } 3680 3804 3681 3805 … … 3810 3934 /** Opcode 0x66 0x0f 0x2d - cvtpd2pi Qpi, Wpd */ 3811 3935 FNIEMOP_STUB(iemOp_cvtpd2pi_Qpi_Wpd); 3936 3937 3812 3938 /** Opcode 0xf3 0x0f 0x2d - cvtss2si Gy, Wss */ 3813 FNIEMOP_STUB(iemOp_cvtss2si_Gy_Wss); 3939 FNIEMOP_DEF(iemOp_cvtss2si_Gy_Wss) 3940 { 3941 IEMOP_MNEMONIC2(RM, CVTSS2SI, cvtss2si, Gy, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 3942 3943 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 3944 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) 3945 { 3946 if (IEM_IS_MODRM_REG_MODE(bRm)) 3947 { 3948 /* greg64, XMM */ 3949 IEM_MC_BEGIN(3, 4); 3950 IEM_MC_LOCAL(uint32_t, fMxcsr); 3951 IEM_MC_LOCAL(int64_t, i64Dst); 3952 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3953 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 3954 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 3955 3956 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3957 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3958 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3959 3960 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3961 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 3962 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3963 IEM_MC_IF_MXCSR_XCPT_PENDING() 3964 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3965 IEM_MC_ELSE() 3966 IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3967 IEM_MC_ENDIF(); 3968 3969 IEM_MC_ADVANCE_RIP(); 3970 IEM_MC_END(); 3971 } 3972 else 3973 { 3974 /* greg64, [mem64] */ 3975 IEM_MC_BEGIN(3, 4); 3976 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3977 IEM_MC_LOCAL(uint32_t, fMxcsr); 3978 IEM_MC_LOCAL(int64_t, i64Dst); 3979 IEM_MC_LOCAL(uint32_t, u32Src); 3980 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3981 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 3982 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 3983 3984 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3985 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3986 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3987 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 3988 3989 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3990 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 3991 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3992 IEM_MC_IF_MXCSR_XCPT_PENDING() 3993 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 3994 IEM_MC_ELSE() 3995 IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 3996 IEM_MC_ENDIF(); 3997 3998 IEM_MC_ADVANCE_RIP(); 3999 IEM_MC_END(); 4000 } 4001 } 4002 else 4003 { 4004 if (IEM_IS_MODRM_REG_MODE(bRm)) 4005 { 4006 /* greg, XMM */ 4007 IEM_MC_BEGIN(3, 4); 4008 IEM_MC_LOCAL(uint32_t, fMxcsr); 4009 IEM_MC_LOCAL(int32_t, i32Dst); 4010 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4011 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4012 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 4013 4014 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4015 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4016 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 4017 4018 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4019 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4020 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4021 IEM_MC_IF_MXCSR_XCPT_PENDING() 4022 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4023 IEM_MC_ELSE() 4024 IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 4025 IEM_MC_ENDIF(); 4026 4027 IEM_MC_ADVANCE_RIP(); 4028 IEM_MC_END(); 4029 } 4030 else 4031 { 4032 /* greg, [mem] */ 4033 IEM_MC_BEGIN(3, 4); 4034 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4035 IEM_MC_LOCAL(uint32_t, fMxcsr); 4036 IEM_MC_LOCAL(int32_t, i32Dst); 4037 IEM_MC_LOCAL(uint32_t, u32Src); 4038 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4039 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4040 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 4041 4042 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4043 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4044 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4045 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */ 4046 4047 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4048 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4049 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4050 IEM_MC_IF_MXCSR_XCPT_PENDING() 4051 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4052 IEM_MC_ELSE() 4053 IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 4054 IEM_MC_ENDIF(); 4055 4056 IEM_MC_ADVANCE_RIP(); 4057 IEM_MC_END(); 4058 } 4059 } 4060 return VINF_SUCCESS; 4061 } 3814 4062 3815 4063 -
trunk/src/VBox/VMM/include/IEMInternal.h
r96726 r96731 2298 2298 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */ 2299 2299 typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64; 2300 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */ 2301 typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32; 2302 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */ 2303 typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32; 2300 2304 2301 2305 FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64; … … 2304 2308 FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64; 2305 2309 FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64; 2310 2311 FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32; 2312 FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32; 2313 2314 FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32; 2315 FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32; 2306 2316 2307 2317 /** @} */ -
trunk/src/VBox/VMM/include/IEMMc.h
r96723 r96731 477 477 #define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \ 478 478 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)]) 479 #define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \ 480 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]) 479 481 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \ 480 482 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]) -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r96723 r96731 742 742 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 743 743 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 744 #define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 744 745 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fSseWrite; (void)fMcBegin; } while (0) 745 746 #define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) do { (a_pr32Dst) = (RTFLOAT32U const *)((uintptr_t)0); CHK_PTYPE(RTFLOAT32U const *, a_pr32Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
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