Changeset 9690 in vbox

Timestamp:

Jun 13, 2008 3:51:14 PM (17 years ago)

Author:

vboxsync

Message:

Paging updates for amd64.

Location:

trunk/src/VBox/VMM

Files:

• PGMInternal.h (modified) (4 diffs)
• VMMAll/PGMAll.cpp (modified) (1 diff)
• VMMAll/PGMAllBth.h (modified) (8 diffs)
• VMMAll/PGMAllPool.cpp (modified) (10 diffs)
• VMMAll/PGMAllShw.h (modified) (1 diff)

trunk/src/VBox/VMM/PGMInternal.h

@@ -1279 +1279 @@
 /** The extended PAE page directory (2048 entries, works as root currently). */
 #define PGMPOOL_IDX_PAE_PD      2
- /** PAE Page Directory Table 0. */
+/** PAE Page Directory Table 0. */
 #define PGMPOOL_IDX_PAE_PD_0    3
- /** PAE Page Directory Table 1. */
+/** PAE Page Directory Table 1. */
 #define PGMPOOL_IDX_PAE_PD_1    4
- /** PAE Page Directory Table 2. */
+/** PAE Page Directory Table 2. */
 #define PGMPOOL_IDX_PAE_PD_2    5
- /** PAE Page Directory Table 3. */
+/** PAE Page Directory Table 3. */
 #define PGMPOOL_IDX_PAE_PD_3    6
+/** AMD64 Page Directory Table. */
+#define PGMPOOL_IDX_AMD64_PD    7
 /** Page Directory Pointer Table (PAE root, not currently used). */
-#define PGMPOOL_IDX_PDPT        7
+#define PGMPOOL_IDX_PDPT        8
 /** Page Map Level-4 (64-bit root). */
-#define PGMPOOL_IDX_PML4        8
+#define PGMPOOL_IDX_PML4        9
 /** The first normal index. */
-#define PGMPOOL_IDX_FIRST       9
+#define PGMPOOL_IDX_FIRST       10
 /** The last valid index. (inclusive, 14 bits) */
 #define PGMPOOL_IDX_LAST        0x3fff
@@ -1309 +1311 @@
     uint16_t            iNext;
     /** The user page index. */
-    uint16_t            iUser;
+    uint32_t            iUser;
     /** Index into the user table. */
-    uint16_t            iUserTable;
+    uint32_t            iUserTable;
 } PGMPOOLUSER, *PPGMPOOLUSER;
 typedef const PGMPOOLUSER *PCPGMPOOLUSER;
@@ -1369 +1371 @@
     /** Shw: 64-bit page directory pointer table;   Gst: 64-bit page directory pointer table. */
     PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
+    /** Shw: 64-bit page directory table;   Gst: 64-bit page directory table. */
+    PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
 
     /** Shw: Root 32-bit page directory. */
@@ -2623 +2627 @@
 void           *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
 #endif
-int             pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
+int             pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
 PPGMPOOLPAGE    pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
-void            pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
-void            pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
+void            pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
+void            pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
 int             pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
 void            pgmPoolFlushAll(PVM pVM);

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -779 +779 @@
 
         Assert(!(pPdpe->u & X86_PDPE_PG_MASK));
-        rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOL_IDX_PDPT, iPdPt, &pShwPage);
+        rc = pgmPoolAlloc(pVM, pPdptGst->a[iPdPt].u & X86_PDPE_PG_MASK, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD, PGMPOOL_IDX_PDPT, iPml4e * X86_PG_PAE_ENTRIES + iPdPt, &pShwPage);
         if (rc == VERR_PGM_POOL_FLUSHED)
             return VINF_PGM_SYNC_CR3;

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -2153 +2153 @@
     PX86PDPAE       pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
+    const unsigned  iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
+    const unsigned  iPdPte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     const unsigned  iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PX86PDPAE       pPDDst;
@@ -2166 +2168 @@
     PSHWPDE         pPdeDst = &pPDDst->a[iPDDst];
     SHWPDE          PdeDst = *pPdeDst;
+
+    /* Calculate unique identifier for the PD pool allocations. */
+# if PGM_SHW_TYPE == PGM_TYPE_AMD64
+    const unsigned iPoolIdx = (iPml4e * X86_PG_PAE_ENTRIES + iPdPte) * X86_PG_PAE_ENTRIES + iPDDst;
+# else
+    const unsigned iPoolIdx = iPDDst;
+# endif
 
 # ifndef PGM_WITHOUT_MAPPINGS
@@ -2227 +2236 @@
             GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
 # endif
-            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
+            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPoolIdx, &pShwPage);
         }
         else
@@ -2236 +2245 @@
             GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
 # endif
-            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
+            rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPoolIdx, &pShwPage);
         }
         if (rc == VINF_SUCCESS)
@@ -3008 +3017 @@
                                 && !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
                             {
-                                pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDDst->a[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
+                                AssertCompile(PGMPOOL_IDX_AMD64_PD == SHW_POOL_ROOT_IDX);
+                                pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDDst->a[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_AMD64_PD, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
                                 pPDDst->a[iPD].u = 0;
                             }
                         }
 
-                        pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPDPTE);
+                        pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPML4E * X86_PG_PAE_ENTRIES + iPDPTE);
                         pPdptDst->a[iPDPTE].u = 0;
                     }
@@ -3071 +3081 @@
                         {
 #   if PGM_GST_TYPE == PGM_TYPE_AMD64
-                            pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
+                            pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
 #   else
-                            pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
+                            pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
 #   endif
                             pPDEDst[iPD].u = 0;
@@ -3084 +3094 @@
                     if (!(pPdptDst->a[iPDPTE].u & PGM_PLXFLAGS_PERMANENT))
                     {
-                        pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPDPTE);
+#   if PGM_GST_TYPE == PGM_TYPE_AMD64
+                        pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPML4E * X86_PG_PAE_ENTRIES + iPDPTE);
+#   else
+                        AssertFailed(); /* can't happen; the 4 pdpt pages are fixed! */
+#   endif
                         pPdptDst->a[iPDPTE].u = 0;
                     }
@@ -3162 +3176 @@
 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                     for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
-#  elif PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
+#  elif PGM_GST_TYPE == PGM_TYPE_PAE
                     const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
+#  elif PGM_GST_TYPE == PGM_TYPE_AMD64
+                    const unsigned iPdShw = iPD + (iPDPTE + iPML4E * X86_PG_PAE_ENTRIES) * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
 #  else
                     const unsigned iPdShw = iPD; NOREF(iPdShw);

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -55 +55 @@
 #endif
 #ifdef PGMPOOL_WITH_CACHE
-static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
+static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
 #endif
 #ifdef PGMPOOL_WITH_MONITORING
@@ -1047 +1047 @@
  * @param   ppPage      Where to store the pointer to the page.
  */
-static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage)
+static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
 {
 #ifndef IN_GC
@@ -1816 +1816 @@
  * @param   iUserTable  The user table index.
  */
-DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint16_t iUserTable)
+DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
 {
     int rc = VINF_SUCCESS;
@@ -1906 +1906 @@
  * @param   iUserTable  The user table.
  */
-static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable)
+static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
 {
     PPGMPOOLUSER paUsers = pPool->CTXSUFF(paUsers);
@@ -1970 +1970 @@
  * @param   iUserTable  The index into the user table (shadowed).
  */
-static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable)
+static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
 {
     /*
@@ -2393 +2393 @@
             Assert(pUser->iUserTable < X86_PG_PAE_ENTRIES);
             break;
+        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
+            Assert(!(u.pau64[pUser->iUser] & PGM_PDFLAGS_MAPPING));
+            Assert(pUser->iUserTable < X86_PG_PAE_ENTRIES*X86_PG_PAE_ENTRIES && pUser->iUser == PGMPOOL_IDX_PDPT);
+            break;
         case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
+            Assert(!(u.pau64[pUser->iUserTable] & PGM_PLXFLAGS_PERMANENT));
+            Assert(pUser->iUserTable < X86_PG_PAE_ENTRIES && pUser->iUser == PGMPOOL_IDX_PML4);
+            break;
         case PGMPOOLKIND_ROOT_PML4:
             Assert(!(u.pau64[pUser->iUserTable] & PGM_PLXFLAGS_PERMANENT));
@@ -3197 +3204 @@
         paUsers[i].iNext = i + 1;
         paUsers[i].iUser = NIL_PGMPOOL_IDX;
-        paUsers[i].iUserTable = 0xfffe;
+        paUsers[i].iUserTable = 0xfffffffe;
     }
     paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
@@ -3374 +3381 @@
  * @param   iUserTable  The index into the user table (shadowed).
  */
-void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable)
+void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
 {
     STAM_PROFILE_START(&pPool->StatFree, a);
@@ -3459 +3466 @@
  * @param   ppPage      Where to store the pointer to the page. NULL is stored here on failure.
  */
-int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage)
+int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
 {
     PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
@@ -3579 +3586 @@
  * @param   iUserTable  The index into the user table (shadowed).
  */
-void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable)
+void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
 {
     LogFlow(("pgmPoolFree: HCPhys=%VHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -78 +78 @@
 # define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
 # define SHW_TOTAL_PD_ENTRIES   (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
-# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PML4
+# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_AMD64_PD
 #else /* 32 bits PAE mode */
 # define SHW_PDPT_SHIFT        X86_PDPT_SHIFT